001 /*
002 * This file is part of the Jikes RVM project (http://jikesrvm.org).
003 *
004 * This file is licensed to You under the Eclipse Public License (EPL);
005 * You may not use this file except in compliance with the License. You
006 * may obtain a copy of the License at
007 *
008 * http://www.opensource.org/licenses/eclipse-1.0.php
009 *
010 * See the COPYRIGHT.txt file distributed with this work for information
011 * regarding copyright ownership.
012 */
013 package org.jikesrvm.compilers.common.assembler.ia32;
014
015 import org.jikesrvm.*;
016 import org.jikesrvm.runtime.Magic;
017 import org.jikesrvm.compilers.baseline.ia32.BaselineCompilerImpl;
018 import org.jikesrvm.ia32.OutOfLineMachineCode;
019 import org.jikesrvm.ia32.RegisterConstants;
020 import org.jikesrvm.compilers.common.assembler.ForwardReference;
021 import org.jikesrvm.compilers.common.assembler.AbstractAssembler;
022 import static org.jikesrvm.ia32.RegisterConstants.GPR;
023
024 import org.vmmagic.pragma.*;
025 import org.vmmagic.unboxed.*;
026
027 /**
028 * <P> This class is the low-level assembler for Intel; it contains
029 * functionality for encoding specific instructions into an array of
030 * bytes. It consists of three parts: </P>
031 * <UL>
032 * <LI> Some support that handles common operations for generating
033 * any IA32 instruction, such as encoding the operands into the
034 * ModRM and SIB bytes
035 * <LI> Some hand-coded methods that emit instructions with
036 * distinctive formats or with special consistency requirements,
037 * such as FXCH or CMOV
038 * <LI> Machine-generated methods that emit instructions with
039 * relatively standard formats, such as binary accumulation
040 * instructions like ADD and SUB.
041 * </UL>
042 * <P> This assembler provides a direct interface to the IA32 ISA: it
043 * contains emit methods that generate specific IA32 opcodes, and each
044 * emit method specifies the addressing modes and operand sizes that
045 * it expects. Thus, it has an emit method that generates an ADD of a
046 * register-displacement operand and an immediate operand. It is the
047 * job of the client to determine the addressing modes, operand
048 * sizes and exact opcodes that it desires. </P>
049 *
050 * <P> This assembler does provide support for forward branches. It
051 * is permitted to specify a branch operand as an arbitrary label, and
052 * later to inform the assembler to which instruction this label
053 * refers. The assembler, when informed to what the label refers,
054 * will go back and generate the appropriate offsets for all branches
055 * that refer to the given label. The mechanism is implemented by the
056 * following methods and helper classes:
057 * <UL>
058 * <LI> {@link #forwardRefs}
059 * <LI> {@link #resolveForwardReferences}
060 * <LI> {@link #patchUnconditionalBranch}
061 * <LI> {@link #patchConditionalBranch}
062 * <LI> {@link #emitJCC_Cond_Label}
063 * <LI> {@link #emitJMP_Label}
064 * <LI> {@link #emitCALL_Label}
065 * <LI> {@link ForwardReference}
066 * </UL>
067 * </P>
068 *
069 * <P> There is also support for generating tableswitches. This
070 * consists providing support for storing tables of relative addresses
071 * that can be used to compute the target of a tableswitch. This
072 * support assumes a particular code sequence for tableswitches
073 * (followed by baseline and optimizing compilers). See {@link
074 * #emitOFFSET_Imm_ImmOrLabel} for details. </P>
075 *
076 * <P> The automatically-generated emit methods of this assembler
077 * exploit regularities in the IA32 binary encoding; for example,
078 * several instructions (ADD, ADC, SUB, AND, OR, XOR) can be
079 * classified as binary accumulators that share a common set of
080 * permitted addressing modes and binary encoding all the way down a
081 * special case for enconding operands EAX and an immediate. A shell
082 * script (genAssembler.sh in the intel assembler source directory)
083 * explots this by specifying a generic way of emtting a binary
084 * accumulation and then calling it for each specific opcode that fits
085 * that format. These generated methods are combined with the
086 * hand-coded ones (from Assembler.in, also in the assembler
087 * source directory) as part of the Jikes RVM build process. </P>
088 *
089 * <P> This assembler is shared by the baseline and optimizing
090 * compilers: it used directly by the baseline compiler, while the
091 * optimizing compiler has an {@link org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt}
092 * that is built on top of this one to match
093 * {@link org.jikesrvm.compilers.opt.ir.Instruction}s and
094 * {@link org.jikesrvm.compilers.opt.ir.Operator}s to the emit methods
095 * this assembler provides. The {@link org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt}
096 * is entirely machine-generated, and this
097 * requires that the methods for encoding instructions use a stylized
098 * naming and signiture convention that is designed to make the method
099 * signiture computable from the opcode and the operand types. The
100 * naming convention is as follows:
101 *
102 * <PRE>
103 * final void emit<EM>opcode</EM>\(_<EM>operand code</EM>\)*[_<EM>size</EM>](\(<EM>operand arguments</EM>\)*)
104 * </PRE>
105 *
106 * where the following substitutions are made:
107 * <DL>
108 * <DT> <EM>opcode</EM>
109 * <DI> is the opcode of the instruction (e.g. ADC, MOV, etc)
110 *
111 * <DT> <EM>operand code</EM>
112 * <DI> represents the type of the nth operand:
113 * <DL>
114 * <DT> "Imm" <DI> immediate operands
115 * <DT> "Reg" <DI> register operands
116 * <DT> "RegInd" <DI> register indirect operands
117 * <DT> "RegDisp" <DI> register displacement
118 * <DT> "RegOff" <DI> shifted index + displacement
119 * <DT> "RegIdx" <DI> register base + shifted index + displacement
120 * <DT> "Cond" <DI> condition codes
121 * </DL>
122 *
123 * <DT> <EM>size</EM>
124 * <DI> indicates non-word-sized operations
125 * <DL>
126 * <DT> "Byte" <DI> bytes
127 * <DT> "Word" <DI> Intel "words" (i.e. 16 bites)
128 * <DT> "Quad" <DI> quad words (i.e. double-precision floating point)
129 * </DL>
130 *
131 * <DT> <EM>operand arguments</EM>
132 * <DI> are the needed components of the operands, in order
133 * <DL>
134 * <DT> "Imm"
135 * <DI>
136 * <UL>
137 * <LI> immediate value (int)
138 * </UL>
139 * <DT> "Reg"
140 * <DI>
141 * <UL>
142 * <LI> register number (byte)
143 * </UL>
144 * <DT> "RegInd"
145 * <DI>
146 * <UL>
147 * <LI> register number (byte)
148 * </UL>
149 * <DT> "RegDisp"
150 * <DI>
151 * <UL>
152 * <LI> register number (byte)
153 * <LI> displacement (int)
154 * </UL>
155 * <DT> "RegOff"
156 * <DI>
157 * <UL>
158 * <LI> index register (byte)
159 * <LI> scale (short)
160 * <LI> displacement (int)
161 * </UL>
162 * <DT> "RegIdx"
163 * <DI>
164 * <UL>
165 * <LI> base register (byte)
166 * <LI> index register (byte)
167 * <LI> scale (short)
168 * <LI> displacement (int)
169 * </UL>
170 * <DT> "Cond"
171 * <DI>
172 * <UL>
173 * <LI> condition code mask (byte)
174 * </UL>
175 * </DL>
176 * </DL>
177 *
178 * @see org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt
179 * @see Lister
180 * @see ForwardReference
181 *
182 */
183 public abstract class Assembler extends AbstractAssembler implements RegisterConstants, AssemblerConstants {
184
185 /**
186 * The lister object is used to print generated machine code.
187 */
188 protected final Lister lister;
189
190 /**
191 * The array holding the generated binary code.
192 */
193 private byte [] machineCodes;
194
195 /**
196 * The current end of the generated machine code
197 */
198 protected int mi;
199
200 /**
201 * Create an assembler with a given machine code buffer size that
202 * will not print the machine code as it generates it.
203 * The buffer size is merely a heuristic, because the assembler will
204 * expand its buffer if it becomes full.
205 *
206 * @param bytecodeSize initial machine code buffer size.
207 */
208 protected Assembler (int bytecodeSize) {
209 this(bytecodeSize, false);
210 }
211
212 /**
213 * Create an assembler with a given machine code buffer size and
214 * tell it whether or not to print machine code as it generates it.
215 * The buffer size is merely a heuristic, because the assembler will
216 * expand its buffer if it becomes full.
217 *
218 * @param bytecodeSize initial machine code buffer size.
219 * @param shouldPrint whether to dump generated machine code.
220 */
221 protected Assembler (int bytecodeSize, boolean shouldPrint) {
222 machineCodes = new byte[bytecodeSize*CODE_EXPANSION_FACTOR + CODE_OVERHEAD_TERM];
223 lister = shouldPrint ? new Lister((ArchitectureSpecific.Assembler) this) : null;
224 }
225
226 /**
227 * Create an assembler with a given machine code buffer size and
228 * tell it whether or not to print machine code as it generates it.
229 * The buffer size is merely a heuristic, because the assembler will
230 * expand its buffer if it becomes full.
231 *
232 * @param bytecodeSize initial machine code buffer size.
233 * @param shouldPrint whether to dump generated machine code.
234 * @param comp BaselineCompilerImpl instance that this assembler is associated with;
235 * currently ignored on IA32.
236 */
237 protected Assembler (int bytecodeSize, boolean shouldPrint, BaselineCompilerImpl comp) {
238 this(bytecodeSize, shouldPrint);
239 }
240
241 /**
242 * Heuristic constant used to calculate initial size of the machine
243 * code buffer. This is an average of how many bytes of generated
244 * code come from a given bytecode in the baseline compiler.
245 */
246 private static final int CODE_EXPANSION_FACTOR = 12;
247
248 /**
249 * Heuristic constant used to calculate initial size of the machine
250 * code buffer. This is an estimate of the fixed method overhead
251 * code generated by the baseline compiler, such as method
252 * prologue.
253 */
254 private static final int CODE_OVERHEAD_TERM = 100;
255
256 /**
257 * Return the current offset in the generated code buffer of the
258 * end of the genertaed machine code.
259 *
260 * @return the end of the generated machine code.
261 */
262 public final int getMachineCodeIndex () {
263 return mi;
264 }
265
266 /**
267 * Set the given byte offset in the machine code array to the
268 * given byte value. This is the low-level function by which the
269 * assembler produces binary code into its machine code buffer.
270 * This function will resize the underlying machine code array if
271 * the index given exceeds the array's length.
272 *
273 * @param index the byte offset into which to write
274 * @param data the byte data value to write
275 */
276 @NoNullCheck
277 @NoBoundsCheck
278 protected final void setMachineCodes(int index, byte data) {
279 if(index < machineCodes.length) {
280 machineCodes[index] = data;
281 } else {
282 growMachineCodes(index, data);
283 }
284 }
285
286 @NoInline
287 private void growMachineCodes(int index, byte data) {
288 byte [] old = machineCodes;
289 machineCodes = new byte [2 * old.length ];
290 System.arraycopy(old, 0, machineCodes, 0, old.length);
291 machineCodes[index] = data;
292 }
293
294
295 /**
296 * Create a MachineCode object
297 */
298 public final ArchitectureSpecific.MachineCode finalizeMachineCode(int[] bytecodeMap) {
299 return new ArchitectureSpecific.MachineCode(getMachineCodes(), bytecodeMap);
300 }
301
302 /**
303 * Should code created by this assembler instance be allocated in the
304 * hot code code space? By default the answer is false (ie, no).
305 */
306 protected boolean isHotCode() { return false; }
307
308 /**
309 * Return a copy of the generated code as a CodeArray.
310 * @return a copy of the generated code as a CodeArray.
311 */
312 public final ArchitectureSpecific.CodeArray getMachineCodes () {
313 int len = getMachineCodeIndex();
314 ArchitectureSpecific.CodeArray trimmed = ArchitectureSpecific.CodeArray.Factory.create(len, isHotCode());
315 for (int i=0; i<len; i++) {
316 trimmed.set(i, machineCodes[i]);
317 }
318 return trimmed;
319 }
320
321 /**
322 * Give the lister a message associated with a particular
323 * bytecode. This is used by the baseline assembler to print the
324 * bytecode associated with portions of machine code. (The
325 * optimizing compiler does not do this because its association
326 * between bytecodes and generated code is much less direct).
327 *
328 * @param bytecodeNumber the offset of the current bytecode in the
329 * current method's bytecode array.
330 * @param bc a message descriptive of the current bytecode.
331 */
332 public final void noteBytecode (int bytecodeNumber, String bc) {
333 if (lister != null) lister.noteBytecode(bytecodeNumber, bc);
334 }
335
336 @NoInline
337 public final void noteBytecode (int i, String bcode, int x) {
338 noteBytecode(i, bcode+" "+x);
339 }
340
341 @NoInline
342 public final void noteBytecode (int i, String bcode, long x) {
343 noteBytecode(i, bcode+" "+x);
344 }
345
346 @NoInline
347 public final void noteBytecode (int i, String bcode, Object o) {
348 noteBytecode(i, bcode+" "+o);
349 }
350
351 @NoInline
352 public final void noteBytecode (int i, String bcode, int x, int y) {
353 noteBytecode(i, bcode+" "+x+" "+y);
354 }
355
356 @NoInline
357 public final void noteBranchBytecode (int i, String bcode, int off,
358 int bt) {
359 noteBytecode(i, bcode +" "+off+" ["+bt+"] ");
360 }
361
362 @NoInline
363 public final void noteTableswitchBytecode (int i, int l, int h, int d) {
364 noteBytecode(i, "tableswitch [" + l + "--" + h + "] " + d);
365 }
366
367 @NoInline
368 public final void noteLookupswitchBytecode (int i, int n, int d) {
369 noteBytecode(i, "lookupswitch [<" + n + ">]" + d);
370 }
371
372 /**
373 * Inform the lister of a comment related to the currently
374 * generated machine code.
375 *
376 * @param comment a comment string
377 */
378 public final void comment (String comment) {
379 if (lister != null) lister.comment(mi, comment);
380 }
381
382 /**
383 * Print the raw bits of the current instruction. It takes the
384 * start of the instruction as a parameter, and prints from that
385 * start to the current machine code index.
386 *
387 * @see #getMachineCodeIndex
388 *
389 * @param start the starting index of the last instruction.
390 */
391 public final void writeLastInstruction(int start) {
392 for (int j=start; j<mi; j++) {
393 if (j < machineCodes.length) {
394 VM.sysWrite(Lister.hex(machineCodes[j]));
395 } else {
396 VM.sysWrite(Lister.hex((byte)0x0));
397 }
398 }
399 }
400
401 /**
402 * Find out whether a given signed value can be represented in a
403 * given number of bits.
404 *
405 * @param val the value to be represented
406 * @param bits the number of bits to use.
407 * @return true if val can be encoded in bits.
408 */
409 @Inline
410 protected static boolean fits (Offset val, int bits) {
411 return fits(val.toWord(), bits);
412 }
413
414 /**
415 * Find out whether a given signed value can be represented in a
416 * given number of bits.
417 *
418 * @param val the value to be represented
419 * @param bits the number of bits to use.
420 * @return true if val can be encoded in bits.
421 */
422 @Inline
423 protected static boolean fits (Address val, int bits) {
424 return fits(val.toWord(), bits);
425 }
426
427 /**
428 * Find out whether a given signed value can be represented in a
429 * given number of bits.
430 *
431 * @param val the value to be represented
432 * @param bits the number of bits to use.
433 * @return true if val can be encoded in bits.
434 */
435 @Inline
436 protected static boolean fits (Word val, int bits) {
437 Word o = val.rsha(bits-1);
438 return (o.isZero() || o.isMax());
439 }
440
441 /**
442 * Find out whether a given signed value can be represented in a
443 * given number of bits.
444 *
445 * @param val the value to be represented
446 * @param bits the number of bits to use.
447 * @return true if val can be encoded in bits.
448 */
449 @Inline
450 protected static boolean fits (int val, int bits) {
451 val = val >> bits-1;
452 return (val == 0 || val == -1);
453 }
454
455 /**
456 * In the representation of addressing modes in the ModRM and SIB
457 * bytes, the code for register-displacement for on ESP has a
458 * special meaning. Thus, when register-displacement mode using ESP
459 * is desired, this special SIB (scale-index-base) byte must be
460 * emitted.
461 */
462 private static final byte SIBforESP = (byte) ((0<<6) + (4<<3) + ESP.value()); // (scale factor 1) no index, ESP is base
463
464 /**
465 * Generate a REX prefix if necessary
466 *
467 * @param W is a quad word override needed
468 * @param R_reg extension of the modrm field
469 * @param X_reg extension of the SIB index field
470 * @param B_reg extension of the modrm field, SIB base or opcode reg field
471 */
472 @Inline
473 private void generateREXprefix(boolean W, MachineRegister R_reg, MachineRegister X_reg, MachineRegister B_reg) {
474 boolean R = R_reg != null && R_reg.needsREXprefix();
475 boolean X = X_reg != null && X_reg.needsREXprefix();
476 boolean B = B_reg != null && B_reg.needsREXprefix();
477 if (W || R || X || B) {
478 if (VM.VerifyAssertions) VM._assert(!VM.buildFor32Addr());
479 byte prefixByte = (byte)(0x40 | (W ? 8 : 0) | (R ? 4 : 0) | (X ? 2 : 0) | (B ? 1 : 0));
480 setMachineCodes(mi++, prefixByte);
481 }
482 }
483
484 /**
485 * Return a ModRM byte encoding a source and destination register
486 * (i.e. for a register-register instruction).
487 *
488 * @param reg1 the r/m register.
489 * @param reg2 the other register or extended opcode.
490 * @return the encoded ModRM byte.
491 */
492 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
493 private byte regRegModRM(MachineRegister reg1, MachineRegister reg2) {
494 return (byte) ((3 << 6) | ((reg2.value() & 7) << 3) | (reg1.value() & 0x7));
495 }
496
497 /**
498 * Return a ModRM byte encoding a source register-32-bit-displacement
499 * operand and a destination register. Note that the displacement
500 * is handled separately, and not encoded in the ModRM itself.
501 *
502 * @param reg1 the r/m register.
503 * @param reg2 the other register or extended opcode.
504 * @return the encoded ModRM byte.
505 */
506 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
507 private byte regDisp32RegModRM(MachineRegister reg1, MachineRegister reg2) {
508 return (byte) ((2 << 6) | ((reg2.value() & 7)<< 3) | (reg1.value() & 7));
509 }
510
511 /**
512 * Return a ModRM byte encoding a source register-8-bit-displacement
513 * operand and a destination register. Note that the displacement
514 * is handled separately, and not encoded in the ModRM itself.
515 *
516 * @param reg1 the r/m register.
517 * @param reg2 the other register or extended opcode.
518 * @return the encoded ModRM byte.
519 */
520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
521 private byte regDisp8RegModRM(MachineRegister reg1, MachineRegister reg2) {
522 return (byte) ((1 << 6) | ((reg2.value() & 7) << 3) | (reg1.value() & 7));
523 }
524
525 /**
526 * Return a ModRM byte encoding a source register-indirect
527 * operand and a destination register.
528 *
529 * @param reg1 the r/m register.
530 * @param reg2 the other register or extended opcode.
531 * @return the encoded ModRM byte.
532 */
533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
534 private byte regIndirectRegModRM(MachineRegister reg1, MachineRegister reg2) {
535 return (byte) (((reg2.value() & 7) << 3) | (reg1.value() & 7));
536 }
537
538 /**
539 * The more complex IA32 addressing modes require a
540 * scale-index-base (SIB) byte. This is used to encode addressing
541 * modes such as [ indexReg \<\< scale + baseReg ]. This method
542 * encodes the SIB byte for a given base, index and scale.
543 *
544 * @param scale the shift amount for the index register value.
545 * @param baseReg the base register.
546 * @param indexReg the index register.
547 * @return the encoded SIB byte.
548 */
549 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
550 private byte sib(short scale, MachineRegister baseReg, MachineRegister indexReg) {
551 return (byte) ((scale << 6) | ((indexReg.value() & 7) << 3) | (baseReg.value() & 7));
552 }
553
554 /**
555 * Generate the appropriate bytes into the generated machine code
556 * to represent a register-register instruction.
557 *
558 * @param reg1 the r/m operand.
559 * @param reg2 the other register or extended opcode.
560 */
561 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
562 private void emitRegRegOperands(MachineRegister reg1, MachineRegister reg2) {
563 setMachineCodes(mi++, regRegModRM(reg1, reg2));
564 }
565
566 /**
567 * Generate the appropriate bytes into the generated machine code
568 * to represent a register-32-bit-displacement--register
569 * instruction. This method generates the appropriate ModRM, the SIB
570 * if needed for the ESP special case, and the little-endian encoded
571 * 32 bit displacement.
572 *
573 * @see #SIBforESP
574 *
575 * @param reg1 the r/m operand.
576 * @param disp the 32 bit displacement.
577 * @param reg2 the other register or extended opcode.
578 */
579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
580 private void emitRegDisp32RegOperands(MachineRegister reg1, int disp, MachineRegister reg2) {
581 setMachineCodes(mi++, regDisp32RegModRM(reg1, reg2));
582 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
583 emitImm32(disp);
584 }
585
586 /**
587 * Generate the appropriate bytes into the generated machine code
588 * to represent a register-8-bit-displacement--register
589 * instruction. This method generates the appropriate ModRM, the SIB
590 * if needed for the ESP special case, and the little-endian encoded
591 * 32 bit displacement.
592 *
593 * @see #SIBforESP
594 *
595 * @param reg1 the r/m operand.
596 * @param disp the 8 bit displacement.
597 * @param reg2 the other register or extended opcode.
598 */
599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
600 private void emitRegDisp8RegOperands(MachineRegister reg1, byte disp, MachineRegister reg2) {
601 setMachineCodes(mi++, regDisp8RegModRM(reg1, reg2));
602 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
603 emitImm8(disp);
604 }
605
606 /**
607 * Generate the appropriate bytes into the generated machine code
608 * to represent a register-displacement--register instruction. This
609 * method simply chooses the appropriate lower-level method based on
610 * displacement size
611 *
612 * @see #emitRegDisp32RegOperands
613 * @see #emitRegDisp8RegOperands
614 *
615 * @param reg1 the r/m operand.
616 * @param disp the displacement.
617 * @param reg2 the other register or extended opcode.
618 */
619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
620 private void emitRegDispRegOperands(MachineRegister reg1, Offset disp, MachineRegister reg2) {
621 if (reg1 == GPR.EIP) {
622 setMachineCodes(mi++, regIndirectRegModRM(EBP, reg2)); // EBP == RIP addressing mode
623 emitImm32(disp);
624 } else if (fits(disp,8)) {
625 emitRegDisp8RegOperands(reg1, (byte)disp.toInt(), reg2);
626 } else {
627 if (VM.VerifyAssertions) VM._assert(fits(disp,32));
628 emitRegDisp32RegOperands(reg1, disp.toInt(), reg2);
629 }
630 }
631
632 /**
633 * Generate the appropriate bytes into the generated machine code
634 * to express a register-indirect--register instruction. This
635 * method handles low-level encoding issues, specifically the
636 * special cases for register indirect mode on ESP and EBP. Using
637 * ESP requires an SIB byte, and EBP cannot be used in indirect mode
638 * at all (that encoding is used to express scaled-index-displacement
639 * mode) so this method uses register-displacement with a 0
640 * displacement to fake it.
641 *
642 * @see #emitRegDispRegOperands
643 *
644 * @param reg1 the r/m operand
645 * @param reg2 the other register or extended opcode
646 */
647 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
648 private void emitRegIndirectRegOperands(MachineRegister reg1, MachineRegister reg2) {
649 if (reg1 == EBP) {
650 emitRegDispRegOperands(reg1, Offset.zero(), reg2);
651 } else {
652 setMachineCodes(mi++, regIndirectRegModRM(reg1, reg2));
653 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
654 }
655 }
656
657 /**
658 * Generate the appropriate bytes into the generated code to denote
659 * a scaled-register+displacement--register instruction. This
660 * expresses the case where the SIB byte is used, but no base
661 * register is desired. This method handles the somewhat convoluted
662 * special case used to express this mode (the r/m register is 4/ESP and
663 * the base register must be 5/EBP).
664 *
665 * @param index the index register for the r/m operand
666 * @param scale the amount to shift the index register
667 * @param disp the displacement for the r/m operand
668 * @param reg2 the other operand or the extended opcode
669 */
670 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
671 private void emitRegOffRegOperands(MachineRegister index, short scale, Offset disp, MachineRegister reg2) {
672 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2));
673 setMachineCodes(mi++, sib(scale, EBP, index));
674 emitImm32(disp);
675 }
676
677 /**
678 * Generate the appropriate bytes into the generated code to denote
679 * an absolute-address--register instruction.
680 *
681 * @param disp the displacement for the r/m operand
682 * @param reg2 the other operand or the extended opcode
683 */
684 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
685 private void emitAbsRegOperands(Address disp, MachineRegister reg2) {
686 if (VM.buildFor32Addr()) {
687 setMachineCodes(mi++, regIndirectRegModRM(EBP, reg2)); // EBP == No displacement
688 } else {
689 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2)); // ESP == SIB byte
690 setMachineCodes(mi++, sib((short)0, EBP, ESP)); // EBP+ESP<<0 == no SIB
691 }
692 emitImm32(disp);
693 }
694
695 /**
696 * Generate the full glory of scaled-index-base-displacement
697 * addressing to the generated machine code. This method handles
698 * various special cases, mostly choosing the smallest displacement
699 * possible.
700 *
701 * @param base the base register for the r/m operand
702 * @param index the index register for the r/m operand
703 * @param scale the amount to shift the index register
704 * @param disp the displacement for the r/m operand
705 * @param reg2 the other operand or the extended opcode
706 */
707 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
708 private void emitSIBRegOperands(MachineRegister base, MachineRegister index, short scale, Offset disp, MachineRegister reg2) {
709 if (VM.VerifyAssertions) VM._assert(index != ESP);
710 if (disp.EQ(Offset.zero()) && base != EBP) {
711 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2));
712 setMachineCodes(mi++, sib(scale, base, index));
713 } else if (fits(disp,8)) {
714 setMachineCodes(mi++, regDisp8RegModRM(ESP, reg2));
715 setMachineCodes(mi++, sib(scale, base, index));
716 emitImm8((byte)disp.toInt());
717 } else {
718 setMachineCodes(mi++, regDisp32RegModRM(ESP, reg2));
719 setMachineCodes(mi++, sib(scale, base, index));
720 emitImm32(disp);
721 }
722 }
723
724 /**
725 * Generate the smallest-byte-first IA32 encoding of 32 bit
726 * immediates into the generated code.
727 *
728 * @param disp the displacement to generate.
729 */
730 @Inline
731 private void emitImm32(Offset disp) {
732 emitImm32(disp.toWord());
733 }
734
735 /**
736 * Generate the smallest-byte-first IA32 encoding of 32 bit
737 * immediates into the generated code.
738 *
739 * @param disp the displacement to generate.
740 */
741 @Inline
742 private void emitImm32(Address disp) {
743 emitImm32(disp.toWord());
744 }
745
746 /**
747 * Generate the smallest-byte-first IA32 encoding of 32 bit
748 * immediates into the generated code.
749 *
750 * @param disp the displacement to generate.
751 */
752 @Inline
753 private void emitImm32(Word disp) {
754 if (VM.VerifyAssertions) VM._assert(fits(disp,32));
755 mi = emitImm32(disp.toInt(), mi);
756 }
757
758 /**
759 * Generate the smallest-byte-first IA32 encoding of 32 bit
760 * immediates into the generated code.
761 *
762 * @param imm the immediate to generate.
763 */
764 @Inline
765 private void emitImm32(int imm) {
766 mi = emitImm32(imm, mi);
767 }
768
769 /**
770 * Generate the smallest-byte first x86_64 encoding of the 64 bit
771 * immeditate into the generated code.
772 *
773 * @param imm the immediate the generate;
774 */
775 @Inline
776 private void emitImm64(long imm) {
777 mi = emitImm64(imm, mi);
778 }
779
780 /**
781 * Generate the IA32 encoding of an 16 bit immediate into the
782 * generated code.
783 *
784 * @param imm the immediate to generate.
785 */
786 @Inline
787 private void emitImm16(int imm) {
788 mi = emitImm16(imm, mi);
789 }
790
791 /**
792 * Generate the IA32 encoding of an 8 bit immediate into the
793 * generated code.
794 *
795 * @param imm the immediate to generate.
796 */
797 @Inline
798 private void emitImm8(int imm) {
799 mi = emitImm8(imm, mi);
800 }
801
802 /**
803 * Generate the smallest-byte-first IA32 encoding of 16 bit
804 * immediates into the generated code at the location specified.
805 *
806 * @param imm the immediate to generate.
807 * @param idx the location in the generated code to write.
808 */
809 @Inline
810 private int emitImm16(int imm, int idx) {
811 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
812 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
813 return idx;
814 }
815
816 /**
817 * Generate the smallest-byte-first IA32 encoding of 32 bit
818 * immediate into the generated code at the location specified.
819 *
820 * @param imm the immediate to generate.
821 * @param idx the location in the generated code to write.
822 */
823 @Inline
824 private int emitImm32(int imm, int idx) {
825 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
826 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
827 setMachineCodes(idx++, (byte) ((imm >> 16) & 0xFF));
828 setMachineCodes(idx++, (byte) ((imm >> 24) & 0xFF));
829 return idx;
830 }
831
832 /**
833 * Generate the smallest-byte first x86_64 encoding of the 64 bit
834 * immeditate into the generated code at the location specified.
835 *
836 * @param imm the immediate the generate;
837 * @param idx the location in the generated code to write.
838 */
839 private int emitImm64(long imm, int idx) {
840 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
841 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
842 setMachineCodes(idx++, (byte) ((imm >> 16) & 0xFF));
843 setMachineCodes(idx++, (byte) ((imm >> 24) & 0xFF));
844 setMachineCodes(idx++, (byte) ((imm >> 32) & 0xFF));
845 setMachineCodes(idx++, (byte) ((imm >> 40) & 0xFF));
846 setMachineCodes(idx++, (byte) ((imm >> 48) & 0xFF));
847 setMachineCodes(idx++, (byte) ((imm >> 56) & 0xFF));
848 return idx;
849 }
850
851 /**
852 * Generate the IA32 encoding of an 8 bit immediate into the
853 * generated code at the location specified.
854 *
855 * @param imm the immediate to generate.
856 * @param idx the location in the generated code to write.
857 */
858 @Inline
859 private int emitImm8(int imm, int idx) {
860 setMachineCodes(idx++, (byte) imm);
861 return idx;
862 }
863
864 /**
865 * Generate a conditional opcode given the base opcode and the
866 * condition code desired. The CMOVcc, SETcc and Jcc families of
867 * instructions all have opcodes defined as a base opcode plus some
868 * bits representing the condition code. (of course, FCMOV does not
869 * this, since that would be too logical).
870 *
871 * @param opCode the base opcode to emit
872 * @param cond the condition code desired
873 */
874 @Inline
875 private void emitCondOpByte(byte opCode, byte cond) {
876 setMachineCodes(mi++, (byte) (opCode | cond));
877 }
878
879 /**
880 * Generate a locking prefix word into the generated code. Locking
881 * operations on IA32 are expressed by writing a locking byte before
882 * the instruction.
883 */
884 @Inline
885 public final void emitLockNextInstruction() {
886 setMachineCodes(mi++, (byte) 0xF0);
887 if (lister != null) lister.lockPrefix();
888 }
889
890 /**
891 * Generate a branch likely prefix into the generated code.
892 */
893 @Inline
894 public final void emitBranchLikelyNextInstruction() {
895 setMachineCodes(mi++, (byte) 0x3E);
896 if (lister != null) lister.branchLikelyPrefix();
897 }
898
899 /**
900 * Generate a branch unlikely prefix into the generated code.
901 */
902 @Inline
903 public final void emitBranchUnlikelyNextInstruction() {
904 setMachineCodes(mi++, (byte) 0x2E);
905 if (lister != null) lister.branchUnlikelyPrefix();
906 }
907
908 /**
909 * Generate a patch point into the generated code.
910 * (1) force patch point to be 32 bit aligned by optionally
911 * generating a nop.
912 * (2) emit a short branch (2 byte) around 3 bytes of nop.
913 * (3) If the the code is later patched, we first patch the 3
914 * nop bytes to be the upper 24 bits of a long jump
915 * instruction, then update the 2 bytes of the patch
916 * point to be an unconditional jump with a 32 bit immediate.
917 */
918 @Inline
919 public final void emitPatchPoint() {
920 emitNOP((4-mi-1) & 3);
921 ForwardReference r = forwardJMP();
922 emitNOP(3);
923 r.resolve(this);
924 }
925
926 /**
927 * Apply a patch.
928 * We expect the following instruction stream:
929 * i1; JMP rel8; NOP; NOP; NOP; i2;
930 * where patchOffset is the index of the last NOP.
931 * We patch it to be
932 * i1; JMP rel32; i2;
933 *
934 * @param code the code array to patch
935 * @param patchOffset the offset of the last byte of the patch point
936 * @param rel32 the new immediate to use in the branch instruction
937 * the code patcher is going to lay down before patchOffset
938 */
939 public static void patchCode(ArchitectureSpecific.CodeArray code, int patchOffset, int rel32) {
940 byte p0 = (byte)0xE9;
941 byte p1 = (byte) (rel32 & 0x000000ff);
942 byte p2 = (byte)((rel32 & 0x0000ff00) >>> 8);
943 byte p3 = (byte)((rel32 & 0x00ff0000) >>> 16);
944 byte p4 = (byte)((rel32 & 0xff000000) >>> 24);
945 if ((patchOffset & 0x2) == 0x2) {
946 // (a) lay down p4,p3,p2 one byte at a time
947 // (b) pick up the two bytes before p0 and then
948 // lay down b2b1p0p1 as a word.
949 code.set(patchOffset--, p4);
950 code.set(patchOffset--, p3);
951 code.set(patchOffset--, p2);
952 patchOffset -= 2; // skip over p1, p0
953 byte b1 = code.get(patchOffset--);
954 byte b2 = code.get(patchOffset);
955 int patch = (((int)p1&0xff) << 24) | (((int)p0&0xff) << 16) |
956 (((int)b1&0xff) << 8) | ((int)b2&0xff);
957 Magic.setIntAtOffset(code, Offset.fromIntSignExtend(patchOffset), patch);
958 } else {
959 // (a) lay down p4
960 // (b) lay down p0p1p2p3 as a word
961 code.set(patchOffset--, p4);
962 patchOffset -= 3; // skip over p0p1p2p3
963 int patch = (((int)p3&0xff) << 24) | (((int)p2&0xff) << 16) |
964 (((int)p1&0xff) << 8) | ((int)p0&0xff);
965 Magic.setIntAtOffset(code, Offset.fromIntSignExtend(patchOffset), patch);
966 }
967 }
968
969 /**
970 * Return the appropriate condition code if we want to
971 * reverse the sense of the branch
972 */
973 public final byte flipCode(byte cond) {
974 switch (cond) {
975 case EQ: return NE;
976 case NE: return EQ;
977 case LT: return GE;
978 case GT: return LE;
979 case LE: return GT;
980 case GE: return LT;
981 default: throw new InternalError("Unexpected condition code");
982 }
983 }
984
985 /**
986 * Generate a forward JMP instruction into the generated code.
987 * This form is used when the compiler wants to hang onto the
988 * forward reference object and call resolve on it directly. These
989 * forward references are not handled by the mechanism in the
990 * assembler; the client is responsible for calling resolve on the
991 * reference when generating the target instruction. The baseline
992 * compiler uses this form for jumps within the machine code for a
993 * single bytecode.
994 */
995 public final ForwardReference forwardJMP () {
996 int miStart = mi;
997 ForwardReference r = new ForwardReference.ShortBranch(mi);
998 setMachineCodes(mi++, (byte) 0xEB);
999 mi += 1; // leave space for displacement
1000 if (lister != null) lister.I(miStart, "JMP", 0);
1001 return r;
1002 }
1003
1004 /**
1005 * Generate a forward Jcc instruction into the generated code.
1006 * This form is used when the compiler wants to hang onto the
1007 * forward reference object and call resolve on it directly. These
1008 * forward references are not handled by the mechanism in the
1009 * assembler; the client is responsible for calling resolve on the
1010 * reference when generating the target instruction. The baseline
1011 * compiler uses this form for jumps within the machine code for a
1012 * single bytecode.
1013 *
1014 * @param cond the condition code on which to branch
1015 */
1016 public final ForwardReference forwardJcc (byte cond) {
1017 int miStart = mi;
1018 ForwardReference r = new ForwardReference.ShortBranch(mi);
1019 setMachineCodes(mi++, (byte) (0x70 + cond));
1020 mi += 1; // leave space for displacement
1021 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], 0);
1022 return r;
1023 }
1024
1025 /**
1026 * The set of outstanding forward references. This list is used by
1027 * the assembler to keep track of all outstanding forward
1028 * references. References are put on this list by the emit methods
1029 * for JMP and Jcc when they find a branch that is going forward.
1030 * Each reference must understand what instruction it is looking for
1031 * and how to patch its source instruction. Then, when the client
1032 * calls resolveForwardBranches, the assembler searches this list to
1033 * find branches that match the instruction currently being
1034 * generated, and calls the resolve method on each one that does.
1035 *
1036 * All forward branches have a label as the branch target; clients
1037 * can arbirarily associate labels and instructions, but must be
1038 * consistent in giving the chosen label as the target of branches
1039 * to an instruction and calling resolveForwardBranches with the
1040 * given label immediately before emitting the target instruction.
1041 * See the header comments of ForwardReference for more details.
1042 */
1043 protected ForwardReference forwardRefs;
1044
1045 /**
1046 * Resolve all forward branches that have the given target, and
1047 * make them branch to the instruction currently being generated.
1048 * Clients of the assembler call this method immediately before they
1049 * emit the instruction intended to be the target of the given
1050 * label.
1051 *
1052 * All forward branches have a label as the branch target; clients
1053 * can arbirarily associate labels and instructions, but must be
1054 * consistent in giving the chosen label as the target of branches
1055 * to an instruction and calling resolveForwardBranches with the
1056 * given label immediately before emitting the target instruction.
1057 * See the header comments of ForwardReference for more details.
1058 *
1059 * @param label the forward branch label to resolve
1060 */
1061 public final void resolveForwardReferences (int label) {
1062 if (forwardRefs == null) return; // premature optimization
1063 forwardRefs = ForwardReference.resolveMatching(this, forwardRefs, label);
1064 }
1065
1066 /**
1067 * Set up a code sequence to push a return address. This involves pushing the
1068 * current instruction address, and setting up an ADD that gets resolved later.
1069 *
1070 * @param bReturn the return address that is to be loaded.
1071 */
1072 public final void generateLoadReturnAddress(int bReturn) {
1073 /* Push the IP */
1074 emitCALL_Imm(mi + 5);
1075 ForwardReference r = new ForwardReference.LoadReturnAddress(mi, bReturn);
1076 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1077 /* Fake MAX_INTEGER to ensure 32 bit immediate */
1078 emitADD_RegInd_Imm(ESP, Integer.MAX_VALUE);
1079 }
1080
1081 /**
1082 * Patch the code sequence at sourceIndex to load the complete instruction address
1083 * of the current instruction.
1084 *
1085 * @param sourceIndex the machine code offset of the load return addres to patch.
1086 */
1087 public final void patchLoadReturnAddress(int sourceIndex) {
1088 /* We have the following pattern:
1089 * | PUSH EIP | [SP] += | IMM32 |
1090 * ^ ^
1091 * sourceIndex +3 */
1092 int ipDelta = mi - sourceIndex;
1093 emitImm32(ipDelta, sourceIndex + 3);
1094 }
1095
1096 /**
1097 * Generate a code sequence that will place the address of the start of the
1098 * method in destReg
1099 *
1100 * @param destReg register to hold address of start of method
1101 */
1102 public final void emitMETHODSTART_Reg(GPR destReg) {
1103 if (VM.buildFor32Addr()) {
1104 Offset pcThunkOffset;
1105 pcThunkOffset = OutOfLineMachineCode.pcThunkInstructionsField[destReg.value()].getOffset();
1106 emitCALL_Abs(Magic.getTocPointer().plus(pcThunkOffset));
1107 emitADD_Reg_Imm(destReg, -mi);
1108 } else {
1109 emitLEA_Reg_RegDisp_Quad(destReg, GPR.EIP, Offset.fromIntZeroExtend(Integer.MAX_VALUE));
1110 emitImm32(-mi, mi-4);
1111 }
1112 }
1113
1114 /**
1115 * Make a forward reference and emit a long JMP
1116 * @param btarget optional
1117 * @return a forward reference for patching later
1118 */
1119 public final ForwardReference generatePendingJMP(int btarget) {
1120 int miStart = mi;
1121 ForwardReference r = new ForwardReference.UnconditionalBranch(mi, btarget);
1122 setMachineCodes(mi++, (byte) 0xE9);
1123 mi += 4; // leave space for displacement
1124 if (lister != null) lister.I(miStart, "JMP", 0);
1125 return r;
1126 }
1127 // END OSR SUPPORT //
1128
1129 /**
1130 * Make the given unconditional branch branch to the current
1131 * generated instruction. It is the client's responsibility to
1132 * ensure the given source index really does contain an
1133 * unconditional branch.
1134 *
1135 * @param sourceIndex the machine code offset of the unconditional
1136 * branch to patch.
1137 */
1138 public final void patchUnconditionalBranch (int sourceIndex) {
1139 if (VM.AlignmentChecking || isHotCode()) {
1140 // force 4byte alignment here
1141 emitNOP((4 - mi) & 3);
1142 }
1143 if (lister != null) lister.comefrom(mi, sourceIndex);
1144 int relOffset = mi - (sourceIndex+5);
1145 sourceIndex++; // skip the op code
1146 emitImm32(relOffset, sourceIndex);
1147 }
1148
1149 /**
1150 * Make the given conditional branch branch to the current
1151 * generated instruction. It is the client's responsibility to
1152 * ensure the given source index really does contain an
1153 * conditional branch.
1154 *
1155 * @param sourceIndex the machine code offset of the conditional
1156 * branch to patch.
1157 */
1158 public final void patchConditionalBranch (int sourceIndex) {
1159 if (VM.AlignmentChecking || isHotCode()) {
1160 // force 4byte alignment here
1161 emitNOP((4 - mi) & 3);
1162 }
1163 if (lister != null) lister.comefrom(mi, sourceIndex);
1164 int relOffset = mi - (sourceIndex+6);
1165 sourceIndex += 2; // skip the (two byte) op code
1166 emitImm32(relOffset, sourceIndex);
1167 }
1168
1169 /**
1170 * Make the given unconditional branch branch to the current
1171 * generated instruction. It is the client's responsibility to
1172 * ensure the given source index really does contain an
1173 * unconditional branch. This instruction requires that the branch
1174 * have been generated with an 8 bit offset.
1175 *
1176 * @param sourceIndex the machine code offset of the unconditional
1177 * branch to patch.
1178 */
1179 public final void patchShortBranch (int sourceIndex) {
1180 if (VM.AlignmentChecking || isHotCode()) {
1181 // force 4byte alignment here
1182 emitNOP((4 - mi) & 3);
1183 }
1184 if (lister != null) lister.comefrom(mi, sourceIndex);
1185 int relOffset = mi - (sourceIndex+2);
1186 if (VM.VerifyAssertions) VM._assert(fits(relOffset, 8), "offset too large: "+relOffset);
1187 sourceIndex++; // skip the op code
1188 emitImm8((byte)relOffset, sourceIndex);
1189 }
1190
1191 /////////////////////////////////////
1192 // table switch support /////////////
1193 /////////////////////////////////////
1194
1195 /**
1196 * An OFFSET instruction is not really an instruction; it is rather
1197 * an address (of an instruction) that is written into the binary
1198 * code. These are used to build a table of addresses for table
1199 * switches. The code for tableswitches first calculates the address of the
1200 * start of the method. Using this address a branch relative to the start
1201 * of the method is computed by loading the offset from the start of the
1202 * method for a particular switch case. The OFFSET instruction is encoding
1203 * one value in the table.
1204 *
1205 * This mechanism assumes code for emitting tableswitch looks as
1206 * follows; it is not very nice, but is improved on X86 64 with the addition
1207 * of RIP displacement addressing. The GNU tools generate something.
1208 * Note that default cases must be handled separately. </P>
1209 *
1210 * <PRE>
1211 * T0 = getPCThunk() or RIP less offset from start of method
1212 * T0 += [T0 + m<<2 + tableDisplacement]
1213 * JMP T0
1214 * tableDisplacement:
1215 * OFFSET 0 (case 0 target)
1216 * OFFSET 1 (case 1 target)
1217 * ...
1218 * OFFSET n (case n target)
1219 * </PRE>
1220 *
1221 * @see #patchSwitchCase
1222 *
1223 * @param c the table entry being emitted (i.e. the value of the
1224 * switch expression corresponding to this target)
1225 * @param mTarget the method-relative target offset
1226 * @param bTarget the label associated with the branch target instrucion
1227 */
1228 public final void emitOFFSET_Imm_ImmOrLabel(int c, int mTarget, int bTarget) {
1229 int miStart = mi;
1230 if (0 < mTarget) { // resolved (backward) reference
1231 emitImm32(mTarget);
1232 if (lister != null) lister.I(miStart, "DATA", mTarget);
1233 } else { // unresolved forward reference
1234 ForwardReference r = new ForwardReference.SwitchCase(mi, bTarget);
1235 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1236 emitImm32(c);
1237 if (lister != null) lister.I(miStart, "DATA", c);
1238 }
1239 }
1240
1241 /**
1242 * Patch a tableswitch offset table entry at the given source
1243 * index. This method resolves the table entry at the given source
1244 * index to point to the current instruction plus an aligning NOP.
1245 *
1246 * @see #emitOFFSET_Imm_ImmOrLabel
1247 *
1248 * @param sourceIndex the location of the offset to patch
1249 */
1250 public final void patchSwitchCase (int sourceIndex) {
1251 if (VM.AlignmentChecking || isHotCode()) {
1252 // force 4byte alignment here
1253 emitNOP((4 - mi) & 3);
1254 }
1255 if (lister != null) lister.comefrom(mi, sourceIndex);
1256 int c = 0;
1257 c |= (machineCodes[sourceIndex+0] & 0xFF) << 0;
1258 c |= (machineCodes[sourceIndex+1] & 0xFF) << 8;
1259 c |= (machineCodes[sourceIndex+2] & 0xFF) << 16;
1260 c |= (machineCodes[sourceIndex+3] & 0xFF) << 24; // c = case index
1261 emitImm32(mi, sourceIndex); // write mi to sourceIndex
1262 }
1263
1264 /**
1265 * Patch the instruction that will load the displacement to the offset table
1266 * from the start of the method assuming that the next code to be created is
1267 * the offset table.
1268 *
1269 * @param toPatchAddress the address of the instruction that performs the
1270 * displacement load
1271 */
1272 public final void patchSwitchTableDisplacement(int toPatchAddress) {
1273 if (VM.buildFor32Addr()) {
1274 // the instruction to patch is an reg = [reg + idx<<scale + disp]
1275 emitImm32(mi, toPatchAddress+3);
1276 } else {
1277 // the instruction to patch is an reg = [reg + idx<<scale + disp]
1278 emitImm32(mi, toPatchAddress+3);
1279 }
1280 }
1281
1282 /////////////////////////////////////
1283 // instructions (hand coded) //
1284 /////////////////////////////////////
1285
1286 /**
1287 * Generate a bswap on a register. That is,
1288 * <PRE>
1289 * bswap reg
1290 * </PRE>
1291 *
1292 * @param reg register to operate upon
1293 */
1294 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1295 public final void emitBSWAP_Reg(GPR reg) {
1296 int miStart = mi;
1297 generateREXprefix(false, null, null, reg);
1298 setMachineCodes(mi++, (byte) 0x0F);
1299 setMachineCodes(mi++, (byte) (0xC8 | (reg.value() & 7)));
1300 if (lister != null) lister.R(miStart, "bswap", reg);
1301 }
1302
1303 /**
1304 * Generate a bswap on a quad register. That is,
1305 * <PRE>
1306 * bswap reg
1307 * </PRE>
1308 *
1309 * @param reg register to operate upon
1310 */
1311 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1312 public final void emitBSWAP_Reg_Quad(GPR reg) {
1313 int miStart = mi;
1314 generateREXprefix(true, null, null, reg);
1315 setMachineCodes(mi++, (byte) 0x0F);
1316 setMachineCodes(mi++, (byte) (0xC8 | (reg.value() & 7)));
1317 if (lister != null) lister.R(miStart, "bswap", reg);
1318 }
1319
1320 /**
1321 * Conditionally move the source to the destination, i.e.
1322 * <PRE>
1323 * if (cond) dst = src
1324 * </PRE>
1325 */
1326 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1327 public final void emitCMOV_Cond_Reg_Reg(byte cond, GPR dst, GPR src) {
1328 int miStart = mi;
1329 generateREXprefix(false, dst, null, src);
1330 setMachineCodes(mi++, (byte) 0x0F);
1331 emitCondOpByte((byte)0x40, cond);
1332 emitRegRegOperands(src, dst);
1333 if (lister != null) lister.RR(miStart, "CMOV" + CONDITION[cond], dst, src);
1334 }
1335
1336 /**
1337 * Conditionally move the source to the destination, i.e.
1338 * <PRE>
1339 * if (cond) dst = [src + disp]
1340 * </PRE>
1341 */
1342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1343 public final void emitCMOV_Cond_Reg_RegDisp(byte cond, GPR dst, GPR src, Offset disp) {
1344 int miStart = mi;
1345 generateREXprefix(false, dst, null, src);
1346 setMachineCodes(mi++, (byte) 0x0F);
1347 emitCondOpByte((byte)0x40, cond);
1348 emitRegDispRegOperands(src, disp, dst);
1349 if (lister != null) lister.RRD(miStart, "CMOV" + CONDITION[cond], dst, src, disp);
1350 }
1351
1352 /**
1353 * Conditionally move the source to the destination, i.e.
1354 * <PRE>
1355 * if (cond) dst = [src]
1356 * </PRE>
1357 */
1358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1359 public final void emitCMOV_Cond_Reg_RegInd(byte cond, GPR dst, GPR src) {
1360 int miStart = mi;
1361 generateREXprefix(false, dst, null, src);
1362 setMachineCodes(mi++, (byte) 0x0F);
1363 emitCondOpByte((byte)0x40, cond);
1364 emitRegIndirectRegOperands(src, dst);
1365 if (lister != null) lister.RRN(miStart, "CMOV" + CONDITION[cond], dst, src);
1366 }
1367
1368 /**
1369 * Conditionally move the source to the destination, i.e.
1370 * <PRE>
1371 * if (cond) dst = [index2<<scale2 + disp2]
1372 * </PRE>
1373 */
1374 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1375 public final void emitCMOV_Cond_Reg_RegOff(byte cond, GPR dst, GPR index2, short scale2, Offset disp2) {
1376 int miStart = mi;
1377 generateREXprefix(false, dst, index2, null);
1378 setMachineCodes(mi++, (byte) 0x0F);
1379 emitCondOpByte((byte)0x40, cond);
1380 emitRegOffRegOperands(index2, scale2, disp2, dst);
1381 if (lister != null) lister.RRFD(miStart, "CMOV" + CONDITION[cond], dst, index2, scale2, disp2);
1382 }
1383
1384 /**
1385 * Conditionally move the source to the destination, i.e.
1386 * <PRE>
1387 * if (cond) dst = [disp2]
1388 * </PRE>
1389 */
1390 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1391 public final void emitCMOV_Cond_Reg_Abs(byte cond, GPR dst, Address disp2) {
1392 int miStart = mi;
1393 generateREXprefix(false, dst, null, null);
1394 setMachineCodes(mi++, (byte) 0x0F);
1395 emitCondOpByte((byte)0x40, cond);
1396 emitAbsRegOperands(disp2, dst);
1397 if (lister != null) lister.RRA(miStart, "CMOV" + CONDITION[cond], dst, disp2);
1398 }
1399
1400 /**
1401 * Conditionally move the source to the destination, i.e.
1402 * <PRE>
1403 * if (cond) dst = [base2 + index2<<scale2 + disp2]
1404 * </PRE>
1405 */
1406 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3,4})
1407 public final void emitCMOV_Cond_Reg_RegIdx(byte cond, GPR dst, GPR base2, GPR index2, short scale2, Offset disp2) {
1408 int miStart = mi;
1409 generateREXprefix(false, dst, index2, base2);
1410 setMachineCodes(mi++, (byte) 0x0F);
1411 emitCondOpByte((byte)0x40, cond);
1412 emitSIBRegOperands(base2, index2, scale2, disp2, dst);
1413 if (lister != null) lister.RRXD(miStart, "CMOV" + CONDITION[cond], dst, base2, index2, scale2, disp2);
1414 }
1415
1416 /**
1417 * Set destination to zero or one, if the given condition is false
1418 * or true, respectively. That is,
1419 * <PRE>
1420 * dst = (cond)? 1: 0
1421 * </PRE>
1422 *
1423 * @param cond the condition to be tested
1424 * @param dst the destination register
1425 */
1426 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1427 public final void emitSET_Cond_Reg_Byte(byte cond, GPR dst) {
1428 int miStart = mi;
1429 generateREXprefix(false, null, null, dst);
1430 setMachineCodes(mi++, (byte) 0x0F);
1431 emitCondOpByte((byte)0x90, cond);
1432 emitRegRegOperands(dst, EAX /* UNUSED */);
1433 if (lister != null) lister.R(miStart, "SET" + CONDITION[cond], dst);
1434 }
1435
1436 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1437 public final void emitSET_Cond_RegDisp_Byte(byte cond, GPR dst, Offset disp) {
1438 int miStart = mi;
1439 generateREXprefix(false, null, null, dst);
1440 setMachineCodes(mi++, (byte) 0x0F);
1441 emitCondOpByte((byte)0x90, cond);
1442 emitRegDispRegOperands(dst, disp, EAX /* UNUSED */);
1443 if (lister != null) lister.RD(miStart, "SET" + CONDITION[cond], dst, disp);
1444 }
1445
1446 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1447 public final void emitSET_Cond_RegInd_Byte(byte cond, GPR dst) {
1448 int miStart = mi;
1449 generateREXprefix(false, null, null, dst);
1450 setMachineCodes(mi++, (byte) 0x0F);
1451 emitCondOpByte((byte)0x90, cond);
1452 emitRegIndirectRegOperands(dst, EAX /* UNUSED */);
1453 if (lister != null) lister.RN(miStart, "SET" + CONDITION[cond], dst);
1454 }
1455
1456 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1457 public final void emitSET_Cond_RegIdx_Byte(byte cond, GPR base, GPR index, short scale, Offset disp) {
1458 int miStart = mi;
1459 generateREXprefix(false, null, index, base);
1460 setMachineCodes(mi++, (byte) 0x0F);
1461 emitCondOpByte((byte)0x90, cond);
1462 emitSIBRegOperands(base, index, scale, disp, EAX /* UNUSED */);
1463 if (lister != null) lister.RXD(miStart, "SET" + CONDITION[cond], base, index, scale, disp);
1464 }
1465
1466 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1467 public final void emitSET_Cond_RegOff_Byte(byte cond, GPR index, short scale, Offset disp) {
1468 int miStart = mi;
1469 generateREXprefix(false, null, index, null);
1470 setMachineCodes(mi++, (byte) 0x0F);
1471 emitCondOpByte((byte)0x90, cond);
1472 emitRegOffRegOperands(index, scale, disp, EAX /* UNUSED */);
1473 if (lister != null) lister.RFD(miStart, "SET" + CONDITION[cond], index, scale, disp);
1474 }
1475
1476 @Inline
1477 public final void emitSET_Cond_Abs_Byte(byte cond, Address disp) {
1478 int miStart = mi;
1479 generateREXprefix(false, null, null, null);
1480 setMachineCodes(mi++, (byte) 0x0F);
1481 emitCondOpByte((byte)0x90, cond);
1482 emitAbsRegOperands(disp, EAX /* UNUSED */);
1483 if (lister != null) lister.RA(miStart, "SET" + CONDITION[cond], disp);
1484 }
1485
1486 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1487 public final void emitIMUL2_Reg_Reg(GPR dstReg, GPR srcReg) {
1488 int miStart = mi;
1489 generateREXprefix(false, dstReg, null, srcReg);
1490 setMachineCodes(mi++, (byte) 0x0F);
1491 setMachineCodes(mi++, (byte) 0xAF);
1492 emitRegRegOperands(srcReg, dstReg);
1493 if (lister != null) lister.RR(miStart, "IMUL", dstReg, srcReg);
1494 }
1495
1496 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1497 public final void emitIMUL2_Reg_RegInd(GPR dstReg, GPR srcBase) {
1498 int miStart = mi;
1499 generateREXprefix(false, dstReg, null, srcBase);
1500 setMachineCodes(mi++, (byte) 0x0F);
1501 setMachineCodes(mi++, (byte) 0xAF);
1502 emitRegIndirectRegOperands(srcBase, dstReg);
1503 if (lister != null) lister.RRN(miStart, "IMUL", dstReg, srcBase);
1504 }
1505
1506 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1507 public final void emitIMUL2_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
1508 int miStart = mi;
1509 generateREXprefix(false, dstReg, null, srcBase);
1510 setMachineCodes(mi++, (byte) 0x0F);
1511 setMachineCodes(mi++, (byte) 0xAF);
1512 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1513 if (lister != null) lister.RRD(miStart, "IMUL", dstReg, srcBase, srcDisp);
1514 }
1515
1516 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1517 public final void emitIMUL2_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1518 int miStart = mi;
1519 generateREXprefix(false, dstReg, srcIndex, null);
1520 setMachineCodes(mi++, (byte) 0x0F);
1521 setMachineCodes(mi++, (byte) 0xAF);
1522 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1523 if (lister != null) lister.RRFD(miStart, "IMUL", dstReg, srcIndex, srcScale, srcDisp);
1524 }
1525
1526 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1527 public final void emitIMUL2_Reg_Abs(GPR dstReg, Address srcDisp) {
1528 int miStart = mi;
1529 generateREXprefix(false, dstReg, null, null);
1530 setMachineCodes(mi++, (byte) 0x0F);
1531 setMachineCodes(mi++, (byte) 0xAF);
1532 emitAbsRegOperands(srcDisp, dstReg);
1533 if (lister != null) lister.RRA(miStart, "IMUL", dstReg, srcDisp);
1534 }
1535
1536 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1537 public final void emitIMUL2_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1538 int miStart = mi;
1539 generateREXprefix(false, dstReg, srcIndex, srcBase);
1540 setMachineCodes(mi++, (byte) 0x0F);
1541 setMachineCodes(mi++, (byte) 0xAF);
1542 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1543 if (lister != null) lister.RRXD(miStart, "IMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1544 }
1545
1546 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1547 public final void emitIMUL2_Reg_Imm(GPR dstReg, int imm) {
1548 int miStart = mi;
1549 generateREXprefix(false, dstReg, null, null);
1550 if (fits(imm,8)) {
1551 setMachineCodes(mi++, (byte) 0x6B);
1552 emitRegRegOperands(dstReg, dstReg);
1553 emitImm8((byte)imm);
1554 } else {
1555 setMachineCodes(mi++, (byte) 0x69);
1556 emitRegRegOperands(dstReg, dstReg);
1557 emitImm32(imm);
1558 }
1559 if (lister != null) lister.RI(miStart, "IMUL", dstReg, imm);
1560 }
1561
1562 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1563 public final void emitIMUL2_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
1564 int miStart = mi;
1565 generateREXprefix(true, dstReg, null, srcReg);
1566 setMachineCodes(mi++, (byte) 0x0F);
1567 setMachineCodes(mi++, (byte) 0xAF);
1568 emitRegRegOperands(srcReg, dstReg);
1569 if (lister != null) lister.RR(miStart, "IMUL", dstReg, srcReg);
1570 }
1571
1572 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1573 public final void emitIMUL2_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
1574 int miStart = mi;
1575 generateREXprefix(true, dstReg, null, srcBase);
1576 setMachineCodes(mi++, (byte) 0x0F);
1577 setMachineCodes(mi++, (byte) 0xAF);
1578 emitRegIndirectRegOperands(srcBase, dstReg);
1579 if (lister != null) lister.RRN(miStart, "IMUL", dstReg, srcBase);
1580 }
1581
1582 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1583 public final void emitIMUL2_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
1584 int miStart = mi;
1585 generateREXprefix(true, dstReg, null, srcBase);
1586 setMachineCodes(mi++, (byte) 0x0F);
1587 setMachineCodes(mi++, (byte) 0xAF);
1588 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1589 if (lister != null) lister.RRD(miStart, "IMUL", dstReg, srcBase, srcDisp);
1590 }
1591
1592 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1593 public final void emitIMUL2_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1594 int miStart = mi;
1595 generateREXprefix(true, dstReg, srcIndex, null);
1596 setMachineCodes(mi++, (byte) 0x0F);
1597 setMachineCodes(mi++, (byte) 0xAF);
1598 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1599 if (lister != null) lister.RRFD(miStart, "IMUL", dstReg, srcIndex, srcScale, srcDisp);
1600 }
1601
1602 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1603 public final void emitIMUL2_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
1604 int miStart = mi;
1605 generateREXprefix(true, dstReg, null, null);
1606 setMachineCodes(mi++, (byte) 0x0F);
1607 setMachineCodes(mi++, (byte) 0xAF);
1608 emitAbsRegOperands(srcDisp, dstReg);
1609 if (lister != null) lister.RRA(miStart, "IMUL", dstReg, srcDisp);
1610 }
1611
1612 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1613 public final void emitIMUL2_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1614 int miStart = mi;
1615 generateREXprefix(true, dstReg, srcIndex, srcBase);
1616 setMachineCodes(mi++, (byte) 0x0F);
1617 setMachineCodes(mi++, (byte) 0xAF);
1618 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1619 if (lister != null) lister.RRXD(miStart, "IMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1620 }
1621
1622 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1623 public final void emitIMUL2_Reg_Imm_Quad(GPR dstReg, int imm) {
1624 int miStart = mi;
1625 generateREXprefix(true, dstReg, null, null);
1626 if (fits(imm,8)) {
1627 setMachineCodes(mi++, (byte) 0x6B);
1628 emitRegRegOperands(dstReg, dstReg);
1629 emitImm8((byte)imm);
1630 } else {
1631 setMachineCodes(mi++, (byte) 0x69);
1632 emitRegRegOperands(dstReg, dstReg);
1633 emitImm32(imm);
1634 }
1635 if (lister != null) lister.RI(miStart, "IMUL", dstReg, imm);
1636 }
1637
1638 // trap
1639 public final void emitINT_Imm (int v) {
1640 if (VM.VerifyAssertions) VM._assert(v <= 0xFF);
1641 int miStart = mi;
1642 if (v == 3) { // special case interrupt
1643 setMachineCodes(mi++, (byte) 0xCC);
1644 } else {
1645 setMachineCodes(mi++, (byte) 0xCD);
1646 setMachineCodes(mi++, (byte) v);
1647 }
1648 if (lister != null) lister.I(miStart, "INT", v);
1649 }
1650
1651 /**
1652 * Conditionally branch to the given target, i.e.
1653 * <PRE>
1654 * if (cond) then IP = (instruction @ label)
1655 * </PRE>
1656 *
1657 * This emit method is expecting only a forward branch (that is
1658 * what the Label operand means); it creates a ForwardReference
1659 * to the given label, and puts it into the assembler's list of
1660 * references to resolve. This emiiter knows it emits conditional
1661 * branches, so it uses ForwardReference.ConditionalBranch as the
1662 * forward reference type to create.
1663 *
1664 * All forward branches have a label as the branch target; clients
1665 * can arbirarily associate labels and instructions, but must be
1666 * consistent in giving the chosen label as the target of branches
1667 * to an instruction and calling resolveForwardBranches with the
1668 * given label immediately before emitting the target instruction.
1669 * See the header comments of ForwardReference for more details.
1670 *
1671 * @param cond the IA32 ISA condition code bits to mask into opcode
1672 * @param label the label associated with the branch target instrucion
1673 *
1674 * @see org.jikesrvm.compilers.common.assembler.ForwardReference.ConditionalBranch
1675 */
1676 public final void emitJCC_Cond_Label (byte cond, int label) {
1677 int miStart = mi;
1678 ForwardReference r = new ForwardReference.ConditionalBranch(mi, label);
1679 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1680 setMachineCodes(mi++, (byte) 0x0F);
1681 setMachineCodes(mi++, (byte) (0x80 + cond));
1682 mi += 4; // leave space for displacement TODO!! handle short branches
1683 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], label);
1684 }
1685
1686 /**
1687 * Conditionally branch to the given target, i.e.
1688 * <PRE>
1689 * if (cond) then IP = mTarget
1690 * </PRE>
1691 *
1692 * This emit method emits only backward branches (that is what
1693 * branching to an Imm operand means), so it simply writes the
1694 * appropriate binary code without bothering with the forward
1695 * reference mechanism.
1696 *
1697 * @param cond the IA32 ISA condition code bits to mask into opcode
1698 * @param mTarget the method-relative target offset
1699 */
1700 public final void emitJCC_Cond_Imm (byte cond, int mTarget) {
1701 int miStart = mi;
1702 int relOffset = mTarget - (mi + 1 + 1); // address relative to next instruction
1703 if (fits(relOffset, 8)) {
1704 emitCondOpByte((byte)0x70, cond);
1705 emitImm8((byte)relOffset);
1706 } else {
1707 setMachineCodes(mi++, (byte) 0x0F);
1708 emitCondOpByte((byte)0x80, cond);
1709 relOffset = mTarget - (mi + 4); // address relative to next instruction
1710 emitImm32(relOffset);
1711 }
1712 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], relOffset);
1713 }
1714
1715 /**
1716 * Conditionally branch to the given target, i.e.
1717 * <PRE>
1718 * if (cond) then IP = mTarget -or- (instruction @ bTarget)
1719 * </PRE>
1720 *
1721 * This emit method represents a branch that could be either
1722 * forward or backward; it simply calls either the Label or Imm
1723 * emit method.
1724 *
1725 * @see #emitJCC_Cond_Label
1726 * @see #emitJCC_Cond_Imm
1727 *
1728 * @param cond the IA32 ISA condition code bits to mask into opcode
1729 * @param mTarget the method-relative target offset
1730 * @param bTarget the label associated with the branch target instrucion
1731 */
1732 public final void emitJCC_Cond_ImmOrLabel (byte cond, int mTarget, int bTarget) {
1733 if (mTarget == 0) { // forward branch
1734 emitJCC_Cond_Label(cond, bTarget);
1735 } else { // backward branch
1736 emitJCC_Cond_Imm(cond, mTarget);
1737 }
1738 }
1739
1740 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1741 public final void emitLEA_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
1742 int miStart = mi;
1743 generateREXprefix(false, dstReg, null, srcBase);
1744 setMachineCodes(mi++, (byte) 0x8D);
1745 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1746 if (lister != null) lister.RRD(miStart, "LEA", dstReg, srcBase, srcDisp);
1747 }
1748
1749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1750 public final void emitLEA_Reg_RegInd(GPR dstReg, GPR srcBase) {
1751 int miStart = mi;
1752 generateREXprefix(false, dstReg, null, srcBase);
1753 setMachineCodes(mi++, (byte) 0x8D);
1754 emitRegIndirectRegOperands(srcBase, dstReg);
1755 if (lister != null) lister.RRN(miStart, "LEA", dstReg, srcBase);
1756 }
1757
1758 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1759 public final void emitLEA_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1760 int miStart = mi;
1761 generateREXprefix(false, dstReg, srcIndex, null);
1762 setMachineCodes(mi++, (byte) 0x8D);
1763 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1764 if (lister != null) lister.RRFD(miStart, "LEA", dstReg, srcIndex, srcScale, srcDisp);
1765 }
1766
1767 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1768 public final void emitLEA_Reg_Abs(GPR dstReg, Address srcDisp) {
1769 int miStart = mi;
1770 generateREXprefix(false, dstReg, null, null);
1771 setMachineCodes(mi++, (byte) 0x8D);
1772 emitAbsRegOperands(srcDisp, dstReg);
1773 if (lister != null) lister.RRA(miStart, "LEA", dstReg, srcDisp);
1774 }
1775
1776 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1777 public final void emitLEA_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1778 int miStart = mi;
1779 generateREXprefix(false, dstReg, srcIndex, srcBase);
1780 setMachineCodes(mi++, (byte) 0x8D);
1781 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1782 if (lister != null) lister.RRXD(miStart, "LEA", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1783 }
1784
1785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1786 public final void emitLEA_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
1787 int miStart = mi;
1788 generateREXprefix(true, dstReg, null, srcBase);
1789 setMachineCodes(mi++, (byte) 0x8D);
1790 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1791 if (lister != null) lister.RRD(miStart, "LEA", dstReg, srcBase, srcDisp);
1792 }
1793
1794 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1795 public final void emitLEA_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
1796 int miStart = mi;
1797 generateREXprefix(true, dstReg, null, srcBase);
1798 setMachineCodes(mi++, (byte) 0x8D);
1799 emitRegIndirectRegOperands(srcBase, dstReg);
1800 if (lister != null) lister.RRN(miStart, "LEA", dstReg, srcBase);
1801 }
1802
1803 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1804 public final void emitLEA_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1805 int miStart = mi;
1806 generateREXprefix(true, dstReg, srcIndex, null);
1807 setMachineCodes(mi++, (byte) 0x8D);
1808 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1809 if (lister != null) lister.RRFD(miStart, "LEA", dstReg, srcIndex, srcScale, srcDisp);
1810 }
1811
1812 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1813 public final void emitLEA_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
1814 int miStart = mi;
1815 generateREXprefix(true, dstReg, null, null);
1816 setMachineCodes(mi++, (byte) 0x8D);
1817 emitAbsRegOperands(srcDisp, dstReg);
1818 if (lister != null) lister.RRA(miStart, "LEA", dstReg, srcDisp);
1819 }
1820
1821 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1822 public final void emitLEA_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1823 int miStart = mi;
1824 generateREXprefix(true, dstReg, srcIndex, srcBase);
1825 setMachineCodes(mi++, (byte) 0x8D);
1826 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1827 if (lister != null) lister.RRXD(miStart, "LEA", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1828 }
1829
1830 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1831 public final void emitMOV_Reg_Imm(GPR dstReg, int imm) {
1832 int miStart = mi;
1833 generateREXprefix(false, null, null, dstReg);
1834 setMachineCodes(mi++, (byte) (0xB8 | dstReg.value()));
1835 emitImm32(imm);
1836 if (lister != null) lister.RI(miStart, "MOV", dstReg, imm);
1837 }
1838
1839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1840 public final void emitMOV_Reg_Imm_Quad(GPR dstReg, long imm) {
1841 int miStart = mi;
1842 generateREXprefix(true, null, null, dstReg);
1843 setMachineCodes(mi++, (byte) (0xB8 | dstReg.value()));
1844 emitImm64(imm);
1845 if (lister != null) lister.RI(miStart, "MOV", dstReg, imm);
1846 }
1847
1848 /** pop address and goto it */
1849 public final void emitRET () {
1850 int miStart = mi;
1851 setMachineCodes(mi++, (byte) 0xC3);
1852 if (lister != null) lister.OP(miStart, "RET");
1853 }
1854
1855 /** pop address and goto it, pop parameterBytes additional bytes */
1856 public final void emitRET_Imm (int parameterBytes) {
1857 int miStart = mi;
1858 if (parameterBytes == 0) {
1859 setMachineCodes(mi++, (byte) 0xC3);
1860 if (lister != null) lister.OP(miStart, "RET");
1861 } else {
1862 setMachineCodes(mi++, (byte) 0xC2);
1863 emitImm16(parameterBytes);
1864 if (VM.VerifyAssertions) VM._assert ((parameterBytes & 0xffff0000) == 0);
1865 if (lister != null) lister.I(miStart, "RET", parameterBytes);
1866 }
1867 }
1868
1869 /** allocate stack frame for procedure */
1870 public final void emitENTER_Imm (int frameSize) {
1871 int miStart = mi;
1872 setMachineCodes(mi++, (byte) 0xC8);
1873 emitImm16(frameSize);
1874 setMachineCodes(mi++, (byte) 0x0);
1875 if (lister != null) lister.I(miStart, "ENTER", frameSize);
1876 }
1877
1878 /** sign extends EAX into EDX */
1879 public final void emitCDQ () {
1880 int miStart = mi;
1881 setMachineCodes(mi++, (byte)0x99);
1882 if (lister != null) lister.OP(miStart, "CDQ");
1883 }
1884
1885 /** sign extends RAX into RDX */
1886 public final void emitCDO () {
1887 int miStart = mi;
1888 generateREXprefix(true, null, null, null);
1889 setMachineCodes(mi++, (byte)0x99);
1890 if (lister != null) lister.OP(miStart, "CDO");
1891 }
1892
1893 /** sign extends EAX into RDX */
1894 public final void emitCDQE () {
1895 int miStart = mi;
1896 generateREXprefix(true, null, null, null);
1897 setMachineCodes(mi++, (byte)0x98);
1898 if (lister != null) lister.OP(miStart, "CDQE");
1899 }
1900
1901 /**
1902 * Read time stamp into edx:eax, on Linux this appears to be unprivileged.
1903 * <pre>
1904 * edx:eax <- time stamp counter
1905 * </pre>
1906 */
1907 public final void emitRDTSC() {
1908 int miStart = mi;
1909 setMachineCodes(mi++, (byte) 0x0F);
1910 setMachineCodes(mi++, (byte) 0x31);
1911 if (lister != null) lister.OP(miStart, "RDTSC");
1912 }
1913
1914 /** software prefetch of value in EDI */
1915 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1916 public final void emitPREFETCHNTA_RegInd(GPR srcReg) {
1917 if (VM.VerifyAssertions) VM._assert(srcReg == EDI);
1918 int miStart = mi;
1919 setMachineCodes(mi++, (byte) 0x0F);
1920 setMachineCodes(mi++,(byte) 0x18);
1921 emitRegRegOperands(GPR.getForOpcode(0), GPR.getForOpcode(0));
1922 if (lister != null) lister.R(miStart, "PREFETCHNTA", srcReg);
1923 }
1924
1925 /** Suggest to process that a a compare for a spin lock has just failed */
1926 public final void emitPAUSE () {
1927 int miStart = mi;
1928 setMachineCodes(mi++, (byte) 0xF3);
1929 setMachineCodes(mi++,(byte) 0x90);
1930 if (lister != null) lister.OP(miStart, "PAUSE");
1931 }
1932
1933 /**
1934 * Compare and exchange 8 bytes
1935 * <PRE>
1936 * cmpxchg8b [dst + disp]
1937 * </PRE>
1938 */
1939 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1940 public final void emitCMPXCHG8B_RegDisp(GPR base, Offset disp) {
1941 int miStart = mi;
1942 generateREXprefix(false, null, null, base);
1943 setMachineCodes(mi++, (byte) 0x0F);
1944 setMachineCodes(mi++, (byte) 0xC7);
1945 emitRegDispRegOperands(base, disp, GPR.getForOpcode(1));
1946 if (lister != null) lister.RD(miStart, "CMPXCHG8B" , base, disp);
1947 }
1948
1949 /**
1950 * Compare and exchange 8 bytes
1951 * <PRE>
1952 * cmpxchg8b [dst]
1953 * </PRE>
1954 */
1955 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1956 public final void emitCMPXCHG8B_RegInd(GPR base) {
1957 int miStart = mi;
1958 generateREXprefix(false, null, null, base);
1959 setMachineCodes(mi++, (byte) 0x0F);
1960 setMachineCodes(mi++, (byte) 0xC7);
1961 emitRegIndirectRegOperands(base, GPR.getForOpcode(1));
1962 if (lister != null) lister.R(miStart, "CMPXCHG8B" , base);
1963 }
1964
1965 /**
1966 * Compare and exchange 8 bytes
1967 * <PRE>
1968 * cmpxchg8b [index2<<scale2 + disp2]
1969 * </PRE>
1970 */
1971 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1972 public final void emitCMPXCHG8B_RegOff(GPR index2, short scale2, Offset disp2) {
1973 int miStart = mi;
1974 generateREXprefix(false, null, index2, null);
1975 setMachineCodes(mi++, (byte) 0x0F);
1976 setMachineCodes(mi++, (byte) 0xC7);
1977 emitRegOffRegOperands(index2, scale2, disp2, GPR.getForOpcode(1));
1978 if (lister != null) lister.RFD(miStart, "CMPXCHG8B", index2, scale2, disp2);
1979 }
1980
1981 /**
1982 * Compare and exchange 8 bytes
1983 * <PRE>
1984 * cmpxchg8b [base + index2<<scale2 + disp2]
1985 * </PRE>
1986 */
1987 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1988 public final void emitCMPXCHG8B_RegIdx(GPR base2, GPR index2, short scale2, Offset disp2) {
1989 int miStart = mi;
1990 generateREXprefix(false, null, index2, base2);
1991 setMachineCodes(mi++, (byte) 0x0F);
1992 setMachineCodes(mi++, (byte) 0xC7);
1993 emitSIBRegOperands(base2, index2, scale2, disp2, GPR.getForOpcode(1));
1994 if (lister != null) lister.RXD(miStart, "CMPXCHG8B", base2, index2, scale2, disp2);
1995 }
1996
1997 /** Store AH into Flags */
1998 public final void emitSAHF () {
1999 int miStart = mi;
2000 setMachineCodes(mi++, (byte) 0x9E);
2001 if (lister != null) lister.OP(miStart, "SAHF");
2002 }
2003
2004 /**
2005 * Emit NOP instruction
2006 *
2007 * @param length size of NOP instruction required
2008 */
2009 public final void emitNOP (int length) {
2010 int miStart = mi;
2011 switch (length) {
2012 case 0:
2013 break;
2014 case 1:
2015 setMachineCodes(mi++, (byte) 0x90);
2016 break;
2017 case 2:
2018 setMachineCodes(mi++, (byte) 0x66);
2019 setMachineCodes(mi++, (byte) 0x90);
2020 break;
2021 case 3:
2022 setMachineCodes(mi++, (byte) 0x0F);
2023 setMachineCodes(mi++, (byte) 0x1F);
2024 setMachineCodes(mi++, (byte) 0x00);
2025 break;
2026 case 4:
2027 setMachineCodes(mi++, (byte) 0x0F);
2028 setMachineCodes(mi++, (byte) 0x1F);
2029 setMachineCodes(mi++, (byte) 0x40);
2030 setMachineCodes(mi++, (byte) 0x00);
2031 break;
2032 case 5:
2033 setMachineCodes(mi++, (byte) 0x0F);
2034 setMachineCodes(mi++, (byte) 0x1F);
2035 setMachineCodes(mi++, (byte) 0x44);
2036 setMachineCodes(mi++, (byte) 0x00);
2037 setMachineCodes(mi++, (byte) 0x00);
2038 break;
2039 case 6:
2040 setMachineCodes(mi++, (byte) 0x66);
2041 setMachineCodes(mi++, (byte) 0x0F);
2042 setMachineCodes(mi++, (byte) 0x1F);
2043 setMachineCodes(mi++, (byte) 0x44);
2044 setMachineCodes(mi++, (byte) 0x00);
2045 setMachineCodes(mi++, (byte) 0x00);
2046 break;
2047 case 7:
2048 setMachineCodes(mi++, (byte) 0x0F);
2049 setMachineCodes(mi++, (byte) 0x1F);
2050 setMachineCodes(mi++, (byte) 0x80);
2051 setMachineCodes(mi++, (byte) 0x00);
2052 setMachineCodes(mi++, (byte) 0x00);
2053 setMachineCodes(mi++, (byte) 0x00);
2054 setMachineCodes(mi++, (byte) 0x00);
2055 break;
2056 case 8:
2057 setMachineCodes(mi++, (byte) 0x0F);
2058 setMachineCodes(mi++, (byte) 0x1F);
2059 setMachineCodes(mi++, (byte) 0x84);
2060 setMachineCodes(mi++, (byte) 0x00);
2061 setMachineCodes(mi++, (byte) 0x00);
2062 setMachineCodes(mi++, (byte) 0x00);
2063 setMachineCodes(mi++, (byte) 0x00);
2064 setMachineCodes(mi++, (byte) 0x00);
2065 break;
2066 case 9:
2067 setMachineCodes(mi++, (byte) 0x66);
2068 setMachineCodes(mi++, (byte) 0x0F);
2069 setMachineCodes(mi++, (byte) 0x1F);
2070 setMachineCodes(mi++, (byte) 0x84);
2071 setMachineCodes(mi++, (byte) 0x00);
2072 setMachineCodes(mi++, (byte) 0x00);
2073 setMachineCodes(mi++, (byte) 0x00);
2074 setMachineCodes(mi++, (byte) 0x00);
2075 setMachineCodes(mi++, (byte) 0x00);
2076 break;
2077 default:
2078 throw new Error("Unexpected NOP length "+length);
2079 }
2080 if (lister != null) lister.OP(miStart, "NOP");
2081 }
2082
2083 ////////////////////////////////////////////
2084 // hand-coded floating point instructions //
2085 ////////////////////////////////////////////
2086
2087 /**
2088 * Empty MMX technology state
2089 * <PRE>
2090 * emms
2091 * </PRE>
2092 */
2093 public final void emitEMMS() {
2094 int miStart = mi;
2095 setMachineCodes(mi++, (byte) 0x0F);
2096 setMachineCodes(mi++, (byte) 0x77);
2097 if (lister != null) lister.OP(miStart, "EMMS");
2098 }
2099
2100 /** x87 floating point conditional moves */
2101 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
2102 public final void emitFCMOV_Cond_Reg_Reg(byte cond, FPR reg1, FPR reg2) {
2103 int miStart = mi;
2104 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
2105 switch (cond) {
2106 case LLT:
2107 setMachineCodes(mi++, (byte) 0xDA);
2108 setMachineCodes(mi++, (byte) (0xC0 + reg2.value()));
2109 break;
2110 case EQ:
2111 setMachineCodes(mi++, (byte) 0xDA);
2112 setMachineCodes(mi++, (byte) (0xC8 + reg2.value()));
2113 break;
2114 case LLE:
2115 setMachineCodes(mi++, (byte) 0xDA);
2116 setMachineCodes(mi++, (byte) (0xD0 + reg2.value()));
2117 break;
2118 case PE:
2119 setMachineCodes(mi++, (byte) 0xDA);
2120 setMachineCodes(mi++, (byte) (0xD8 + reg2.value()));
2121 break;
2122 case LGE:
2123 setMachineCodes(mi++, (byte) 0xDB);
2124 setMachineCodes(mi++, (byte) (0xC0 + reg2.value()));
2125 break;
2126 case NE:
2127 setMachineCodes(mi++, (byte) 0xDB);
2128 setMachineCodes(mi++, (byte) (0xC8 + reg2.value()));
2129 break;
2130 case LGT:
2131 setMachineCodes(mi++, (byte) 0xDB);
2132 setMachineCodes(mi++, (byte) (0xD0 + reg2.value()));
2133 break;
2134 case PO:
2135 setMachineCodes(mi++, (byte) 0xDB);
2136 setMachineCodes(mi++, (byte) (0xD8 + reg2.value()));
2137 break;
2138 default:
2139 if (VM.VerifyAssertions) VM._assert(VM.NOT_REACHED);
2140 }
2141 if (lister != null) lister.RR(miStart, "FCMOV" + CONDITION[cond], reg1, reg2);
2142 }
2143
2144 /** x87 floating point push of ST(i) into ST(0) */
2145 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2146 public final void emitFLD_Reg_Reg(FPR destReg, FPR srcReg) {
2147 int miStart = mi;
2148 if (VM.VerifyAssertions) VM._assert(destReg == FP0);
2149 setMachineCodes(mi++, (byte) 0xD9);
2150 setMachineCodes(mi++, (byte) (0xC0 + srcReg.value()));
2151 if (lister != null) lister.R(miStart, "FLD", srcReg);
2152 }
2153
2154 // floating point copy of ST(0) into ST(I)
2155 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2156 public final void emitFST_Reg_Reg(FPR destReg, FPR srcReg) {
2157 int miStart = mi;
2158 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
2159 setMachineCodes(mi++, (byte) 0xDD);
2160 setMachineCodes(mi++, (byte) (0xD0 + destReg.value()));
2161 if (lister != null) lister.R(miStart, "FST", destReg);
2162 }
2163
2164 // floating point pop of ST(0) into ST(I)
2165 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2166 public final void emitFSTP_Reg_Reg(FPR destReg, FPR srcReg) {
2167 int miStart = mi;
2168 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
2169 setMachineCodes(mi++, (byte) 0xDD);
2170 setMachineCodes(mi++, (byte) (0xD8 + destReg.value()));
2171 if (lister != null) lister.R(miStart, "FST", destReg);
2172 }
2173
2174 // Change Sign: Top of FPU register stack -= Top og FPU register stack
2175 public final void emitFCHS () {
2176 int miStart = mi;
2177 setMachineCodes(mi++, (byte) 0xD9);
2178 setMachineCodes(mi++, (byte) 0xE0);
2179 if (lister != null) lister.OP(miStart, "FADD32");
2180 }
2181
2182 public final void emitFUCOMPP () {
2183 int miStart = mi;
2184 setMachineCodes(mi++, (byte) 0xDA);
2185 setMachineCodes(mi++, (byte) 0xE9);
2186 if (lister != null) lister.OP(miStart, "FUCOMPP");
2187 }
2188
2189 // Store Status Word into AX register/noexecptions
2190 public final void emitFNSTSW () {
2191 int miStart = mi;
2192 setMachineCodes(mi++, (byte) 0xDF);
2193 setMachineCodes(mi++, (byte) 0xE0);
2194 if (lister != null) lister.OP(miStart, "FNSTSW");
2195 }
2196
2197 // Real Remainder:
2198 // Top of FPU register stack <- ST(0) - (Q*ST(1)
2199 // Q is the interger value obtained from truncating
2200 // ST(0)/ST(1) toward 0
2201 public final void emitFPREM () {
2202 int miStart = mi;
2203 setMachineCodes(mi++, (byte) 0xD9);
2204 setMachineCodes(mi++, (byte) 0xF8);
2205 if (lister != null) lister.OP(miStart, "FPREM");
2206 }
2207
2208 // Blow away floating point state
2209 public final void emitFINIT() {
2210 int miStart = mi;
2211 setMachineCodes(mi++, (byte) 0x9B);
2212 setMachineCodes(mi++, (byte) 0xDB);
2213 setMachineCodes(mi++, (byte) 0xE3);
2214 if (lister != null) lister.OP(miStart, "FINIT");
2215 }
2216
2217 // Blow away floating point state
2218 // Pending exceptions??? Don't tell me about pending exceptions!!
2219 public final void emitFNINIT() {
2220 int miStart = mi;
2221 setMachineCodes(mi++, (byte) 0xDB);
2222 setMachineCodes(mi++, (byte) 0xE3);
2223 if (lister != null) lister.OP(miStart, "FNINIT");
2224 }
2225
2226 /** Declare we are no longer using FP register */
2227 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2228 public final void emitFFREE_Reg(FPR reg) {
2229 int miStart = mi;
2230 setMachineCodes(mi++, (byte) 0xDD);
2231 setMachineCodes(mi++, (byte) ( (byte)0xC0 + reg.value() ));
2232 if (lister != null) lister.R(miStart, "FFREE", reg);
2233 }
2234
2235 /** The dreaded FXCH (symbol of all that's wrong with x87 floating point) */
2236 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2237 public final void emitFXCH_Reg_Reg(FPR regOne, FPR regTwo) {
2238 int miStart = mi;
2239
2240 // at least one reg must not be FP0
2241 FPR nonZeroReg = FP0; // :)
2242 if (regOne == FP0 && regTwo == FP0)
2243 // do nothing; this is stupid
2244 return;
2245 else if (regOne == FP0 && regTwo != FP0)
2246 nonZeroReg = regTwo;
2247 else if (regTwo == FP0 && regOne != FP0)
2248 nonZeroReg = regOne;
2249
2250 // if not, bad instruction, so die
2251 if (nonZeroReg == FP0)
2252 VM._assert(false, "FXCH of " + regOne + ", " + regTwo);
2253
2254 // generate it, with special case (of course) for FP1
2255 setMachineCodes(mi++, (byte) 0xD9);
2256 if (nonZeroReg == FP1)
2257 setMachineCodes(mi++, (byte) 0xC9);
2258 else
2259 setMachineCodes(mi++, (byte) (0xC8 | nonZeroReg.value()));
2260
2261 // list it
2262 if (lister != null) lister.R(miStart, "FXCH", nonZeroReg);
2263 }
2264
2265 /*
2266 * BELOW HERE ARE AUTOMATICALLY-GENERATED INSTRUCTIONS. DO NOT EDIT.
2267 *
2268 * These instructions are generated by genAssembler.sh in the
2269 * src-generated/ia32-assembler directory. Please make all needed
2270 * edits to that script.
2271 */
2272 /**
2273 * Generate a register(indirect)--register ADC. That is,
2274 * <PRE>
2275 * [dstBase] +CF= srcReg
2276 * </PRE>
2277 *
2278 * @param dstBase the destination base
2279 * @param srcReg the source register
2280 */
2281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2282 public final void emitADC_RegInd_Reg(GPR dstBase, GPR srcReg) {
2283 int miStart = mi;
2284 // no group 1 to 4 prefix byte
2285 generateREXprefix(false, srcReg, null, dstBase);
2286 // single byte opcode
2287 setMachineCodes(mi++, (byte) 0x11);
2288 emitRegIndirectRegOperands(dstBase, srcReg);
2289 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2290 }
2291
2292 /**
2293 * Generate a register-offset--register ADC. That is,
2294 * <PRE>
2295 * [dstReg<<dstScale + dstDisp] +CF= srcReg
2296 * </PRE>
2297 *
2298 * @param dstIndex the destination index register
2299 * @param dstScale the destination shift amount
2300 * @param dstDisp the destination displacement
2301 * @param srcReg the source register
2302 */
2303 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2304 public final void emitADC_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2305 int miStart = mi;
2306 // no group 1 to 4 prefix byte
2307 generateREXprefix(false, srcReg, dstIndex, null);
2308 // single byte opcode
2309 setMachineCodes(mi++, (byte) 0x11);
2310 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2311 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2312 }
2313
2314 /**
2315 * Generate a absolute--register ADC. That is,
2316 * <PRE>
2317 * [dstDisp] +CF= srcReg
2318 * </PRE>
2319 *
2320 * @param dstDisp the destination address
2321 * @param srcReg the source register
2322 */
2323 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2324 public final void emitADC_Abs_Reg(Address dstDisp, GPR srcReg) {
2325 int miStart = mi;
2326 // no group 1 to 4 prefix byte
2327 generateREXprefix(false, srcReg, null, null);
2328 // single byte opcode
2329 setMachineCodes(mi++, (byte) 0x11);
2330 emitAbsRegOperands(dstDisp, srcReg);
2331 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2332 }
2333
2334 /**
2335 * Generate a register-index--register ADC. That is,
2336 * <PRE>
2337 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= srcReg
2338 * </PRE>
2339 *
2340 * @param dstBase the base register
2341 * @param dstIndex the destination index register
2342 * @param dstScale the destination shift amount
2343 * @param dstDisp the destination displacement
2344 * @param srcReg the source register
2345 */
2346 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2347 public final void emitADC_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2348 int miStart = mi;
2349 // no group 1 to 4 prefix byte
2350 generateREXprefix(false, srcReg, dstIndex, dstBase);
2351 // single byte opcode
2352 setMachineCodes(mi++, (byte) 0x11);
2353 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2354 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2355 }
2356
2357 /**
2358 * Generate a register-displacement--register ADC. That is,
2359 * <PRE>
2360 * [dstBase + dstDisp] +CF= srcReg
2361 * </PRE>
2362 *
2363 * @param dstBase the base register
2364 * @param dstDisp the destination displacement
2365 * @param srcReg the source register
2366 */
2367 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2368 public final void emitADC_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
2369 int miStart = mi;
2370 // no group 1 to 4 prefix byte
2371 generateREXprefix(false, srcReg, null, dstBase);
2372 // single byte opcode
2373 setMachineCodes(mi++, (byte) 0x11);
2374 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2375 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2376 }
2377
2378 /**
2379 * Generate a register--register ADC. That is,
2380 * <PRE>
2381 * dstReg +CF= srcReg
2382 * </PRE>
2383 *
2384 * @param dstReg the destination register
2385 * @param srcReg the source register
2386 */
2387 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2388 public final void emitADC_Reg_Reg(GPR dstReg, GPR srcReg) {
2389 int miStart = mi;
2390 // no group 1 to 4 prefix byte
2391 generateREXprefix(false, srcReg, null, dstReg);
2392 // single byte opcode
2393 setMachineCodes(mi++, (byte) 0x11);
2394 emitRegRegOperands(dstReg, srcReg);
2395 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2396 }
2397
2398 /**
2399 * Generate a register--register-displacement ADC. That is,
2400 * <PRE>
2401 * dstReg +CF= [srcReg + srcDisp]
2402 * </PRE>
2403 *
2404 * @param dstReg the destination register
2405 * @param srcBase the source register
2406 * @param srcDisp the source displacement
2407 */
2408 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2409 public final void emitADC_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
2410 int miStart = mi;
2411 // no group 1 to 4 prefix byte
2412 generateREXprefix(false, dstReg, null, srcBase);
2413 // single byte opcode
2414 setMachineCodes(mi++, (byte) 0x13);
2415 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2416 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2417 }
2418
2419 /**
2420 * Generate a register--register-offset ADC. That is,
2421 * <PRE>
2422 * dstReg +CF= [srcIndex<<srcScale + srcDisp]
2423 * </PRE>
2424 *
2425 * @param dstReg the destination register
2426 * @param srcIndex the source index register
2427 * @param srcScale the source shift amount
2428 * @param srcDisp the source displacement
2429 */
2430 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2431 public final void emitADC_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2432 int miStart = mi;
2433 // no group 1 to 4 prefix byte
2434 generateREXprefix(false, dstReg, srcIndex, null);
2435 // single byte opcode
2436 setMachineCodes(mi++, (byte) 0x13);
2437 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2438 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2439 }
2440
2441 /**
2442 * Generate a register--register-offset ADC. That is,
2443 * <PRE>
2444 * dstReg +CF= [srcDisp]
2445 * </PRE>
2446 *
2447 * @param dstReg the destination register
2448 * @param srcDisp the source displacement
2449 */
2450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2451 public final void emitADC_Reg_Abs(GPR dstReg, Address srcDisp) {
2452 int miStart = mi;
2453 // no group 1 to 4 prefix byte
2454 generateREXprefix(false, dstReg, null, null);
2455 // single byte opcode
2456 setMachineCodes(mi++, (byte) 0x13);
2457 emitAbsRegOperands(srcDisp, dstReg);
2458 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2459 }
2460
2461 /**
2462 * Generate a register--register-offset ADC. That is,
2463 * <PRE>
2464 * dstReg +CF= [srcBase + srcIndex<<srcScale + srcDisp]
2465 * </PRE>
2466 *
2467 * @param dstReg the destination register
2468 * @param srcBase the source base register
2469 * @param srcIndex the source index register
2470 * @param srcScale the source shift amount
2471 * @param srcDisp the source displacement
2472 */
2473 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2474 public final void emitADC_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2475 int miStart = mi;
2476 // no group 1 to 4 prefix byte
2477 generateREXprefix(false, dstReg, srcIndex, srcBase);
2478 // single byte opcode
2479 setMachineCodes(mi++, (byte) 0x13);
2480 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2481 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2482 }
2483
2484 /**
2485 * Generate a register--register(indirect) ADC. That is,
2486 * <PRE>
2487 * dstReg +CF= [srcBase]
2488 * </PRE>
2489 *
2490 * @param dstReg the destination register
2491 * @param srcBase the source base register
2492 */
2493 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2494 public final void emitADC_Reg_RegInd(GPR dstReg, GPR srcBase) {
2495 int miStart = mi;
2496 // no group 1 to 4 prefix byte
2497 generateREXprefix(false, dstReg, null, srcBase);
2498 // single byte opcode
2499 setMachineCodes(mi++, (byte) 0x13);
2500 emitRegIndirectRegOperands(srcBase, dstReg);
2501 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2502 }
2503
2504 /**
2505 * Generate a register(indirect)--register ADC. That is,
2506 * <PRE>
2507 * [dstBase] +CF= (word) srcReg
2508 * </PRE>
2509 *
2510 * @param dstBase the destination base
2511 * @param srcReg the source register
2512 */
2513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2514 public final void emitADC_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
2515 int miStart = mi;
2516 setMachineCodes(mi++, (byte) 0x66);
2517 generateREXprefix(false, srcReg, null, dstBase);
2518 // single byte opcode
2519 setMachineCodes(mi++, (byte) 0x11);
2520 emitRegIndirectRegOperands(dstBase, srcReg);
2521 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2522 }
2523
2524 /**
2525 * Generate a register-offset--register ADC. That is,
2526 * <PRE>
2527 * [dstReg<<dstScale + dstDisp] +CF= (word) srcReg
2528 * </PRE>
2529 *
2530 * @param dstIndex the destination index register
2531 * @param dstScale the destination shift amount
2532 * @param dstDisp the destination displacement
2533 * @param srcReg the source register
2534 */
2535 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2536 public final void emitADC_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2537 int miStart = mi;
2538 setMachineCodes(mi++, (byte) 0x66);
2539 generateREXprefix(false, srcReg, dstIndex, null);
2540 // single byte opcode
2541 setMachineCodes(mi++, (byte) 0x11);
2542 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2543 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2544 }
2545
2546 /**
2547 * Generate a absolute--register ADC. That is,
2548 * <PRE>
2549 * [dstDisp] +CF= (word) srcReg
2550 * </PRE>
2551 *
2552 * @param dstDisp the destination address
2553 * @param srcReg the source register
2554 */
2555 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2556 public final void emitADC_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
2557 int miStart = mi;
2558 setMachineCodes(mi++, (byte) 0x66);
2559 generateREXprefix(false, srcReg, null, null);
2560 // single byte opcode
2561 setMachineCodes(mi++, (byte) 0x11);
2562 emitAbsRegOperands(dstDisp, srcReg);
2563 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2564 }
2565
2566 /**
2567 * Generate a register-index--register ADC. That is,
2568 * <PRE>
2569 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (word) srcReg
2570 * </PRE>
2571 *
2572 * @param dstBase the base register
2573 * @param dstIndex the destination index register
2574 * @param dstScale the destination shift amount
2575 * @param dstDisp the destination displacement
2576 * @param srcReg the source register
2577 */
2578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2579 public final void emitADC_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2580 int miStart = mi;
2581 setMachineCodes(mi++, (byte) 0x66);
2582 generateREXprefix(false, srcReg, dstIndex, dstBase);
2583 // single byte opcode
2584 setMachineCodes(mi++, (byte) 0x11);
2585 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2586 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2587 }
2588
2589 /**
2590 * Generate a register-displacement--register ADC. That is,
2591 * <PRE>
2592 * [dstBase + dstDisp] +CF= (word) srcReg
2593 * </PRE>
2594 *
2595 * @param dstBase the base register
2596 * @param dstDisp the destination displacement
2597 * @param srcReg the source register
2598 */
2599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2600 public final void emitADC_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
2601 int miStart = mi;
2602 setMachineCodes(mi++, (byte) 0x66);
2603 generateREXprefix(false, srcReg, null, dstBase);
2604 // single byte opcode
2605 setMachineCodes(mi++, (byte) 0x11);
2606 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2607 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2608 }
2609
2610 /**
2611 * Generate a register--register ADC. That is,
2612 * <PRE>
2613 * dstReg +CF= (word) srcReg
2614 * </PRE>
2615 *
2616 * @param dstReg the destination register
2617 * @param srcReg the source register
2618 */
2619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2620 public final void emitADC_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
2621 int miStart = mi;
2622 setMachineCodes(mi++, (byte) 0x66);
2623 generateREXprefix(false, srcReg, null, dstReg);
2624 // single byte opcode
2625 setMachineCodes(mi++, (byte) 0x11);
2626 emitRegRegOperands(dstReg, srcReg);
2627 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2628 }
2629
2630 /**
2631 * Generate a register--register-displacement ADC. That is,
2632 * <PRE>
2633 * dstReg +CF= (word) [srcReg + srcDisp]
2634 * </PRE>
2635 *
2636 * @param dstReg the destination register
2637 * @param srcBase the source register
2638 * @param srcDisp the source displacement
2639 */
2640 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2641 public final void emitADC_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
2642 int miStart = mi;
2643 setMachineCodes(mi++, (byte) 0x66);
2644 generateREXprefix(false, dstReg, null, srcBase);
2645 // single byte opcode
2646 setMachineCodes(mi++, (byte) 0x13);
2647 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2648 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2649 }
2650
2651 /**
2652 * Generate a register--register-offset ADC. That is,
2653 * <PRE>
2654 * dstReg +CF= (word) [srcIndex<<srcScale + srcDisp]
2655 * </PRE>
2656 *
2657 * @param dstReg the destination register
2658 * @param srcIndex the source index register
2659 * @param srcScale the source shift amount
2660 * @param srcDisp the source displacement
2661 */
2662 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2663 public final void emitADC_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2664 int miStart = mi;
2665 setMachineCodes(mi++, (byte) 0x66);
2666 generateREXprefix(false, dstReg, srcIndex, null);
2667 // single byte opcode
2668 setMachineCodes(mi++, (byte) 0x13);
2669 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2670 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2671 }
2672
2673 /**
2674 * Generate a register--register-offset ADC. That is,
2675 * <PRE>
2676 * dstReg +CF= (word) [srcDisp]
2677 * </PRE>
2678 *
2679 * @param dstReg the destination register
2680 * @param srcDisp the source displacement
2681 */
2682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2683 public final void emitADC_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
2684 int miStart = mi;
2685 setMachineCodes(mi++, (byte) 0x66);
2686 generateREXprefix(false, dstReg, null, null);
2687 // single byte opcode
2688 setMachineCodes(mi++, (byte) 0x13);
2689 emitAbsRegOperands(srcDisp, dstReg);
2690 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2691 }
2692
2693 /**
2694 * Generate a register--register-offset ADC. That is,
2695 * <PRE>
2696 * dstReg +CF= (word) [srcBase + srcIndex<<srcScale + srcDisp]
2697 * </PRE>
2698 *
2699 * @param dstReg the destination register
2700 * @param srcBase the source base register
2701 * @param srcIndex the source index register
2702 * @param srcScale the source shift amount
2703 * @param srcDisp the source displacement
2704 */
2705 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2706 public final void emitADC_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2707 int miStart = mi;
2708 setMachineCodes(mi++, (byte) 0x66);
2709 generateREXprefix(false, dstReg, srcIndex, srcBase);
2710 // single byte opcode
2711 setMachineCodes(mi++, (byte) 0x13);
2712 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2713 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2714 }
2715
2716 /**
2717 * Generate a register--register(indirect) ADC. That is,
2718 * <PRE>
2719 * dstReg +CF= (word) [srcBase]
2720 * </PRE>
2721 *
2722 * @param dstReg the destination register
2723 * @param srcBase the source base register
2724 */
2725 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2726 public final void emitADC_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
2727 int miStart = mi;
2728 setMachineCodes(mi++, (byte) 0x66);
2729 generateREXprefix(false, dstReg, null, srcBase);
2730 // single byte opcode
2731 setMachineCodes(mi++, (byte) 0x13);
2732 emitRegIndirectRegOperands(srcBase, dstReg);
2733 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2734 }
2735
2736 /**
2737 * Generate a register(indirect)--register ADC. That is,
2738 * <PRE>
2739 * [dstBase] +CF= (quad) srcReg
2740 * </PRE>
2741 *
2742 * @param dstBase the destination base
2743 * @param srcReg the source register
2744 */
2745 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2746 public final void emitADC_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
2747 int miStart = mi;
2748 // no group 1 to 4 prefix byte
2749 generateREXprefix(true, srcReg, null, dstBase);
2750 // single byte opcode
2751 setMachineCodes(mi++, (byte) 0x11);
2752 emitRegIndirectRegOperands(dstBase, srcReg);
2753 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2754 }
2755
2756 /**
2757 * Generate a register-offset--register ADC. That is,
2758 * <PRE>
2759 * [dstReg<<dstScale + dstDisp] +CF= (quad) srcReg
2760 * </PRE>
2761 *
2762 * @param dstIndex the destination index register
2763 * @param dstScale the destination shift amount
2764 * @param dstDisp the destination displacement
2765 * @param srcReg the source register
2766 */
2767 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2768 public final void emitADC_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2769 int miStart = mi;
2770 // no group 1 to 4 prefix byte
2771 generateREXprefix(true, srcReg, dstIndex, null);
2772 // single byte opcode
2773 setMachineCodes(mi++, (byte) 0x11);
2774 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2775 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2776 }
2777
2778 /**
2779 * Generate a absolute--register ADC. That is,
2780 * <PRE>
2781 * [dstDisp] +CF= (quad) srcReg
2782 * </PRE>
2783 *
2784 * @param dstDisp the destination address
2785 * @param srcReg the source register
2786 */
2787 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2788 public final void emitADC_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
2789 int miStart = mi;
2790 // no group 1 to 4 prefix byte
2791 generateREXprefix(true, srcReg, null, null);
2792 // single byte opcode
2793 setMachineCodes(mi++, (byte) 0x11);
2794 emitAbsRegOperands(dstDisp, srcReg);
2795 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2796 }
2797
2798 /**
2799 * Generate a register-index--register ADC. That is,
2800 * <PRE>
2801 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (quad) srcReg
2802 * </PRE>
2803 *
2804 * @param dstBase the base register
2805 * @param dstIndex the destination index register
2806 * @param dstScale the destination shift amount
2807 * @param dstDisp the destination displacement
2808 * @param srcReg the source register
2809 */
2810 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2811 public final void emitADC_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2812 int miStart = mi;
2813 // no group 1 to 4 prefix byte
2814 generateREXprefix(true, srcReg, dstIndex, dstBase);
2815 // single byte opcode
2816 setMachineCodes(mi++, (byte) 0x11);
2817 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2818 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2819 }
2820
2821 /**
2822 * Generate a register-displacement--register ADC. That is,
2823 * <PRE>
2824 * [dstBase + dstDisp] +CF= (quad) srcReg
2825 * </PRE>
2826 *
2827 * @param dstBase the base register
2828 * @param dstDisp the destination displacement
2829 * @param srcReg the source register
2830 */
2831 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2832 public final void emitADC_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
2833 int miStart = mi;
2834 // no group 1 to 4 prefix byte
2835 generateREXprefix(true, srcReg, null, dstBase);
2836 // single byte opcode
2837 setMachineCodes(mi++, (byte) 0x11);
2838 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2839 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2840 }
2841
2842 /**
2843 * Generate a register--register ADC. That is,
2844 * <PRE>
2845 * dstReg +CF= (quad) srcReg
2846 * </PRE>
2847 *
2848 * @param dstReg the destination register
2849 * @param srcReg the source register
2850 */
2851 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2852 public final void emitADC_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
2853 int miStart = mi;
2854 // no group 1 to 4 prefix byte
2855 generateREXprefix(true, srcReg, null, dstReg);
2856 // single byte opcode
2857 setMachineCodes(mi++, (byte) 0x11);
2858 emitRegRegOperands(dstReg, srcReg);
2859 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2860 }
2861
2862 /**
2863 * Generate a register--register-displacement ADC. That is,
2864 * <PRE>
2865 * dstReg +CF= (quad) [srcReg + srcDisp]
2866 * </PRE>
2867 *
2868 * @param dstReg the destination register
2869 * @param srcBase the source register
2870 * @param srcDisp the source displacement
2871 */
2872 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2873 public final void emitADC_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
2874 int miStart = mi;
2875 // no group 1 to 4 prefix byte
2876 generateREXprefix(true, dstReg, null, srcBase);
2877 // single byte opcode
2878 setMachineCodes(mi++, (byte) 0x13);
2879 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2880 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2881 }
2882
2883 /**
2884 * Generate a register--register-offset ADC. That is,
2885 * <PRE>
2886 * dstReg +CF= (quad) [srcIndex<<srcScale + srcDisp]
2887 * </PRE>
2888 *
2889 * @param dstReg the destination register
2890 * @param srcIndex the source index register
2891 * @param srcScale the source shift amount
2892 * @param srcDisp the source displacement
2893 */
2894 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2895 public final void emitADC_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2896 int miStart = mi;
2897 // no group 1 to 4 prefix byte
2898 generateREXprefix(true, dstReg, srcIndex, null);
2899 // single byte opcode
2900 setMachineCodes(mi++, (byte) 0x13);
2901 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2902 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2903 }
2904
2905 /**
2906 * Generate a register--register-offset ADC. That is,
2907 * <PRE>
2908 * dstReg +CF= (quad) [srcDisp]
2909 * </PRE>
2910 *
2911 * @param dstReg the destination register
2912 * @param srcDisp the source displacement
2913 */
2914 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2915 public final void emitADC_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
2916 int miStart = mi;
2917 // no group 1 to 4 prefix byte
2918 generateREXprefix(true, dstReg, null, null);
2919 // single byte opcode
2920 setMachineCodes(mi++, (byte) 0x13);
2921 emitAbsRegOperands(srcDisp, dstReg);
2922 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2923 }
2924
2925 /**
2926 * Generate a register--register-offset ADC. That is,
2927 * <PRE>
2928 * dstReg +CF= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
2929 * </PRE>
2930 *
2931 * @param dstReg the destination register
2932 * @param srcBase the source base register
2933 * @param srcIndex the source index register
2934 * @param srcScale the source shift amount
2935 * @param srcDisp the source displacement
2936 */
2937 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2938 public final void emitADC_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2939 int miStart = mi;
2940 // no group 1 to 4 prefix byte
2941 generateREXprefix(true, dstReg, srcIndex, srcBase);
2942 // single byte opcode
2943 setMachineCodes(mi++, (byte) 0x13);
2944 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2945 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2946 }
2947
2948 /**
2949 * Generate a register--register(indirect) ADC. That is,
2950 * <PRE>
2951 * dstReg +CF= (quad) [srcBase]
2952 * </PRE>
2953 *
2954 * @param dstReg the destination register
2955 * @param srcBase the source base register
2956 */
2957 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2958 public final void emitADC_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
2959 int miStart = mi;
2960 // no group 1 to 4 prefix byte
2961 generateREXprefix(true, dstReg, null, srcBase);
2962 // single byte opcode
2963 setMachineCodes(mi++, (byte) 0x13);
2964 emitRegIndirectRegOperands(srcBase, dstReg);
2965 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2966 }
2967
2968 /**
2969 * Generate a register(indirect)--register ADC. That is,
2970 * <PRE>
2971 * [dstBase] +CF= (byte) srcReg
2972 * </PRE>
2973 *
2974 * @param dstBase the destination base
2975 * @param srcReg the source register
2976 */
2977 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2978 public final void emitADC_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
2979 int miStart = mi;
2980 // no group 1 to 4 prefix byte
2981 generateREXprefix(false, srcReg, null, dstBase);
2982 // single byte opcode
2983 setMachineCodes(mi++, (byte) 0x10);
2984 emitRegIndirectRegOperands(dstBase, srcReg);
2985 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2986 }
2987
2988 /**
2989 * Generate a register-offset--register ADC. That is,
2990 * <PRE>
2991 * [dstReg<<dstScale + dstDisp] +CF= (byte) srcReg
2992 * </PRE>
2993 *
2994 * @param dstIndex the destination index register
2995 * @param dstScale the destination shift amount
2996 * @param dstDisp the destination displacement
2997 * @param srcReg the source register
2998 */
2999 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
3000 public final void emitADC_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3001 int miStart = mi;
3002 // no group 1 to 4 prefix byte
3003 generateREXprefix(false, srcReg, dstIndex, null);
3004 // single byte opcode
3005 setMachineCodes(mi++, (byte) 0x10);
3006 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
3007 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
3008 }
3009
3010 /**
3011 * Generate a absolute--register ADC. That is,
3012 * <PRE>
3013 * [dstDisp] +CF= (byte) srcReg
3014 * </PRE>
3015 *
3016 * @param dstDisp the destination address
3017 * @param srcReg the source register
3018 */
3019 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
3020 public final void emitADC_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
3021 int miStart = mi;
3022 // no group 1 to 4 prefix byte
3023 generateREXprefix(false, srcReg, null, null);
3024 // single byte opcode
3025 setMachineCodes(mi++, (byte) 0x10);
3026 emitAbsRegOperands(dstDisp, srcReg);
3027 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
3028 }
3029
3030 /**
3031 * Generate a register-index--register ADC. That is,
3032 * <PRE>
3033 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (byte) srcReg
3034 * </PRE>
3035 *
3036 * @param dstBase the base register
3037 * @param dstIndex the destination index register
3038 * @param dstScale the destination shift amount
3039 * @param dstDisp the destination displacement
3040 * @param srcReg the source register
3041 */
3042 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
3043 public final void emitADC_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3044 int miStart = mi;
3045 // no group 1 to 4 prefix byte
3046 generateREXprefix(false, srcReg, dstIndex, dstBase);
3047 // single byte opcode
3048 setMachineCodes(mi++, (byte) 0x10);
3049 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
3050 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
3051 }
3052
3053 /**
3054 * Generate a register-displacement--register ADC. That is,
3055 * <PRE>
3056 * [dstBase + dstDisp] +CF= (byte) srcReg
3057 * </PRE>
3058 *
3059 * @param dstBase the base register
3060 * @param dstDisp the destination displacement
3061 * @param srcReg the source register
3062 */
3063 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
3064 public final void emitADC_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
3065 int miStart = mi;
3066 // no group 1 to 4 prefix byte
3067 generateREXprefix(false, srcReg, null, dstBase);
3068 // single byte opcode
3069 setMachineCodes(mi++, (byte) 0x10);
3070 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
3071 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
3072 }
3073
3074 /**
3075 * Generate a register--register ADC. That is,
3076 * <PRE>
3077 * dstReg +CF= (byte) srcReg
3078 * </PRE>
3079 *
3080 * @param dstReg the destination register
3081 * @param srcReg the source register
3082 */
3083 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3084 public final void emitADC_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
3085 int miStart = mi;
3086 // no group 1 to 4 prefix byte
3087 generateREXprefix(false, srcReg, null, dstReg);
3088 // single byte opcode
3089 setMachineCodes(mi++, (byte) 0x10);
3090 emitRegRegOperands(dstReg, srcReg);
3091 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
3092 }
3093
3094 /**
3095 * Generate a register--register-displacement ADC. That is,
3096 * <PRE>
3097 * dstReg +CF= (byte) [srcReg + srcDisp]
3098 * </PRE>
3099 *
3100 * @param dstReg the destination register
3101 * @param srcBase the source register
3102 * @param srcDisp the source displacement
3103 */
3104 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3105 public final void emitADC_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
3106 int miStart = mi;
3107 // no group 1 to 4 prefix byte
3108 generateREXprefix(false, dstReg, null, srcBase);
3109 // single byte opcode
3110 setMachineCodes(mi++, (byte) 0x12);
3111 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
3112 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
3113 }
3114
3115 /**
3116 * Generate a register--register-offset ADC. That is,
3117 * <PRE>
3118 * dstReg +CF= (byte) [srcIndex<<srcScale + srcDisp]
3119 * </PRE>
3120 *
3121 * @param dstReg the destination register
3122 * @param srcIndex the source index register
3123 * @param srcScale the source shift amount
3124 * @param srcDisp the source displacement
3125 */
3126 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3127 public final void emitADC_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
3128 int miStart = mi;
3129 // no group 1 to 4 prefix byte
3130 generateREXprefix(false, dstReg, srcIndex, null);
3131 // single byte opcode
3132 setMachineCodes(mi++, (byte) 0x12);
3133 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
3134 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
3135 }
3136
3137 /**
3138 * Generate a register--register-offset ADC. That is,
3139 * <PRE>
3140 * dstReg +CF= (byte) [srcDisp]
3141 * </PRE>
3142 *
3143 * @param dstReg the destination register
3144 * @param srcDisp the source displacement
3145 */
3146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3147 public final void emitADC_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
3148 int miStart = mi;
3149 // no group 1 to 4 prefix byte
3150 generateREXprefix(false, dstReg, null, null);
3151 // single byte opcode
3152 setMachineCodes(mi++, (byte) 0x12);
3153 emitAbsRegOperands(srcDisp, dstReg);
3154 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
3155 }
3156
3157 /**
3158 * Generate a register--register-offset ADC. That is,
3159 * <PRE>
3160 * dstReg +CF= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
3161 * </PRE>
3162 *
3163 * @param dstReg the destination register
3164 * @param srcBase the source base register
3165 * @param srcIndex the source index register
3166 * @param srcScale the source shift amount
3167 * @param srcDisp the source displacement
3168 */
3169 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
3170 public final void emitADC_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
3171 int miStart = mi;
3172 // no group 1 to 4 prefix byte
3173 generateREXprefix(false, dstReg, srcIndex, srcBase);
3174 // single byte opcode
3175 setMachineCodes(mi++, (byte) 0x12);
3176 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
3177 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
3178 }
3179
3180 /**
3181 * Generate a register--register(indirect) ADC. That is,
3182 * <PRE>
3183 * dstReg +CF= (byte) [srcBase]
3184 * </PRE>
3185 *
3186 * @param dstReg the destination register
3187 * @param srcBase the source base register
3188 */
3189 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3190 public final void emitADC_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
3191 int miStart = mi;
3192 // no group 1 to 4 prefix byte
3193 generateREXprefix(false, dstReg, null, srcBase);
3194 // single byte opcode
3195 setMachineCodes(mi++, (byte) 0x12);
3196 emitRegIndirectRegOperands(srcBase, dstReg);
3197 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
3198 }
3199
3200 /**
3201 * Generate a register--immediate ADC. That is,
3202 * <PRE>
3203 * dstReg +CF= imm
3204 * </PRE>
3205 *
3206 * @param dstReg the destination register
3207 * @param imm immediate
3208 */
3209 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3210 public final void emitADC_Reg_Imm(GPR dstReg, int imm) {
3211 int miStart = mi;
3212 // no group 1 to 4 prefix byte
3213 generateREXprefix(false, null, null, dstReg);
3214 // single byte opcode
3215 if (fits(imm,8)) {
3216 setMachineCodes(mi++, (byte) 0x83);
3217 // "register 0x2" is really part of the opcode
3218 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3219 emitImm8((byte)imm);
3220 } else if (dstReg == EAX) {
3221 setMachineCodes(mi++, (byte) 0x15);
3222 emitImm32(imm);
3223 } else {
3224 setMachineCodes(mi++, (byte) 0x81);
3225 // "register 0x2" is really part of the opcode
3226 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3227 emitImm32(imm);
3228 }
3229 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3230 }
3231
3232 /**
3233 * Generate a register-displacement--immediate ADC. That is,
3234 * <PRE>
3235 * [dstBase + dstDisp] +CF= imm
3236 * </PRE>
3237 *
3238 * @param dstBase the destination register
3239 * @param dstDisp the destination displacement
3240 * @param imm immediate
3241 */
3242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3243 public final void emitADC_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
3244 int miStart = mi;
3245 // no group 1 to 4 prefix byte
3246 generateREXprefix(false, null, null, dstBase);
3247 // single byte opcode
3248 if (fits(imm,8)) {
3249 setMachineCodes(mi++, (byte) 0x83);
3250 // "register 0x2" is really part of the opcode
3251 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3252 emitImm8((byte)imm);
3253 } else {
3254 setMachineCodes(mi++, (byte) 0x81);
3255 // "register 0x2" is really part of the opcode
3256 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3257 emitImm32(imm);
3258 }
3259 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3260 }
3261
3262 /**
3263 * Generate a register-offset--immediate ADC. That is,
3264 * <PRE>
3265 * [dstIndex<<dstScale + dstDisp] +CF= imm
3266 * </PRE>
3267 *
3268 * @param dstIndex the destination index register
3269 * @param dstScale the destination shift amount
3270 * @param dstDisp the destination displacement
3271 * @param imm immediate
3272 */
3273 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3274 public final void emitADC_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3275 int miStart = mi;
3276 // no group 1 to 4 prefix byte
3277 generateREXprefix(false, null, dstIndex, null);
3278 // single byte opcode
3279 if (fits(imm,8)) {
3280 setMachineCodes(mi++, (byte) 0x83);
3281 // "register 0x2" is really part of the opcode
3282 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3283 emitImm8((byte)imm);
3284 } else {
3285 setMachineCodes(mi++, (byte) 0x81);
3286 // "register 0x2" is really part of the opcode
3287 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3288 emitImm32(imm);
3289 }
3290 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3291 }
3292
3293 /**
3294 * Generate a absolute--immediate ADC. That is,
3295 * <PRE>
3296 * [dstDisp] +CF= imm
3297 * </PRE>
3298 *
3299 * @param dstDisp the destination displacement
3300 * @param imm immediate
3301 */
3302 public final void emitADC_Abs_Imm(Address dstDisp, int imm) {
3303 int miStart = mi;
3304 // no group 1 to 4 prefix byte
3305 generateREXprefix(false, null, null, null);
3306 // single byte opcode
3307 if (fits(imm,8)) {
3308 setMachineCodes(mi++, (byte) 0x83);
3309 // "register 0x2" is really part of the opcode
3310 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3311 emitImm8((byte)imm);
3312 } else {
3313 setMachineCodes(mi++, (byte) 0x81);
3314 // "register 0x2" is really part of the opcode
3315 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3316 emitImm32(imm);
3317 }
3318 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3319 }
3320
3321 /**
3322 * Generate a register-index--immediate ADC. That is,
3323 * <PRE>
3324 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= imm
3325 * </PRE>
3326 *
3327 * @param dstBase the destination base register
3328 * @param dstIndex the destination index register
3329 * @param dstScale the destination shift amount
3330 * @param dstDisp the destination displacement
3331 * @param imm immediate
3332 */
3333 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3334 public final void emitADC_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3335 int miStart = mi;
3336 // no group 1 to 4 prefix byte
3337 generateREXprefix(false, null, dstIndex, dstBase);
3338 // single byte opcode
3339 if (fits(imm,8)) {
3340 setMachineCodes(mi++, (byte) 0x83);
3341 // "register 0x2" is really part of the opcode
3342 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3343 emitImm8((byte)imm);
3344 } else {
3345 setMachineCodes(mi++, (byte) 0x81);
3346 // "register 0x2" is really part of the opcode
3347 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3348 emitImm32(imm);
3349 }
3350 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3351 }
3352
3353 /**
3354 * Generate a register(indirect)--immediate ADC. That is,
3355 * <PRE>
3356 * [dstBase] +CF= imm
3357 * </PRE>
3358 *
3359 * @param dstBase the destination base register
3360 * @param imm immediate
3361 */
3362 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3363 public final void emitADC_RegInd_Imm(GPR dstBase, int imm) {
3364 int miStart = mi;
3365 // no group 1 to 4 prefix byte
3366 generateREXprefix(false, null, null, dstBase);
3367 // single byte opcode
3368 if (fits(imm,8)) {
3369 setMachineCodes(mi++, (byte) 0x83);
3370 // "register 0x2" is really part of the opcode
3371 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3372 emitImm8((byte)imm);
3373 } else {
3374 setMachineCodes(mi++, (byte) 0x81);
3375 // "register 0x2" is really part of the opcode
3376 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3377 emitImm32(imm);
3378 }
3379 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3380 }
3381
3382 /**
3383 * Generate a register--immediate ADC. That is,
3384 * <PRE>
3385 * dstReg +CF= (word) imm
3386 * </PRE>
3387 *
3388 * @param dstReg the destination register
3389 * @param imm immediate
3390 */
3391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3392 public final void emitADC_Reg_Imm_Word(GPR dstReg, int imm) {
3393 int miStart = mi;
3394 setMachineCodes(mi++, (byte) 0x66);
3395 generateREXprefix(false, null, null, dstReg);
3396 // single byte opcode
3397 if (fits(imm,8)) {
3398 setMachineCodes(mi++, (byte) 0x83);
3399 // "register 0x2" is really part of the opcode
3400 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3401 emitImm8((byte)imm);
3402 } else if (dstReg == EAX) {
3403 setMachineCodes(mi++, (byte) 0x15);
3404 emitImm16(imm);
3405 } else {
3406 setMachineCodes(mi++, (byte) 0x81);
3407 // "register 0x2" is really part of the opcode
3408 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3409 emitImm16(imm);
3410 }
3411 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3412 }
3413
3414 /**
3415 * Generate a register-displacement--immediate ADC. That is,
3416 * <PRE>
3417 * [dstBase + dstDisp] +CF= (word) imm
3418 * </PRE>
3419 *
3420 * @param dstBase the destination register
3421 * @param dstDisp the destination displacement
3422 * @param imm immediate
3423 */
3424 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3425 public final void emitADC_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
3426 int miStart = mi;
3427 setMachineCodes(mi++, (byte) 0x66);
3428 generateREXprefix(false, null, null, dstBase);
3429 // single byte opcode
3430 if (fits(imm,8)) {
3431 setMachineCodes(mi++, (byte) 0x83);
3432 // "register 0x2" is really part of the opcode
3433 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3434 emitImm8((byte)imm);
3435 } else {
3436 setMachineCodes(mi++, (byte) 0x81);
3437 // "register 0x2" is really part of the opcode
3438 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3439 emitImm16(imm);
3440 }
3441 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3442 }
3443
3444 /**
3445 * Generate a register-offset--immediate ADC. That is,
3446 * <PRE>
3447 * [dstIndex<<dstScale + dstDisp] +CF= (word) imm
3448 * </PRE>
3449 *
3450 * @param dstIndex the destination index register
3451 * @param dstScale the destination shift amount
3452 * @param dstDisp the destination displacement
3453 * @param imm immediate
3454 */
3455 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3456 public final void emitADC_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3457 int miStart = mi;
3458 setMachineCodes(mi++, (byte) 0x66);
3459 generateREXprefix(false, null, dstIndex, null);
3460 // single byte opcode
3461 if (fits(imm,8)) {
3462 setMachineCodes(mi++, (byte) 0x83);
3463 // "register 0x2" is really part of the opcode
3464 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3465 emitImm8((byte)imm);
3466 } else {
3467 setMachineCodes(mi++, (byte) 0x81);
3468 // "register 0x2" is really part of the opcode
3469 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3470 emitImm16(imm);
3471 }
3472 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3473 }
3474
3475 /**
3476 * Generate a absolute--immediate ADC. That is,
3477 * <PRE>
3478 * [dstDisp] +CF= (word) imm
3479 * </PRE>
3480 *
3481 * @param dstDisp the destination displacement
3482 * @param imm immediate
3483 */
3484 public final void emitADC_Abs_Imm_Word(Address dstDisp, int imm) {
3485 int miStart = mi;
3486 setMachineCodes(mi++, (byte) 0x66);
3487 generateREXprefix(false, null, null, null);
3488 // single byte opcode
3489 if (fits(imm,8)) {
3490 setMachineCodes(mi++, (byte) 0x83);
3491 // "register 0x2" is really part of the opcode
3492 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3493 emitImm8((byte)imm);
3494 } else {
3495 setMachineCodes(mi++, (byte) 0x81);
3496 // "register 0x2" is really part of the opcode
3497 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3498 emitImm16(imm);
3499 }
3500 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3501 }
3502
3503 /**
3504 * Generate a register-index--immediate ADC. That is,
3505 * <PRE>
3506 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (word) imm
3507 * </PRE>
3508 *
3509 * @param dstBase the destination base register
3510 * @param dstIndex the destination index register
3511 * @param dstScale the destination shift amount
3512 * @param dstDisp the destination displacement
3513 * @param imm immediate
3514 */
3515 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3516 public final void emitADC_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3517 int miStart = mi;
3518 setMachineCodes(mi++, (byte) 0x66);
3519 generateREXprefix(false, null, dstIndex, dstBase);
3520 // single byte opcode
3521 if (fits(imm,8)) {
3522 setMachineCodes(mi++, (byte) 0x83);
3523 // "register 0x2" is really part of the opcode
3524 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3525 emitImm8((byte)imm);
3526 } else {
3527 setMachineCodes(mi++, (byte) 0x81);
3528 // "register 0x2" is really part of the opcode
3529 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3530 emitImm16(imm);
3531 }
3532 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3533 }
3534
3535 /**
3536 * Generate a register(indirect)--immediate ADC. That is,
3537 * <PRE>
3538 * [dstBase] +CF= (word) imm
3539 * </PRE>
3540 *
3541 * @param dstBase the destination base register
3542 * @param imm immediate
3543 */
3544 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3545 public final void emitADC_RegInd_Imm_Word(GPR dstBase, int imm) {
3546 int miStart = mi;
3547 setMachineCodes(mi++, (byte) 0x66);
3548 generateREXprefix(false, null, null, dstBase);
3549 // single byte opcode
3550 if (fits(imm,8)) {
3551 setMachineCodes(mi++, (byte) 0x83);
3552 // "register 0x2" is really part of the opcode
3553 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3554 emitImm8((byte)imm);
3555 } else {
3556 setMachineCodes(mi++, (byte) 0x81);
3557 // "register 0x2" is really part of the opcode
3558 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3559 emitImm16(imm);
3560 }
3561 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3562 }
3563
3564 /**
3565 * Generate a register--immediate ADC. That is,
3566 * <PRE>
3567 * dstReg +CF= (quad) imm
3568 * </PRE>
3569 *
3570 * @param dstReg the destination register
3571 * @param imm immediate
3572 */
3573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3574 public final void emitADC_Reg_Imm_Quad(GPR dstReg, int imm) {
3575 int miStart = mi;
3576 // no group 1 to 4 prefix byte
3577 generateREXprefix(true, null, null, dstReg);
3578 // single byte opcode
3579 if (fits(imm,8)) {
3580 setMachineCodes(mi++, (byte) 0x83);
3581 // "register 0x2" is really part of the opcode
3582 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3583 emitImm8((byte)imm);
3584 } else if (dstReg == EAX) {
3585 setMachineCodes(mi++, (byte) 0x15);
3586 emitImm32(imm);
3587 } else {
3588 setMachineCodes(mi++, (byte) 0x81);
3589 // "register 0x2" is really part of the opcode
3590 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3591 emitImm32(imm);
3592 }
3593 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3594 }
3595
3596 /**
3597 * Generate a register-displacement--immediate ADC. That is,
3598 * <PRE>
3599 * [dstBase + dstDisp] +CF= (quad) imm
3600 * </PRE>
3601 *
3602 * @param dstBase the destination register
3603 * @param dstDisp the destination displacement
3604 * @param imm immediate
3605 */
3606 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3607 public final void emitADC_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
3608 int miStart = mi;
3609 // no group 1 to 4 prefix byte
3610 generateREXprefix(true, null, null, dstBase);
3611 // single byte opcode
3612 if (fits(imm,8)) {
3613 setMachineCodes(mi++, (byte) 0x83);
3614 // "register 0x2" is really part of the opcode
3615 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3616 emitImm8((byte)imm);
3617 } else {
3618 setMachineCodes(mi++, (byte) 0x81);
3619 // "register 0x2" is really part of the opcode
3620 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3621 emitImm32(imm);
3622 }
3623 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3624 }
3625
3626 /**
3627 * Generate a register-offset--immediate ADC. That is,
3628 * <PRE>
3629 * [dstIndex<<dstScale + dstDisp] +CF= (quad) imm
3630 * </PRE>
3631 *
3632 * @param dstIndex the destination index register
3633 * @param dstScale the destination shift amount
3634 * @param dstDisp the destination displacement
3635 * @param imm immediate
3636 */
3637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3638 public final void emitADC_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3639 int miStart = mi;
3640 // no group 1 to 4 prefix byte
3641 generateREXprefix(true, null, dstIndex, null);
3642 // single byte opcode
3643 if (fits(imm,8)) {
3644 setMachineCodes(mi++, (byte) 0x83);
3645 // "register 0x2" is really part of the opcode
3646 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3647 emitImm8((byte)imm);
3648 } else {
3649 setMachineCodes(mi++, (byte) 0x81);
3650 // "register 0x2" is really part of the opcode
3651 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3652 emitImm32(imm);
3653 }
3654 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3655 }
3656
3657 /**
3658 * Generate a absolute--immediate ADC. That is,
3659 * <PRE>
3660 * [dstDisp] +CF= (quad) imm
3661 * </PRE>
3662 *
3663 * @param dstDisp the destination displacement
3664 * @param imm immediate
3665 */
3666 public final void emitADC_Abs_Imm_Quad(Address dstDisp, int imm) {
3667 int miStart = mi;
3668 // no group 1 to 4 prefix byte
3669 generateREXprefix(true, null, null, null);
3670 // single byte opcode
3671 if (fits(imm,8)) {
3672 setMachineCodes(mi++, (byte) 0x83);
3673 // "register 0x2" is really part of the opcode
3674 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3675 emitImm8((byte)imm);
3676 } else {
3677 setMachineCodes(mi++, (byte) 0x81);
3678 // "register 0x2" is really part of the opcode
3679 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3680 emitImm32(imm);
3681 }
3682 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3683 }
3684
3685 /**
3686 * Generate a register-index--immediate ADC. That is,
3687 * <PRE>
3688 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (quad) imm
3689 * </PRE>
3690 *
3691 * @param dstBase the destination base register
3692 * @param dstIndex the destination index register
3693 * @param dstScale the destination shift amount
3694 * @param dstDisp the destination displacement
3695 * @param imm immediate
3696 */
3697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3698 public final void emitADC_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3699 int miStart = mi;
3700 // no group 1 to 4 prefix byte
3701 generateREXprefix(true, null, dstIndex, dstBase);
3702 // single byte opcode
3703 if (fits(imm,8)) {
3704 setMachineCodes(mi++, (byte) 0x83);
3705 // "register 0x2" is really part of the opcode
3706 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3707 emitImm8((byte)imm);
3708 } else {
3709 setMachineCodes(mi++, (byte) 0x81);
3710 // "register 0x2" is really part of the opcode
3711 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3712 emitImm32(imm);
3713 }
3714 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3715 }
3716
3717 /**
3718 * Generate a register(indirect)--immediate ADC. That is,
3719 * <PRE>
3720 * [dstBase] +CF= (quad) imm
3721 * </PRE>
3722 *
3723 * @param dstBase the destination base register
3724 * @param imm immediate
3725 */
3726 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3727 public final void emitADC_RegInd_Imm_Quad(GPR dstBase, int imm) {
3728 int miStart = mi;
3729 // no group 1 to 4 prefix byte
3730 generateREXprefix(true, null, null, dstBase);
3731 // single byte opcode
3732 if (fits(imm,8)) {
3733 setMachineCodes(mi++, (byte) 0x83);
3734 // "register 0x2" is really part of the opcode
3735 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3736 emitImm8((byte)imm);
3737 } else {
3738 setMachineCodes(mi++, (byte) 0x81);
3739 // "register 0x2" is really part of the opcode
3740 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3741 emitImm32(imm);
3742 }
3743 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3744 }
3745
3746 /**
3747 * Generate a register--immediate ADC. That is,
3748 * <PRE>
3749 * dstReg +CF= (byte) imm
3750 * </PRE>
3751 *
3752 * @param dstReg the destination register
3753 * @param imm immediate
3754 */
3755 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3756 public final void emitADC_Reg_Imm_Byte(GPR dstReg, int imm) {
3757 int miStart = mi;
3758 if (dstReg == EAX) {
3759 setMachineCodes(mi++, (byte) 0x14);
3760 emitImm8(imm);
3761 } else {
3762 generateREXprefix(false, null, null, dstReg);
3763 setMachineCodes(mi++, (byte) 0x80);
3764 // "register 0x2" is really part of the opcode
3765 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3766 emitImm8(imm);
3767 }
3768 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3769 }
3770
3771 /**
3772 * Generate a register-displacement--immediate ADC. That is,
3773 * <PRE>
3774 * [dstBase + dstDisp] +CF= (byte) imm
3775 * </PRE>
3776 *
3777 * @param dstBase the destination register
3778 * @param dstDisp the destination displacement
3779 * @param imm immediate
3780 */
3781 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3782 public final void emitADC_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
3783 int miStart = mi;
3784 generateREXprefix(false, null, null, dstBase);
3785 setMachineCodes(mi++, (byte) 0x80);
3786 // "register 0x2" is really part of the opcode
3787 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3788 emitImm8(imm);
3789 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3790 }
3791
3792 /**
3793 * Generate a register-index--immediate ADC. That is,
3794 * <PRE>
3795 * [dstBase + dstIndex<<scale + dstDisp] +CF= (byte) imm
3796 * </PRE>
3797 *
3798 * @param dstBase the destination base register
3799 * @param dstIndex the destination index register
3800 * @param dstScale the destination shift amount
3801 * @param dstDisp the destination displacement
3802 * @param imm immediate
3803 */
3804 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3805 public final void emitADC_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3806 int miStart = mi;
3807 generateREXprefix(false, null, dstIndex, dstBase);
3808 setMachineCodes(mi++, (byte) 0x80);
3809 // "register 0x2" is really part of the opcode
3810 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3811 emitImm8(imm);
3812 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3813 }
3814
3815 /**
3816 * Generate a register-offset--immediate ADC. That is,
3817 * <PRE>
3818 * [dstIndex<<dstScale + dstDisp] +CF= (byte) imm
3819 * </PRE>
3820 *
3821 * @param dstIndex the destination index register
3822 * @param dstScale the destination shift amount
3823 * @param dstDisp the destination displacement
3824 * @param imm immediate
3825 */
3826 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3827 public final void emitADC_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3828 int miStart = mi;
3829 generateREXprefix(false, null, dstIndex, null);
3830 setMachineCodes(mi++, (byte) 0x80);
3831 // "register 0x2" is really part of the opcode
3832 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3833 emitImm8(imm);
3834 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3835 }
3836
3837 /**
3838 * Generate a absolute--immediate ADC. That is,
3839 * <PRE>
3840 * [dstDisp] +CF= (byte) imm
3841 * </PRE>
3842 *
3843 * @param dstDisp the destination displacement
3844 * @param imm immediate
3845 */
3846 public final void emitADC_Abs_Imm_Byte(Address dstDisp, int imm) {
3847 int miStart = mi;
3848 generateREXprefix(false, null, null, null);
3849 setMachineCodes(mi++, (byte) 0x80);
3850 // "register 0x2" is really part of the opcode
3851 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3852 emitImm8(imm);
3853 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3854 }
3855
3856 /**
3857 * Generate a register(indirect)--immediate ADC. That is,
3858 * <PRE>
3859 * [dstBase] +CF= (byte) imm
3860 * </PRE>
3861 *
3862 * @param dstBase the destination base register
3863 * @param imm immediate
3864 */
3865 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3866 public final void emitADC_RegInd_Imm_Byte(GPR dstBase, int imm) {
3867 int miStart = mi;
3868 generateREXprefix(false, null, null, dstBase);
3869 setMachineCodes(mi++, (byte) 0x80);
3870 // "register 0x2" is really part of the opcode
3871 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3872 emitImm8(imm);
3873 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3874 }
3875
3876 /**
3877 * Generate a register(indirect)--register ADD. That is,
3878 * <PRE>
3879 * [dstBase] += srcReg
3880 * </PRE>
3881 *
3882 * @param dstBase the destination base
3883 * @param srcReg the source register
3884 */
3885 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3886 public final void emitADD_RegInd_Reg(GPR dstBase, GPR srcReg) {
3887 int miStart = mi;
3888 // no group 1 to 4 prefix byte
3889 generateREXprefix(false, srcReg, null, dstBase);
3890 // single byte opcode
3891 setMachineCodes(mi++, (byte) 0x01);
3892 emitRegIndirectRegOperands(dstBase, srcReg);
3893 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
3894 }
3895
3896 /**
3897 * Generate a register-offset--register ADD. That is,
3898 * <PRE>
3899 * [dstReg<<dstScale + dstDisp] += srcReg
3900 * </PRE>
3901 *
3902 * @param dstIndex the destination index register
3903 * @param dstScale the destination shift amount
3904 * @param dstDisp the destination displacement
3905 * @param srcReg the source register
3906 */
3907 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
3908 public final void emitADD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3909 int miStart = mi;
3910 // no group 1 to 4 prefix byte
3911 generateREXprefix(false, srcReg, dstIndex, null);
3912 // single byte opcode
3913 setMachineCodes(mi++, (byte) 0x01);
3914 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
3915 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
3916 }
3917
3918 /**
3919 * Generate a absolute--register ADD. That is,
3920 * <PRE>
3921 * [dstDisp] += srcReg
3922 * </PRE>
3923 *
3924 * @param dstDisp the destination address
3925 * @param srcReg the source register
3926 */
3927 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
3928 public final void emitADD_Abs_Reg(Address dstDisp, GPR srcReg) {
3929 int miStart = mi;
3930 // no group 1 to 4 prefix byte
3931 generateREXprefix(false, srcReg, null, null);
3932 // single byte opcode
3933 setMachineCodes(mi++, (byte) 0x01);
3934 emitAbsRegOperands(dstDisp, srcReg);
3935 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
3936 }
3937
3938 /**
3939 * Generate a register-index--register ADD. That is,
3940 * <PRE>
3941 * [dstBase + dstIndex<<dstScale + dstDisp] += srcReg
3942 * </PRE>
3943 *
3944 * @param dstBase the base register
3945 * @param dstIndex the destination index register
3946 * @param dstScale the destination shift amount
3947 * @param dstDisp the destination displacement
3948 * @param srcReg the source register
3949 */
3950 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
3951 public final void emitADD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3952 int miStart = mi;
3953 // no group 1 to 4 prefix byte
3954 generateREXprefix(false, srcReg, dstIndex, dstBase);
3955 // single byte opcode
3956 setMachineCodes(mi++, (byte) 0x01);
3957 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
3958 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
3959 }
3960
3961 /**
3962 * Generate a register-displacement--register ADD. That is,
3963 * <PRE>
3964 * [dstBase + dstDisp] += srcReg
3965 * </PRE>
3966 *
3967 * @param dstBase the base register
3968 * @param dstDisp the destination displacement
3969 * @param srcReg the source register
3970 */
3971 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
3972 public final void emitADD_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
3973 int miStart = mi;
3974 // no group 1 to 4 prefix byte
3975 generateREXprefix(false, srcReg, null, dstBase);
3976 // single byte opcode
3977 setMachineCodes(mi++, (byte) 0x01);
3978 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
3979 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
3980 }
3981
3982 /**
3983 * Generate a register--register ADD. That is,
3984 * <PRE>
3985 * dstReg += srcReg
3986 * </PRE>
3987 *
3988 * @param dstReg the destination register
3989 * @param srcReg the source register
3990 */
3991 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3992 public final void emitADD_Reg_Reg(GPR dstReg, GPR srcReg) {
3993 int miStart = mi;
3994 // no group 1 to 4 prefix byte
3995 generateREXprefix(false, srcReg, null, dstReg);
3996 // single byte opcode
3997 setMachineCodes(mi++, (byte) 0x01);
3998 emitRegRegOperands(dstReg, srcReg);
3999 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4000 }
4001
4002 /**
4003 * Generate a register--register-displacement ADD. That is,
4004 * <PRE>
4005 * dstReg += [srcReg + srcDisp]
4006 * </PRE>
4007 *
4008 * @param dstReg the destination register
4009 * @param srcBase the source register
4010 * @param srcDisp the source displacement
4011 */
4012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4013 public final void emitADD_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
4014 int miStart = mi;
4015 // no group 1 to 4 prefix byte
4016 generateREXprefix(false, dstReg, null, srcBase);
4017 // single byte opcode
4018 setMachineCodes(mi++, (byte) 0x03);
4019 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4020 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4021 }
4022
4023 /**
4024 * Generate a register--register-offset ADD. That is,
4025 * <PRE>
4026 * dstReg += [srcIndex<<srcScale + srcDisp]
4027 * </PRE>
4028 *
4029 * @param dstReg the destination register
4030 * @param srcIndex the source index register
4031 * @param srcScale the source shift amount
4032 * @param srcDisp the source displacement
4033 */
4034 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4035 public final void emitADD_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4036 int miStart = mi;
4037 // no group 1 to 4 prefix byte
4038 generateREXprefix(false, dstReg, srcIndex, null);
4039 // single byte opcode
4040 setMachineCodes(mi++, (byte) 0x03);
4041 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4042 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4043 }
4044
4045 /**
4046 * Generate a register--register-offset ADD. That is,
4047 * <PRE>
4048 * dstReg += [srcDisp]
4049 * </PRE>
4050 *
4051 * @param dstReg the destination register
4052 * @param srcDisp the source displacement
4053 */
4054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4055 public final void emitADD_Reg_Abs(GPR dstReg, Address srcDisp) {
4056 int miStart = mi;
4057 // no group 1 to 4 prefix byte
4058 generateREXprefix(false, dstReg, null, null);
4059 // single byte opcode
4060 setMachineCodes(mi++, (byte) 0x03);
4061 emitAbsRegOperands(srcDisp, dstReg);
4062 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4063 }
4064
4065 /**
4066 * Generate a register--register-offset ADD. That is,
4067 * <PRE>
4068 * dstReg += [srcBase + srcIndex<<srcScale + srcDisp]
4069 * </PRE>
4070 *
4071 * @param dstReg the destination register
4072 * @param srcBase the source base register
4073 * @param srcIndex the source index register
4074 * @param srcScale the source shift amount
4075 * @param srcDisp the source displacement
4076 */
4077 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4078 public final void emitADD_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4079 int miStart = mi;
4080 // no group 1 to 4 prefix byte
4081 generateREXprefix(false, dstReg, srcIndex, srcBase);
4082 // single byte opcode
4083 setMachineCodes(mi++, (byte) 0x03);
4084 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4085 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4086 }
4087
4088 /**
4089 * Generate a register--register(indirect) ADD. That is,
4090 * <PRE>
4091 * dstReg += [srcBase]
4092 * </PRE>
4093 *
4094 * @param dstReg the destination register
4095 * @param srcBase the source base register
4096 */
4097 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4098 public final void emitADD_Reg_RegInd(GPR dstReg, GPR srcBase) {
4099 int miStart = mi;
4100 // no group 1 to 4 prefix byte
4101 generateREXprefix(false, dstReg, null, srcBase);
4102 // single byte opcode
4103 setMachineCodes(mi++, (byte) 0x03);
4104 emitRegIndirectRegOperands(srcBase, dstReg);
4105 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4106 }
4107
4108 /**
4109 * Generate a register(indirect)--register ADD. That is,
4110 * <PRE>
4111 * [dstBase] += (word) srcReg
4112 * </PRE>
4113 *
4114 * @param dstBase the destination base
4115 * @param srcReg the source register
4116 */
4117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4118 public final void emitADD_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
4119 int miStart = mi;
4120 setMachineCodes(mi++, (byte) 0x66);
4121 generateREXprefix(false, srcReg, null, dstBase);
4122 // single byte opcode
4123 setMachineCodes(mi++, (byte) 0x01);
4124 emitRegIndirectRegOperands(dstBase, srcReg);
4125 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4126 }
4127
4128 /**
4129 * Generate a register-offset--register ADD. That is,
4130 * <PRE>
4131 * [dstReg<<dstScale + dstDisp] += (word) srcReg
4132 * </PRE>
4133 *
4134 * @param dstIndex the destination index register
4135 * @param dstScale the destination shift amount
4136 * @param dstDisp the destination displacement
4137 * @param srcReg the source register
4138 */
4139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4140 public final void emitADD_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4141 int miStart = mi;
4142 setMachineCodes(mi++, (byte) 0x66);
4143 generateREXprefix(false, srcReg, dstIndex, null);
4144 // single byte opcode
4145 setMachineCodes(mi++, (byte) 0x01);
4146 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4147 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4148 }
4149
4150 /**
4151 * Generate a absolute--register ADD. That is,
4152 * <PRE>
4153 * [dstDisp] += (word) srcReg
4154 * </PRE>
4155 *
4156 * @param dstDisp the destination address
4157 * @param srcReg the source register
4158 */
4159 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4160 public final void emitADD_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
4161 int miStart = mi;
4162 setMachineCodes(mi++, (byte) 0x66);
4163 generateREXprefix(false, srcReg, null, null);
4164 // single byte opcode
4165 setMachineCodes(mi++, (byte) 0x01);
4166 emitAbsRegOperands(dstDisp, srcReg);
4167 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4168 }
4169
4170 /**
4171 * Generate a register-index--register ADD. That is,
4172 * <PRE>
4173 * [dstBase + dstIndex<<dstScale + dstDisp] += (word) srcReg
4174 * </PRE>
4175 *
4176 * @param dstBase the base register
4177 * @param dstIndex the destination index register
4178 * @param dstScale the destination shift amount
4179 * @param dstDisp the destination displacement
4180 * @param srcReg the source register
4181 */
4182 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4183 public final void emitADD_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4184 int miStart = mi;
4185 setMachineCodes(mi++, (byte) 0x66);
4186 generateREXprefix(false, srcReg, dstIndex, dstBase);
4187 // single byte opcode
4188 setMachineCodes(mi++, (byte) 0x01);
4189 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4190 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4191 }
4192
4193 /**
4194 * Generate a register-displacement--register ADD. That is,
4195 * <PRE>
4196 * [dstBase + dstDisp] += (word) srcReg
4197 * </PRE>
4198 *
4199 * @param dstBase the base register
4200 * @param dstDisp the destination displacement
4201 * @param srcReg the source register
4202 */
4203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4204 public final void emitADD_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
4205 int miStart = mi;
4206 setMachineCodes(mi++, (byte) 0x66);
4207 generateREXprefix(false, srcReg, null, dstBase);
4208 // single byte opcode
4209 setMachineCodes(mi++, (byte) 0x01);
4210 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4211 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4212 }
4213
4214 /**
4215 * Generate a register--register ADD. That is,
4216 * <PRE>
4217 * dstReg += (word) srcReg
4218 * </PRE>
4219 *
4220 * @param dstReg the destination register
4221 * @param srcReg the source register
4222 */
4223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4224 public final void emitADD_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
4225 int miStart = mi;
4226 setMachineCodes(mi++, (byte) 0x66);
4227 generateREXprefix(false, srcReg, null, dstReg);
4228 // single byte opcode
4229 setMachineCodes(mi++, (byte) 0x01);
4230 emitRegRegOperands(dstReg, srcReg);
4231 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4232 }
4233
4234 /**
4235 * Generate a register--register-displacement ADD. That is,
4236 * <PRE>
4237 * dstReg += (word) [srcReg + srcDisp]
4238 * </PRE>
4239 *
4240 * @param dstReg the destination register
4241 * @param srcBase the source register
4242 * @param srcDisp the source displacement
4243 */
4244 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4245 public final void emitADD_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
4246 int miStart = mi;
4247 setMachineCodes(mi++, (byte) 0x66);
4248 generateREXprefix(false, dstReg, null, srcBase);
4249 // single byte opcode
4250 setMachineCodes(mi++, (byte) 0x03);
4251 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4252 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4253 }
4254
4255 /**
4256 * Generate a register--register-offset ADD. That is,
4257 * <PRE>
4258 * dstReg += (word) [srcIndex<<srcScale + srcDisp]
4259 * </PRE>
4260 *
4261 * @param dstReg the destination register
4262 * @param srcIndex the source index register
4263 * @param srcScale the source shift amount
4264 * @param srcDisp the source displacement
4265 */
4266 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4267 public final void emitADD_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4268 int miStart = mi;
4269 setMachineCodes(mi++, (byte) 0x66);
4270 generateREXprefix(false, dstReg, srcIndex, null);
4271 // single byte opcode
4272 setMachineCodes(mi++, (byte) 0x03);
4273 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4274 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4275 }
4276
4277 /**
4278 * Generate a register--register-offset ADD. That is,
4279 * <PRE>
4280 * dstReg += (word) [srcDisp]
4281 * </PRE>
4282 *
4283 * @param dstReg the destination register
4284 * @param srcDisp the source displacement
4285 */
4286 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4287 public final void emitADD_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
4288 int miStart = mi;
4289 setMachineCodes(mi++, (byte) 0x66);
4290 generateREXprefix(false, dstReg, null, null);
4291 // single byte opcode
4292 setMachineCodes(mi++, (byte) 0x03);
4293 emitAbsRegOperands(srcDisp, dstReg);
4294 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4295 }
4296
4297 /**
4298 * Generate a register--register-offset ADD. That is,
4299 * <PRE>
4300 * dstReg += (word) [srcBase + srcIndex<<srcScale + srcDisp]
4301 * </PRE>
4302 *
4303 * @param dstReg the destination register
4304 * @param srcBase the source base register
4305 * @param srcIndex the source index register
4306 * @param srcScale the source shift amount
4307 * @param srcDisp the source displacement
4308 */
4309 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4310 public final void emitADD_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4311 int miStart = mi;
4312 setMachineCodes(mi++, (byte) 0x66);
4313 generateREXprefix(false, dstReg, srcIndex, srcBase);
4314 // single byte opcode
4315 setMachineCodes(mi++, (byte) 0x03);
4316 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4317 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4318 }
4319
4320 /**
4321 * Generate a register--register(indirect) ADD. That is,
4322 * <PRE>
4323 * dstReg += (word) [srcBase]
4324 * </PRE>
4325 *
4326 * @param dstReg the destination register
4327 * @param srcBase the source base register
4328 */
4329 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4330 public final void emitADD_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
4331 int miStart = mi;
4332 setMachineCodes(mi++, (byte) 0x66);
4333 generateREXprefix(false, dstReg, null, srcBase);
4334 // single byte opcode
4335 setMachineCodes(mi++, (byte) 0x03);
4336 emitRegIndirectRegOperands(srcBase, dstReg);
4337 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4338 }
4339
4340 /**
4341 * Generate a register(indirect)--register ADD. That is,
4342 * <PRE>
4343 * [dstBase] += (quad) srcReg
4344 * </PRE>
4345 *
4346 * @param dstBase the destination base
4347 * @param srcReg the source register
4348 */
4349 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4350 public final void emitADD_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
4351 int miStart = mi;
4352 // no group 1 to 4 prefix byte
4353 generateREXprefix(true, srcReg, null, dstBase);
4354 // single byte opcode
4355 setMachineCodes(mi++, (byte) 0x01);
4356 emitRegIndirectRegOperands(dstBase, srcReg);
4357 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4358 }
4359
4360 /**
4361 * Generate a register-offset--register ADD. That is,
4362 * <PRE>
4363 * [dstReg<<dstScale + dstDisp] += (quad) srcReg
4364 * </PRE>
4365 *
4366 * @param dstIndex the destination index register
4367 * @param dstScale the destination shift amount
4368 * @param dstDisp the destination displacement
4369 * @param srcReg the source register
4370 */
4371 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4372 public final void emitADD_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4373 int miStart = mi;
4374 // no group 1 to 4 prefix byte
4375 generateREXprefix(true, srcReg, dstIndex, null);
4376 // single byte opcode
4377 setMachineCodes(mi++, (byte) 0x01);
4378 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4379 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4380 }
4381
4382 /**
4383 * Generate a absolute--register ADD. That is,
4384 * <PRE>
4385 * [dstDisp] += (quad) srcReg
4386 * </PRE>
4387 *
4388 * @param dstDisp the destination address
4389 * @param srcReg the source register
4390 */
4391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4392 public final void emitADD_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
4393 int miStart = mi;
4394 // no group 1 to 4 prefix byte
4395 generateREXprefix(true, srcReg, null, null);
4396 // single byte opcode
4397 setMachineCodes(mi++, (byte) 0x01);
4398 emitAbsRegOperands(dstDisp, srcReg);
4399 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4400 }
4401
4402 /**
4403 * Generate a register-index--register ADD. That is,
4404 * <PRE>
4405 * [dstBase + dstIndex<<dstScale + dstDisp] += (quad) srcReg
4406 * </PRE>
4407 *
4408 * @param dstBase the base register
4409 * @param dstIndex the destination index register
4410 * @param dstScale the destination shift amount
4411 * @param dstDisp the destination displacement
4412 * @param srcReg the source register
4413 */
4414 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4415 public final void emitADD_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4416 int miStart = mi;
4417 // no group 1 to 4 prefix byte
4418 generateREXprefix(true, srcReg, dstIndex, dstBase);
4419 // single byte opcode
4420 setMachineCodes(mi++, (byte) 0x01);
4421 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4422 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4423 }
4424
4425 /**
4426 * Generate a register-displacement--register ADD. That is,
4427 * <PRE>
4428 * [dstBase + dstDisp] += (quad) srcReg
4429 * </PRE>
4430 *
4431 * @param dstBase the base register
4432 * @param dstDisp the destination displacement
4433 * @param srcReg the source register
4434 */
4435 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4436 public final void emitADD_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
4437 int miStart = mi;
4438 // no group 1 to 4 prefix byte
4439 generateREXprefix(true, srcReg, null, dstBase);
4440 // single byte opcode
4441 setMachineCodes(mi++, (byte) 0x01);
4442 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4443 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4444 }
4445
4446 /**
4447 * Generate a register--register ADD. That is,
4448 * <PRE>
4449 * dstReg += (quad) srcReg
4450 * </PRE>
4451 *
4452 * @param dstReg the destination register
4453 * @param srcReg the source register
4454 */
4455 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4456 public final void emitADD_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
4457 int miStart = mi;
4458 // no group 1 to 4 prefix byte
4459 generateREXprefix(true, srcReg, null, dstReg);
4460 // single byte opcode
4461 setMachineCodes(mi++, (byte) 0x01);
4462 emitRegRegOperands(dstReg, srcReg);
4463 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4464 }
4465
4466 /**
4467 * Generate a register--register-displacement ADD. That is,
4468 * <PRE>
4469 * dstReg += (quad) [srcReg + srcDisp]
4470 * </PRE>
4471 *
4472 * @param dstReg the destination register
4473 * @param srcBase the source register
4474 * @param srcDisp the source displacement
4475 */
4476 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4477 public final void emitADD_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
4478 int miStart = mi;
4479 // no group 1 to 4 prefix byte
4480 generateREXprefix(true, dstReg, null, srcBase);
4481 // single byte opcode
4482 setMachineCodes(mi++, (byte) 0x03);
4483 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4484 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4485 }
4486
4487 /**
4488 * Generate a register--register-offset ADD. That is,
4489 * <PRE>
4490 * dstReg += (quad) [srcIndex<<srcScale + srcDisp]
4491 * </PRE>
4492 *
4493 * @param dstReg the destination register
4494 * @param srcIndex the source index register
4495 * @param srcScale the source shift amount
4496 * @param srcDisp the source displacement
4497 */
4498 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4499 public final void emitADD_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4500 int miStart = mi;
4501 // no group 1 to 4 prefix byte
4502 generateREXprefix(true, dstReg, srcIndex, null);
4503 // single byte opcode
4504 setMachineCodes(mi++, (byte) 0x03);
4505 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4506 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4507 }
4508
4509 /**
4510 * Generate a register--register-offset ADD. That is,
4511 * <PRE>
4512 * dstReg += (quad) [srcDisp]
4513 * </PRE>
4514 *
4515 * @param dstReg the destination register
4516 * @param srcDisp the source displacement
4517 */
4518 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4519 public final void emitADD_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
4520 int miStart = mi;
4521 // no group 1 to 4 prefix byte
4522 generateREXprefix(true, dstReg, null, null);
4523 // single byte opcode
4524 setMachineCodes(mi++, (byte) 0x03);
4525 emitAbsRegOperands(srcDisp, dstReg);
4526 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4527 }
4528
4529 /**
4530 * Generate a register--register-offset ADD. That is,
4531 * <PRE>
4532 * dstReg += (quad) [srcBase + srcIndex<<srcScale + srcDisp]
4533 * </PRE>
4534 *
4535 * @param dstReg the destination register
4536 * @param srcBase the source base register
4537 * @param srcIndex the source index register
4538 * @param srcScale the source shift amount
4539 * @param srcDisp the source displacement
4540 */
4541 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4542 public final void emitADD_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4543 int miStart = mi;
4544 // no group 1 to 4 prefix byte
4545 generateREXprefix(true, dstReg, srcIndex, srcBase);
4546 // single byte opcode
4547 setMachineCodes(mi++, (byte) 0x03);
4548 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4549 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4550 }
4551
4552 /**
4553 * Generate a register--register(indirect) ADD. That is,
4554 * <PRE>
4555 * dstReg += (quad) [srcBase]
4556 * </PRE>
4557 *
4558 * @param dstReg the destination register
4559 * @param srcBase the source base register
4560 */
4561 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4562 public final void emitADD_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
4563 int miStart = mi;
4564 // no group 1 to 4 prefix byte
4565 generateREXprefix(true, dstReg, null, srcBase);
4566 // single byte opcode
4567 setMachineCodes(mi++, (byte) 0x03);
4568 emitRegIndirectRegOperands(srcBase, dstReg);
4569 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4570 }
4571
4572 /**
4573 * Generate a register(indirect)--register ADD. That is,
4574 * <PRE>
4575 * [dstBase] += (byte) srcReg
4576 * </PRE>
4577 *
4578 * @param dstBase the destination base
4579 * @param srcReg the source register
4580 */
4581 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4582 public final void emitADD_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
4583 int miStart = mi;
4584 // no group 1 to 4 prefix byte
4585 generateREXprefix(false, srcReg, null, dstBase);
4586 // single byte opcode
4587 setMachineCodes(mi++, (byte) 0x00);
4588 emitRegIndirectRegOperands(dstBase, srcReg);
4589 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4590 }
4591
4592 /**
4593 * Generate a register-offset--register ADD. That is,
4594 * <PRE>
4595 * [dstReg<<dstScale + dstDisp] += (byte) srcReg
4596 * </PRE>
4597 *
4598 * @param dstIndex the destination index register
4599 * @param dstScale the destination shift amount
4600 * @param dstDisp the destination displacement
4601 * @param srcReg the source register
4602 */
4603 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4604 public final void emitADD_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4605 int miStart = mi;
4606 // no group 1 to 4 prefix byte
4607 generateREXprefix(false, srcReg, dstIndex, null);
4608 // single byte opcode
4609 setMachineCodes(mi++, (byte) 0x00);
4610 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4611 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4612 }
4613
4614 /**
4615 * Generate a absolute--register ADD. That is,
4616 * <PRE>
4617 * [dstDisp] += (byte) srcReg
4618 * </PRE>
4619 *
4620 * @param dstDisp the destination address
4621 * @param srcReg the source register
4622 */
4623 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4624 public final void emitADD_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
4625 int miStart = mi;
4626 // no group 1 to 4 prefix byte
4627 generateREXprefix(false, srcReg, null, null);
4628 // single byte opcode
4629 setMachineCodes(mi++, (byte) 0x00);
4630 emitAbsRegOperands(dstDisp, srcReg);
4631 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4632 }
4633
4634 /**
4635 * Generate a register-index--register ADD. That is,
4636 * <PRE>
4637 * [dstBase + dstIndex<<dstScale + dstDisp] += (byte) srcReg
4638 * </PRE>
4639 *
4640 * @param dstBase the base register
4641 * @param dstIndex the destination index register
4642 * @param dstScale the destination shift amount
4643 * @param dstDisp the destination displacement
4644 * @param srcReg the source register
4645 */
4646 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4647 public final void emitADD_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4648 int miStart = mi;
4649 // no group 1 to 4 prefix byte
4650 generateREXprefix(false, srcReg, dstIndex, dstBase);
4651 // single byte opcode
4652 setMachineCodes(mi++, (byte) 0x00);
4653 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4654 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4655 }
4656
4657 /**
4658 * Generate a register-displacement--register ADD. That is,
4659 * <PRE>
4660 * [dstBase + dstDisp] += (byte) srcReg
4661 * </PRE>
4662 *
4663 * @param dstBase the base register
4664 * @param dstDisp the destination displacement
4665 * @param srcReg the source register
4666 */
4667 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4668 public final void emitADD_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
4669 int miStart = mi;
4670 // no group 1 to 4 prefix byte
4671 generateREXprefix(false, srcReg, null, dstBase);
4672 // single byte opcode
4673 setMachineCodes(mi++, (byte) 0x00);
4674 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4675 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4676 }
4677
4678 /**
4679 * Generate a register--register ADD. That is,
4680 * <PRE>
4681 * dstReg += (byte) srcReg
4682 * </PRE>
4683 *
4684 * @param dstReg the destination register
4685 * @param srcReg the source register
4686 */
4687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4688 public final void emitADD_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
4689 int miStart = mi;
4690 // no group 1 to 4 prefix byte
4691 generateREXprefix(false, srcReg, null, dstReg);
4692 // single byte opcode
4693 setMachineCodes(mi++, (byte) 0x00);
4694 emitRegRegOperands(dstReg, srcReg);
4695 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4696 }
4697
4698 /**
4699 * Generate a register--register-displacement ADD. That is,
4700 * <PRE>
4701 * dstReg += (byte) [srcReg + srcDisp]
4702 * </PRE>
4703 *
4704 * @param dstReg the destination register
4705 * @param srcBase the source register
4706 * @param srcDisp the source displacement
4707 */
4708 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4709 public final void emitADD_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
4710 int miStart = mi;
4711 // no group 1 to 4 prefix byte
4712 generateREXprefix(false, dstReg, null, srcBase);
4713 // single byte opcode
4714 setMachineCodes(mi++, (byte) 0x02);
4715 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4716 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4717 }
4718
4719 /**
4720 * Generate a register--register-offset ADD. That is,
4721 * <PRE>
4722 * dstReg += (byte) [srcIndex<<srcScale + srcDisp]
4723 * </PRE>
4724 *
4725 * @param dstReg the destination register
4726 * @param srcIndex the source index register
4727 * @param srcScale the source shift amount
4728 * @param srcDisp the source displacement
4729 */
4730 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4731 public final void emitADD_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4732 int miStart = mi;
4733 // no group 1 to 4 prefix byte
4734 generateREXprefix(false, dstReg, srcIndex, null);
4735 // single byte opcode
4736 setMachineCodes(mi++, (byte) 0x02);
4737 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4738 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4739 }
4740
4741 /**
4742 * Generate a register--register-offset ADD. That is,
4743 * <PRE>
4744 * dstReg += (byte) [srcDisp]
4745 * </PRE>
4746 *
4747 * @param dstReg the destination register
4748 * @param srcDisp the source displacement
4749 */
4750 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4751 public final void emitADD_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
4752 int miStart = mi;
4753 // no group 1 to 4 prefix byte
4754 generateREXprefix(false, dstReg, null, null);
4755 // single byte opcode
4756 setMachineCodes(mi++, (byte) 0x02);
4757 emitAbsRegOperands(srcDisp, dstReg);
4758 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4759 }
4760
4761 /**
4762 * Generate a register--register-offset ADD. That is,
4763 * <PRE>
4764 * dstReg += (byte) [srcBase + srcIndex<<srcScale + srcDisp]
4765 * </PRE>
4766 *
4767 * @param dstReg the destination register
4768 * @param srcBase the source base register
4769 * @param srcIndex the source index register
4770 * @param srcScale the source shift amount
4771 * @param srcDisp the source displacement
4772 */
4773 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4774 public final void emitADD_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4775 int miStart = mi;
4776 // no group 1 to 4 prefix byte
4777 generateREXprefix(false, dstReg, srcIndex, srcBase);
4778 // single byte opcode
4779 setMachineCodes(mi++, (byte) 0x02);
4780 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4781 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4782 }
4783
4784 /**
4785 * Generate a register--register(indirect) ADD. That is,
4786 * <PRE>
4787 * dstReg += (byte) [srcBase]
4788 * </PRE>
4789 *
4790 * @param dstReg the destination register
4791 * @param srcBase the source base register
4792 */
4793 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4794 public final void emitADD_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
4795 int miStart = mi;
4796 // no group 1 to 4 prefix byte
4797 generateREXprefix(false, dstReg, null, srcBase);
4798 // single byte opcode
4799 setMachineCodes(mi++, (byte) 0x02);
4800 emitRegIndirectRegOperands(srcBase, dstReg);
4801 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4802 }
4803
4804 /**
4805 * Generate a register--immediate ADD. That is,
4806 * <PRE>
4807 * dstReg += imm
4808 * </PRE>
4809 *
4810 * @param dstReg the destination register
4811 * @param imm immediate
4812 */
4813 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4814 public final void emitADD_Reg_Imm(GPR dstReg, int imm) {
4815 int miStart = mi;
4816 // no group 1 to 4 prefix byte
4817 generateREXprefix(false, null, null, dstReg);
4818 // single byte opcode
4819 if (fits(imm,8)) {
4820 setMachineCodes(mi++, (byte) 0x83);
4821 // "register 0x0" is really part of the opcode
4822 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
4823 emitImm8((byte)imm);
4824 } else if (dstReg == EAX) {
4825 setMachineCodes(mi++, (byte) 0x05);
4826 emitImm32(imm);
4827 } else {
4828 setMachineCodes(mi++, (byte) 0x81);
4829 // "register 0x0" is really part of the opcode
4830 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
4831 emitImm32(imm);
4832 }
4833 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
4834 }
4835
4836 /**
4837 * Generate a register-displacement--immediate ADD. That is,
4838 * <PRE>
4839 * [dstBase + dstDisp] += imm
4840 * </PRE>
4841 *
4842 * @param dstBase the destination register
4843 * @param dstDisp the destination displacement
4844 * @param imm immediate
4845 */
4846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4847 public final void emitADD_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
4848 int miStart = mi;
4849 // no group 1 to 4 prefix byte
4850 generateREXprefix(false, null, null, dstBase);
4851 // single byte opcode
4852 if (fits(imm,8)) {
4853 setMachineCodes(mi++, (byte) 0x83);
4854 // "register 0x0" is really part of the opcode
4855 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
4856 emitImm8((byte)imm);
4857 } else {
4858 setMachineCodes(mi++, (byte) 0x81);
4859 // "register 0x0" is really part of the opcode
4860 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
4861 emitImm32(imm);
4862 }
4863 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
4864 }
4865
4866 /**
4867 * Generate a register-offset--immediate ADD. That is,
4868 * <PRE>
4869 * [dstIndex<<dstScale + dstDisp] += imm
4870 * </PRE>
4871 *
4872 * @param dstIndex the destination index register
4873 * @param dstScale the destination shift amount
4874 * @param dstDisp the destination displacement
4875 * @param imm immediate
4876 */
4877 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4878 public final void emitADD_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
4879 int miStart = mi;
4880 // no group 1 to 4 prefix byte
4881 generateREXprefix(false, null, dstIndex, null);
4882 // single byte opcode
4883 if (fits(imm,8)) {
4884 setMachineCodes(mi++, (byte) 0x83);
4885 // "register 0x0" is really part of the opcode
4886 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4887 emitImm8((byte)imm);
4888 } else {
4889 setMachineCodes(mi++, (byte) 0x81);
4890 // "register 0x0" is really part of the opcode
4891 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4892 emitImm32(imm);
4893 }
4894 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
4895 }
4896
4897 /**
4898 * Generate a absolute--immediate ADD. That is,
4899 * <PRE>
4900 * [dstDisp] += imm
4901 * </PRE>
4902 *
4903 * @param dstDisp the destination displacement
4904 * @param imm immediate
4905 */
4906 public final void emitADD_Abs_Imm(Address dstDisp, int imm) {
4907 int miStart = mi;
4908 // no group 1 to 4 prefix byte
4909 generateREXprefix(false, null, null, null);
4910 // single byte opcode
4911 if (fits(imm,8)) {
4912 setMachineCodes(mi++, (byte) 0x83);
4913 // "register 0x0" is really part of the opcode
4914 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
4915 emitImm8((byte)imm);
4916 } else {
4917 setMachineCodes(mi++, (byte) 0x81);
4918 // "register 0x0" is really part of the opcode
4919 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
4920 emitImm32(imm);
4921 }
4922 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
4923 }
4924
4925 /**
4926 * Generate a register-index--immediate ADD. That is,
4927 * <PRE>
4928 * [dstBase + dstIndex<<dstScale + dstDisp] += imm
4929 * </PRE>
4930 *
4931 * @param dstBase the destination base register
4932 * @param dstIndex the destination index register
4933 * @param dstScale the destination shift amount
4934 * @param dstDisp the destination displacement
4935 * @param imm immediate
4936 */
4937 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4938 public final void emitADD_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
4939 int miStart = mi;
4940 // no group 1 to 4 prefix byte
4941 generateREXprefix(false, null, dstIndex, dstBase);
4942 // single byte opcode
4943 if (fits(imm,8)) {
4944 setMachineCodes(mi++, (byte) 0x83);
4945 // "register 0x0" is really part of the opcode
4946 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4947 emitImm8((byte)imm);
4948 } else {
4949 setMachineCodes(mi++, (byte) 0x81);
4950 // "register 0x0" is really part of the opcode
4951 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4952 emitImm32(imm);
4953 }
4954 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
4955 }
4956
4957 /**
4958 * Generate a register(indirect)--immediate ADD. That is,
4959 * <PRE>
4960 * [dstBase] += imm
4961 * </PRE>
4962 *
4963 * @param dstBase the destination base register
4964 * @param imm immediate
4965 */
4966 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4967 public final void emitADD_RegInd_Imm(GPR dstBase, int imm) {
4968 int miStart = mi;
4969 // no group 1 to 4 prefix byte
4970 generateREXprefix(false, null, null, dstBase);
4971 // single byte opcode
4972 if (fits(imm,8)) {
4973 setMachineCodes(mi++, (byte) 0x83);
4974 // "register 0x0" is really part of the opcode
4975 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
4976 emitImm8((byte)imm);
4977 } else {
4978 setMachineCodes(mi++, (byte) 0x81);
4979 // "register 0x0" is really part of the opcode
4980 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
4981 emitImm32(imm);
4982 }
4983 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
4984 }
4985
4986 /**
4987 * Generate a register--immediate ADD. That is,
4988 * <PRE>
4989 * dstReg += (word) imm
4990 * </PRE>
4991 *
4992 * @param dstReg the destination register
4993 * @param imm immediate
4994 */
4995 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4996 public final void emitADD_Reg_Imm_Word(GPR dstReg, int imm) {
4997 int miStart = mi;
4998 setMachineCodes(mi++, (byte) 0x66);
4999 generateREXprefix(false, null, null, dstReg);
5000 // single byte opcode
5001 if (fits(imm,8)) {
5002 setMachineCodes(mi++, (byte) 0x83);
5003 // "register 0x0" is really part of the opcode
5004 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5005 emitImm8((byte)imm);
5006 } else if (dstReg == EAX) {
5007 setMachineCodes(mi++, (byte) 0x05);
5008 emitImm16(imm);
5009 } else {
5010 setMachineCodes(mi++, (byte) 0x81);
5011 // "register 0x0" is really part of the opcode
5012 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5013 emitImm16(imm);
5014 }
5015 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5016 }
5017
5018 /**
5019 * Generate a register-displacement--immediate ADD. That is,
5020 * <PRE>
5021 * [dstBase + dstDisp] += (word) imm
5022 * </PRE>
5023 *
5024 * @param dstBase the destination register
5025 * @param dstDisp the destination displacement
5026 * @param imm immediate
5027 */
5028 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5029 public final void emitADD_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
5030 int miStart = mi;
5031 setMachineCodes(mi++, (byte) 0x66);
5032 generateREXprefix(false, null, null, dstBase);
5033 // single byte opcode
5034 if (fits(imm,8)) {
5035 setMachineCodes(mi++, (byte) 0x83);
5036 // "register 0x0" is really part of the opcode
5037 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5038 emitImm8((byte)imm);
5039 } else {
5040 setMachineCodes(mi++, (byte) 0x81);
5041 // "register 0x0" is really part of the opcode
5042 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5043 emitImm16(imm);
5044 }
5045 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5046 }
5047
5048 /**
5049 * Generate a register-offset--immediate ADD. That is,
5050 * <PRE>
5051 * [dstIndex<<dstScale + dstDisp] += (word) imm
5052 * </PRE>
5053 *
5054 * @param dstIndex the destination index register
5055 * @param dstScale the destination shift amount
5056 * @param dstDisp the destination displacement
5057 * @param imm immediate
5058 */
5059 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5060 public final void emitADD_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5061 int miStart = mi;
5062 setMachineCodes(mi++, (byte) 0x66);
5063 generateREXprefix(false, null, dstIndex, null);
5064 // single byte opcode
5065 if (fits(imm,8)) {
5066 setMachineCodes(mi++, (byte) 0x83);
5067 // "register 0x0" is really part of the opcode
5068 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5069 emitImm8((byte)imm);
5070 } else {
5071 setMachineCodes(mi++, (byte) 0x81);
5072 // "register 0x0" is really part of the opcode
5073 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5074 emitImm16(imm);
5075 }
5076 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5077 }
5078
5079 /**
5080 * Generate a absolute--immediate ADD. That is,
5081 * <PRE>
5082 * [dstDisp] += (word) imm
5083 * </PRE>
5084 *
5085 * @param dstDisp the destination displacement
5086 * @param imm immediate
5087 */
5088 public final void emitADD_Abs_Imm_Word(Address dstDisp, int imm) {
5089 int miStart = mi;
5090 setMachineCodes(mi++, (byte) 0x66);
5091 generateREXprefix(false, null, null, null);
5092 // single byte opcode
5093 if (fits(imm,8)) {
5094 setMachineCodes(mi++, (byte) 0x83);
5095 // "register 0x0" is really part of the opcode
5096 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5097 emitImm8((byte)imm);
5098 } else {
5099 setMachineCodes(mi++, (byte) 0x81);
5100 // "register 0x0" is really part of the opcode
5101 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5102 emitImm16(imm);
5103 }
5104 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5105 }
5106
5107 /**
5108 * Generate a register-index--immediate ADD. That is,
5109 * <PRE>
5110 * [dstBase + dstIndex<<dstScale + dstDisp] += (word) imm
5111 * </PRE>
5112 *
5113 * @param dstBase the destination base register
5114 * @param dstIndex the destination index register
5115 * @param dstScale the destination shift amount
5116 * @param dstDisp the destination displacement
5117 * @param imm immediate
5118 */
5119 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5120 public final void emitADD_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5121 int miStart = mi;
5122 setMachineCodes(mi++, (byte) 0x66);
5123 generateREXprefix(false, null, dstIndex, dstBase);
5124 // single byte opcode
5125 if (fits(imm,8)) {
5126 setMachineCodes(mi++, (byte) 0x83);
5127 // "register 0x0" is really part of the opcode
5128 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5129 emitImm8((byte)imm);
5130 } else {
5131 setMachineCodes(mi++, (byte) 0x81);
5132 // "register 0x0" is really part of the opcode
5133 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5134 emitImm16(imm);
5135 }
5136 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5137 }
5138
5139 /**
5140 * Generate a register(indirect)--immediate ADD. That is,
5141 * <PRE>
5142 * [dstBase] += (word) imm
5143 * </PRE>
5144 *
5145 * @param dstBase the destination base register
5146 * @param imm immediate
5147 */
5148 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5149 public final void emitADD_RegInd_Imm_Word(GPR dstBase, int imm) {
5150 int miStart = mi;
5151 setMachineCodes(mi++, (byte) 0x66);
5152 generateREXprefix(false, null, null, dstBase);
5153 // single byte opcode
5154 if (fits(imm,8)) {
5155 setMachineCodes(mi++, (byte) 0x83);
5156 // "register 0x0" is really part of the opcode
5157 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5158 emitImm8((byte)imm);
5159 } else {
5160 setMachineCodes(mi++, (byte) 0x81);
5161 // "register 0x0" is really part of the opcode
5162 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5163 emitImm16(imm);
5164 }
5165 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5166 }
5167
5168 /**
5169 * Generate a register--immediate ADD. That is,
5170 * <PRE>
5171 * dstReg += (quad) imm
5172 * </PRE>
5173 *
5174 * @param dstReg the destination register
5175 * @param imm immediate
5176 */
5177 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5178 public final void emitADD_Reg_Imm_Quad(GPR dstReg, int imm) {
5179 int miStart = mi;
5180 // no group 1 to 4 prefix byte
5181 generateREXprefix(true, null, null, dstReg);
5182 // single byte opcode
5183 if (fits(imm,8)) {
5184 setMachineCodes(mi++, (byte) 0x83);
5185 // "register 0x0" is really part of the opcode
5186 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5187 emitImm8((byte)imm);
5188 } else if (dstReg == EAX) {
5189 setMachineCodes(mi++, (byte) 0x05);
5190 emitImm32(imm);
5191 } else {
5192 setMachineCodes(mi++, (byte) 0x81);
5193 // "register 0x0" is really part of the opcode
5194 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5195 emitImm32(imm);
5196 }
5197 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5198 }
5199
5200 /**
5201 * Generate a register-displacement--immediate ADD. That is,
5202 * <PRE>
5203 * [dstBase + dstDisp] += (quad) imm
5204 * </PRE>
5205 *
5206 * @param dstBase the destination register
5207 * @param dstDisp the destination displacement
5208 * @param imm immediate
5209 */
5210 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5211 public final void emitADD_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
5212 int miStart = mi;
5213 // no group 1 to 4 prefix byte
5214 generateREXprefix(true, null, null, dstBase);
5215 // single byte opcode
5216 if (fits(imm,8)) {
5217 setMachineCodes(mi++, (byte) 0x83);
5218 // "register 0x0" is really part of the opcode
5219 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5220 emitImm8((byte)imm);
5221 } else {
5222 setMachineCodes(mi++, (byte) 0x81);
5223 // "register 0x0" is really part of the opcode
5224 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5225 emitImm32(imm);
5226 }
5227 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5228 }
5229
5230 /**
5231 * Generate a register-offset--immediate ADD. That is,
5232 * <PRE>
5233 * [dstIndex<<dstScale + dstDisp] += (quad) imm
5234 * </PRE>
5235 *
5236 * @param dstIndex the destination index register
5237 * @param dstScale the destination shift amount
5238 * @param dstDisp the destination displacement
5239 * @param imm immediate
5240 */
5241 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5242 public final void emitADD_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5243 int miStart = mi;
5244 // no group 1 to 4 prefix byte
5245 generateREXprefix(true, null, dstIndex, null);
5246 // single byte opcode
5247 if (fits(imm,8)) {
5248 setMachineCodes(mi++, (byte) 0x83);
5249 // "register 0x0" is really part of the opcode
5250 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5251 emitImm8((byte)imm);
5252 } else {
5253 setMachineCodes(mi++, (byte) 0x81);
5254 // "register 0x0" is really part of the opcode
5255 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5256 emitImm32(imm);
5257 }
5258 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5259 }
5260
5261 /**
5262 * Generate a absolute--immediate ADD. That is,
5263 * <PRE>
5264 * [dstDisp] += (quad) imm
5265 * </PRE>
5266 *
5267 * @param dstDisp the destination displacement
5268 * @param imm immediate
5269 */
5270 public final void emitADD_Abs_Imm_Quad(Address dstDisp, int imm) {
5271 int miStart = mi;
5272 // no group 1 to 4 prefix byte
5273 generateREXprefix(true, null, null, null);
5274 // single byte opcode
5275 if (fits(imm,8)) {
5276 setMachineCodes(mi++, (byte) 0x83);
5277 // "register 0x0" is really part of the opcode
5278 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5279 emitImm8((byte)imm);
5280 } else {
5281 setMachineCodes(mi++, (byte) 0x81);
5282 // "register 0x0" is really part of the opcode
5283 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5284 emitImm32(imm);
5285 }
5286 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5287 }
5288
5289 /**
5290 * Generate a register-index--immediate ADD. That is,
5291 * <PRE>
5292 * [dstBase + dstIndex<<dstScale + dstDisp] += (quad) imm
5293 * </PRE>
5294 *
5295 * @param dstBase the destination base register
5296 * @param dstIndex the destination index register
5297 * @param dstScale the destination shift amount
5298 * @param dstDisp the destination displacement
5299 * @param imm immediate
5300 */
5301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5302 public final void emitADD_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5303 int miStart = mi;
5304 // no group 1 to 4 prefix byte
5305 generateREXprefix(true, null, dstIndex, dstBase);
5306 // single byte opcode
5307 if (fits(imm,8)) {
5308 setMachineCodes(mi++, (byte) 0x83);
5309 // "register 0x0" is really part of the opcode
5310 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5311 emitImm8((byte)imm);
5312 } else {
5313 setMachineCodes(mi++, (byte) 0x81);
5314 // "register 0x0" is really part of the opcode
5315 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5316 emitImm32(imm);
5317 }
5318 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5319 }
5320
5321 /**
5322 * Generate a register(indirect)--immediate ADD. That is,
5323 * <PRE>
5324 * [dstBase] += (quad) imm
5325 * </PRE>
5326 *
5327 * @param dstBase the destination base register
5328 * @param imm immediate
5329 */
5330 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5331 public final void emitADD_RegInd_Imm_Quad(GPR dstBase, int imm) {
5332 int miStart = mi;
5333 // no group 1 to 4 prefix byte
5334 generateREXprefix(true, null, null, dstBase);
5335 // single byte opcode
5336 if (fits(imm,8)) {
5337 setMachineCodes(mi++, (byte) 0x83);
5338 // "register 0x0" is really part of the opcode
5339 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5340 emitImm8((byte)imm);
5341 } else {
5342 setMachineCodes(mi++, (byte) 0x81);
5343 // "register 0x0" is really part of the opcode
5344 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5345 emitImm32(imm);
5346 }
5347 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5348 }
5349
5350 /**
5351 * Generate a register--immediate ADD. That is,
5352 * <PRE>
5353 * dstReg += (byte) imm
5354 * </PRE>
5355 *
5356 * @param dstReg the destination register
5357 * @param imm immediate
5358 */
5359 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5360 public final void emitADD_Reg_Imm_Byte(GPR dstReg, int imm) {
5361 int miStart = mi;
5362 if (dstReg == EAX) {
5363 setMachineCodes(mi++, (byte) 0x04);
5364 emitImm8(imm);
5365 } else {
5366 generateREXprefix(false, null, null, dstReg);
5367 setMachineCodes(mi++, (byte) 0x80);
5368 // "register 0x0" is really part of the opcode
5369 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5370 emitImm8(imm);
5371 }
5372 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5373 }
5374
5375 /**
5376 * Generate a register-displacement--immediate ADD. That is,
5377 * <PRE>
5378 * [dstBase + dstDisp] += (byte) imm
5379 * </PRE>
5380 *
5381 * @param dstBase the destination register
5382 * @param dstDisp the destination displacement
5383 * @param imm immediate
5384 */
5385 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5386 public final void emitADD_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
5387 int miStart = mi;
5388 generateREXprefix(false, null, null, dstBase);
5389 setMachineCodes(mi++, (byte) 0x80);
5390 // "register 0x0" is really part of the opcode
5391 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5392 emitImm8(imm);
5393 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5394 }
5395
5396 /**
5397 * Generate a register-index--immediate ADD. That is,
5398 * <PRE>
5399 * [dstBase + dstIndex<<scale + dstDisp] += (byte) imm
5400 * </PRE>
5401 *
5402 * @param dstBase the destination base register
5403 * @param dstIndex the destination index register
5404 * @param dstScale the destination shift amount
5405 * @param dstDisp the destination displacement
5406 * @param imm immediate
5407 */
5408 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5409 public final void emitADD_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5410 int miStart = mi;
5411 generateREXprefix(false, null, dstIndex, dstBase);
5412 setMachineCodes(mi++, (byte) 0x80);
5413 // "register 0x0" is really part of the opcode
5414 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5415 emitImm8(imm);
5416 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5417 }
5418
5419 /**
5420 * Generate a register-offset--immediate ADD. That is,
5421 * <PRE>
5422 * [dstIndex<<dstScale + dstDisp] += (byte) imm
5423 * </PRE>
5424 *
5425 * @param dstIndex the destination index register
5426 * @param dstScale the destination shift amount
5427 * @param dstDisp the destination displacement
5428 * @param imm immediate
5429 */
5430 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5431 public final void emitADD_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5432 int miStart = mi;
5433 generateREXprefix(false, null, dstIndex, null);
5434 setMachineCodes(mi++, (byte) 0x80);
5435 // "register 0x0" is really part of the opcode
5436 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5437 emitImm8(imm);
5438 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5439 }
5440
5441 /**
5442 * Generate a absolute--immediate ADD. That is,
5443 * <PRE>
5444 * [dstDisp] += (byte) imm
5445 * </PRE>
5446 *
5447 * @param dstDisp the destination displacement
5448 * @param imm immediate
5449 */
5450 public final void emitADD_Abs_Imm_Byte(Address dstDisp, int imm) {
5451 int miStart = mi;
5452 generateREXprefix(false, null, null, null);
5453 setMachineCodes(mi++, (byte) 0x80);
5454 // "register 0x0" is really part of the opcode
5455 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5456 emitImm8(imm);
5457 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5458 }
5459
5460 /**
5461 * Generate a register(indirect)--immediate ADD. That is,
5462 * <PRE>
5463 * [dstBase] += (byte) imm
5464 * </PRE>
5465 *
5466 * @param dstBase the destination base register
5467 * @param imm immediate
5468 */
5469 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5470 public final void emitADD_RegInd_Imm_Byte(GPR dstBase, int imm) {
5471 int miStart = mi;
5472 generateREXprefix(false, null, null, dstBase);
5473 setMachineCodes(mi++, (byte) 0x80);
5474 // "register 0x0" is really part of the opcode
5475 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5476 emitImm8(imm);
5477 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5478 }
5479
5480 /**
5481 * Generate a register(indirect)--register AND. That is,
5482 * <PRE>
5483 * [dstBase] &= srcReg
5484 * </PRE>
5485 *
5486 * @param dstBase the destination base
5487 * @param srcReg the source register
5488 */
5489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5490 public final void emitAND_RegInd_Reg(GPR dstBase, GPR srcReg) {
5491 int miStart = mi;
5492 // no group 1 to 4 prefix byte
5493 generateREXprefix(false, srcReg, null, dstBase);
5494 // single byte opcode
5495 setMachineCodes(mi++, (byte) 0x21);
5496 emitRegIndirectRegOperands(dstBase, srcReg);
5497 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5498 }
5499
5500 /**
5501 * Generate a register-offset--register AND. That is,
5502 * <PRE>
5503 * [dstReg<<dstScale + dstDisp] &= srcReg
5504 * </PRE>
5505 *
5506 * @param dstIndex the destination index register
5507 * @param dstScale the destination shift amount
5508 * @param dstDisp the destination displacement
5509 * @param srcReg the source register
5510 */
5511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5512 public final void emitAND_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5513 int miStart = mi;
5514 // no group 1 to 4 prefix byte
5515 generateREXprefix(false, srcReg, dstIndex, null);
5516 // single byte opcode
5517 setMachineCodes(mi++, (byte) 0x21);
5518 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5519 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5520 }
5521
5522 /**
5523 * Generate a absolute--register AND. That is,
5524 * <PRE>
5525 * [dstDisp] &= srcReg
5526 * </PRE>
5527 *
5528 * @param dstDisp the destination address
5529 * @param srcReg the source register
5530 */
5531 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
5532 public final void emitAND_Abs_Reg(Address dstDisp, GPR srcReg) {
5533 int miStart = mi;
5534 // no group 1 to 4 prefix byte
5535 generateREXprefix(false, srcReg, null, null);
5536 // single byte opcode
5537 setMachineCodes(mi++, (byte) 0x21);
5538 emitAbsRegOperands(dstDisp, srcReg);
5539 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
5540 }
5541
5542 /**
5543 * Generate a register-index--register AND. That is,
5544 * <PRE>
5545 * [dstBase + dstIndex<<dstScale + dstDisp] &= srcReg
5546 * </PRE>
5547 *
5548 * @param dstBase the base register
5549 * @param dstIndex the destination index register
5550 * @param dstScale the destination shift amount
5551 * @param dstDisp the destination displacement
5552 * @param srcReg the source register
5553 */
5554 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
5555 public final void emitAND_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5556 int miStart = mi;
5557 // no group 1 to 4 prefix byte
5558 generateREXprefix(false, srcReg, dstIndex, dstBase);
5559 // single byte opcode
5560 setMachineCodes(mi++, (byte) 0x21);
5561 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
5562 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
5563 }
5564
5565 /**
5566 * Generate a register-displacement--register AND. That is,
5567 * <PRE>
5568 * [dstBase + dstDisp] &= srcReg
5569 * </PRE>
5570 *
5571 * @param dstBase the base register
5572 * @param dstDisp the destination displacement
5573 * @param srcReg the source register
5574 */
5575 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
5576 public final void emitAND_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
5577 int miStart = mi;
5578 // no group 1 to 4 prefix byte
5579 generateREXprefix(false, srcReg, null, dstBase);
5580 // single byte opcode
5581 setMachineCodes(mi++, (byte) 0x21);
5582 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
5583 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
5584 }
5585
5586 /**
5587 * Generate a register--register AND. That is,
5588 * <PRE>
5589 * dstReg &= srcReg
5590 * </PRE>
5591 *
5592 * @param dstReg the destination register
5593 * @param srcReg the source register
5594 */
5595 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5596 public final void emitAND_Reg_Reg(GPR dstReg, GPR srcReg) {
5597 int miStart = mi;
5598 // no group 1 to 4 prefix byte
5599 generateREXprefix(false, srcReg, null, dstReg);
5600 // single byte opcode
5601 setMachineCodes(mi++, (byte) 0x21);
5602 emitRegRegOperands(dstReg, srcReg);
5603 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
5604 }
5605
5606 /**
5607 * Generate a register--register-displacement AND. That is,
5608 * <PRE>
5609 * dstReg &= [srcReg + srcDisp]
5610 * </PRE>
5611 *
5612 * @param dstReg the destination register
5613 * @param srcBase the source register
5614 * @param srcDisp the source displacement
5615 */
5616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5617 public final void emitAND_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
5618 int miStart = mi;
5619 // no group 1 to 4 prefix byte
5620 generateREXprefix(false, dstReg, null, srcBase);
5621 // single byte opcode
5622 setMachineCodes(mi++, (byte) 0x23);
5623 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
5624 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
5625 }
5626
5627 /**
5628 * Generate a register--register-offset AND. That is,
5629 * <PRE>
5630 * dstReg &= [srcIndex<<srcScale + srcDisp]
5631 * </PRE>
5632 *
5633 * @param dstReg the destination register
5634 * @param srcIndex the source index register
5635 * @param srcScale the source shift amount
5636 * @param srcDisp the source displacement
5637 */
5638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5639 public final void emitAND_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
5640 int miStart = mi;
5641 // no group 1 to 4 prefix byte
5642 generateREXprefix(false, dstReg, srcIndex, null);
5643 // single byte opcode
5644 setMachineCodes(mi++, (byte) 0x23);
5645 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
5646 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
5647 }
5648
5649 /**
5650 * Generate a register--register-offset AND. That is,
5651 * <PRE>
5652 * dstReg &= [srcDisp]
5653 * </PRE>
5654 *
5655 * @param dstReg the destination register
5656 * @param srcDisp the source displacement
5657 */
5658 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5659 public final void emitAND_Reg_Abs(GPR dstReg, Address srcDisp) {
5660 int miStart = mi;
5661 // no group 1 to 4 prefix byte
5662 generateREXprefix(false, dstReg, null, null);
5663 // single byte opcode
5664 setMachineCodes(mi++, (byte) 0x23);
5665 emitAbsRegOperands(srcDisp, dstReg);
5666 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
5667 }
5668
5669 /**
5670 * Generate a register--register-offset AND. That is,
5671 * <PRE>
5672 * dstReg &= [srcBase + srcIndex<<srcScale + srcDisp]
5673 * </PRE>
5674 *
5675 * @param dstReg the destination register
5676 * @param srcBase the source base register
5677 * @param srcIndex the source index register
5678 * @param srcScale the source shift amount
5679 * @param srcDisp the source displacement
5680 */
5681 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
5682 public final void emitAND_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
5683 int miStart = mi;
5684 // no group 1 to 4 prefix byte
5685 generateREXprefix(false, dstReg, srcIndex, srcBase);
5686 // single byte opcode
5687 setMachineCodes(mi++, (byte) 0x23);
5688 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
5689 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
5690 }
5691
5692 /**
5693 * Generate a register--register(indirect) AND. That is,
5694 * <PRE>
5695 * dstReg &= [srcBase]
5696 * </PRE>
5697 *
5698 * @param dstReg the destination register
5699 * @param srcBase the source base register
5700 */
5701 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5702 public final void emitAND_Reg_RegInd(GPR dstReg, GPR srcBase) {
5703 int miStart = mi;
5704 // no group 1 to 4 prefix byte
5705 generateREXprefix(false, dstReg, null, srcBase);
5706 // single byte opcode
5707 setMachineCodes(mi++, (byte) 0x23);
5708 emitRegIndirectRegOperands(srcBase, dstReg);
5709 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
5710 }
5711
5712 /**
5713 * Generate a register(indirect)--register AND. That is,
5714 * <PRE>
5715 * [dstBase] &= (word) srcReg
5716 * </PRE>
5717 *
5718 * @param dstBase the destination base
5719 * @param srcReg the source register
5720 */
5721 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5722 public final void emitAND_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
5723 int miStart = mi;
5724 setMachineCodes(mi++, (byte) 0x66);
5725 generateREXprefix(false, srcReg, null, dstBase);
5726 // single byte opcode
5727 setMachineCodes(mi++, (byte) 0x21);
5728 emitRegIndirectRegOperands(dstBase, srcReg);
5729 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5730 }
5731
5732 /**
5733 * Generate a register-offset--register AND. That is,
5734 * <PRE>
5735 * [dstReg<<dstScale + dstDisp] &= (word) srcReg
5736 * </PRE>
5737 *
5738 * @param dstIndex the destination index register
5739 * @param dstScale the destination shift amount
5740 * @param dstDisp the destination displacement
5741 * @param srcReg the source register
5742 */
5743 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5744 public final void emitAND_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5745 int miStart = mi;
5746 setMachineCodes(mi++, (byte) 0x66);
5747 generateREXprefix(false, srcReg, dstIndex, null);
5748 // single byte opcode
5749 setMachineCodes(mi++, (byte) 0x21);
5750 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5751 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5752 }
5753
5754 /**
5755 * Generate a absolute--register AND. That is,
5756 * <PRE>
5757 * [dstDisp] &= (word) srcReg
5758 * </PRE>
5759 *
5760 * @param dstDisp the destination address
5761 * @param srcReg the source register
5762 */
5763 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
5764 public final void emitAND_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
5765 int miStart = mi;
5766 setMachineCodes(mi++, (byte) 0x66);
5767 generateREXprefix(false, srcReg, null, null);
5768 // single byte opcode
5769 setMachineCodes(mi++, (byte) 0x21);
5770 emitAbsRegOperands(dstDisp, srcReg);
5771 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
5772 }
5773
5774 /**
5775 * Generate a register-index--register AND. That is,
5776 * <PRE>
5777 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) srcReg
5778 * </PRE>
5779 *
5780 * @param dstBase the base register
5781 * @param dstIndex the destination index register
5782 * @param dstScale the destination shift amount
5783 * @param dstDisp the destination displacement
5784 * @param srcReg the source register
5785 */
5786 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
5787 public final void emitAND_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5788 int miStart = mi;
5789 setMachineCodes(mi++, (byte) 0x66);
5790 generateREXprefix(false, srcReg, dstIndex, dstBase);
5791 // single byte opcode
5792 setMachineCodes(mi++, (byte) 0x21);
5793 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
5794 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
5795 }
5796
5797 /**
5798 * Generate a register-displacement--register AND. That is,
5799 * <PRE>
5800 * [dstBase + dstDisp] &= (word) srcReg
5801 * </PRE>
5802 *
5803 * @param dstBase the base register
5804 * @param dstDisp the destination displacement
5805 * @param srcReg the source register
5806 */
5807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
5808 public final void emitAND_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
5809 int miStart = mi;
5810 setMachineCodes(mi++, (byte) 0x66);
5811 generateREXprefix(false, srcReg, null, dstBase);
5812 // single byte opcode
5813 setMachineCodes(mi++, (byte) 0x21);
5814 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
5815 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
5816 }
5817
5818 /**
5819 * Generate a register--register AND. That is,
5820 * <PRE>
5821 * dstReg &= (word) srcReg
5822 * </PRE>
5823 *
5824 * @param dstReg the destination register
5825 * @param srcReg the source register
5826 */
5827 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5828 public final void emitAND_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
5829 int miStart = mi;
5830 setMachineCodes(mi++, (byte) 0x66);
5831 generateREXprefix(false, srcReg, null, dstReg);
5832 // single byte opcode
5833 setMachineCodes(mi++, (byte) 0x21);
5834 emitRegRegOperands(dstReg, srcReg);
5835 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
5836 }
5837
5838 /**
5839 * Generate a register--register-displacement AND. That is,
5840 * <PRE>
5841 * dstReg &= (word) [srcReg + srcDisp]
5842 * </PRE>
5843 *
5844 * @param dstReg the destination register
5845 * @param srcBase the source register
5846 * @param srcDisp the source displacement
5847 */
5848 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5849 public final void emitAND_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
5850 int miStart = mi;
5851 setMachineCodes(mi++, (byte) 0x66);
5852 generateREXprefix(false, dstReg, null, srcBase);
5853 // single byte opcode
5854 setMachineCodes(mi++, (byte) 0x23);
5855 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
5856 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
5857 }
5858
5859 /**
5860 * Generate a register--register-offset AND. That is,
5861 * <PRE>
5862 * dstReg &= (word) [srcIndex<<srcScale + srcDisp]
5863 * </PRE>
5864 *
5865 * @param dstReg the destination register
5866 * @param srcIndex the source index register
5867 * @param srcScale the source shift amount
5868 * @param srcDisp the source displacement
5869 */
5870 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5871 public final void emitAND_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
5872 int miStart = mi;
5873 setMachineCodes(mi++, (byte) 0x66);
5874 generateREXprefix(false, dstReg, srcIndex, null);
5875 // single byte opcode
5876 setMachineCodes(mi++, (byte) 0x23);
5877 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
5878 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
5879 }
5880
5881 /**
5882 * Generate a register--register-offset AND. That is,
5883 * <PRE>
5884 * dstReg &= (word) [srcDisp]
5885 * </PRE>
5886 *
5887 * @param dstReg the destination register
5888 * @param srcDisp the source displacement
5889 */
5890 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5891 public final void emitAND_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
5892 int miStart = mi;
5893 setMachineCodes(mi++, (byte) 0x66);
5894 generateREXprefix(false, dstReg, null, null);
5895 // single byte opcode
5896 setMachineCodes(mi++, (byte) 0x23);
5897 emitAbsRegOperands(srcDisp, dstReg);
5898 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
5899 }
5900
5901 /**
5902 * Generate a register--register-offset AND. That is,
5903 * <PRE>
5904 * dstReg &= (word) [srcBase + srcIndex<<srcScale + srcDisp]
5905 * </PRE>
5906 *
5907 * @param dstReg the destination register
5908 * @param srcBase the source base register
5909 * @param srcIndex the source index register
5910 * @param srcScale the source shift amount
5911 * @param srcDisp the source displacement
5912 */
5913 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
5914 public final void emitAND_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
5915 int miStart = mi;
5916 setMachineCodes(mi++, (byte) 0x66);
5917 generateREXprefix(false, dstReg, srcIndex, srcBase);
5918 // single byte opcode
5919 setMachineCodes(mi++, (byte) 0x23);
5920 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
5921 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
5922 }
5923
5924 /**
5925 * Generate a register--register(indirect) AND. That is,
5926 * <PRE>
5927 * dstReg &= (word) [srcBase]
5928 * </PRE>
5929 *
5930 * @param dstReg the destination register
5931 * @param srcBase the source base register
5932 */
5933 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5934 public final void emitAND_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
5935 int miStart = mi;
5936 setMachineCodes(mi++, (byte) 0x66);
5937 generateREXprefix(false, dstReg, null, srcBase);
5938 // single byte opcode
5939 setMachineCodes(mi++, (byte) 0x23);
5940 emitRegIndirectRegOperands(srcBase, dstReg);
5941 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
5942 }
5943
5944 /**
5945 * Generate a register(indirect)--register AND. That is,
5946 * <PRE>
5947 * [dstBase] &= (quad) srcReg
5948 * </PRE>
5949 *
5950 * @param dstBase the destination base
5951 * @param srcReg the source register
5952 */
5953 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5954 public final void emitAND_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
5955 int miStart = mi;
5956 // no group 1 to 4 prefix byte
5957 generateREXprefix(true, srcReg, null, dstBase);
5958 // single byte opcode
5959 setMachineCodes(mi++, (byte) 0x21);
5960 emitRegIndirectRegOperands(dstBase, srcReg);
5961 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5962 }
5963
5964 /**
5965 * Generate a register-offset--register AND. That is,
5966 * <PRE>
5967 * [dstReg<<dstScale + dstDisp] &= (quad) srcReg
5968 * </PRE>
5969 *
5970 * @param dstIndex the destination index register
5971 * @param dstScale the destination shift amount
5972 * @param dstDisp the destination displacement
5973 * @param srcReg the source register
5974 */
5975 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5976 public final void emitAND_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5977 int miStart = mi;
5978 // no group 1 to 4 prefix byte
5979 generateREXprefix(true, srcReg, dstIndex, null);
5980 // single byte opcode
5981 setMachineCodes(mi++, (byte) 0x21);
5982 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5983 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5984 }
5985
5986 /**
5987 * Generate a absolute--register AND. That is,
5988 * <PRE>
5989 * [dstDisp] &= (quad) srcReg
5990 * </PRE>
5991 *
5992 * @param dstDisp the destination address
5993 * @param srcReg the source register
5994 */
5995 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
5996 public final void emitAND_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
5997 int miStart = mi;
5998 // no group 1 to 4 prefix byte
5999 generateREXprefix(true, srcReg, null, null);
6000 // single byte opcode
6001 setMachineCodes(mi++, (byte) 0x21);
6002 emitAbsRegOperands(dstDisp, srcReg);
6003 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
6004 }
6005
6006 /**
6007 * Generate a register-index--register AND. That is,
6008 * <PRE>
6009 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) srcReg
6010 * </PRE>
6011 *
6012 * @param dstBase the base register
6013 * @param dstIndex the destination index register
6014 * @param dstScale the destination shift amount
6015 * @param dstDisp the destination displacement
6016 * @param srcReg the source register
6017 */
6018 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
6019 public final void emitAND_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6020 int miStart = mi;
6021 // no group 1 to 4 prefix byte
6022 generateREXprefix(true, srcReg, dstIndex, dstBase);
6023 // single byte opcode
6024 setMachineCodes(mi++, (byte) 0x21);
6025 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
6026 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
6027 }
6028
6029 /**
6030 * Generate a register-displacement--register AND. That is,
6031 * <PRE>
6032 * [dstBase + dstDisp] &= (quad) srcReg
6033 * </PRE>
6034 *
6035 * @param dstBase the base register
6036 * @param dstDisp the destination displacement
6037 * @param srcReg the source register
6038 */
6039 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
6040 public final void emitAND_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
6041 int miStart = mi;
6042 // no group 1 to 4 prefix byte
6043 generateREXprefix(true, srcReg, null, dstBase);
6044 // single byte opcode
6045 setMachineCodes(mi++, (byte) 0x21);
6046 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
6047 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
6048 }
6049
6050 /**
6051 * Generate a register--register AND. That is,
6052 * <PRE>
6053 * dstReg &= (quad) srcReg
6054 * </PRE>
6055 *
6056 * @param dstReg the destination register
6057 * @param srcReg the source register
6058 */
6059 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6060 public final void emitAND_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
6061 int miStart = mi;
6062 // no group 1 to 4 prefix byte
6063 generateREXprefix(true, srcReg, null, dstReg);
6064 // single byte opcode
6065 setMachineCodes(mi++, (byte) 0x21);
6066 emitRegRegOperands(dstReg, srcReg);
6067 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
6068 }
6069
6070 /**
6071 * Generate a register--register-displacement AND. That is,
6072 * <PRE>
6073 * dstReg &= (quad) [srcReg + srcDisp]
6074 * </PRE>
6075 *
6076 * @param dstReg the destination register
6077 * @param srcBase the source register
6078 * @param srcDisp the source displacement
6079 */
6080 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6081 public final void emitAND_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
6082 int miStart = mi;
6083 // no group 1 to 4 prefix byte
6084 generateREXprefix(true, dstReg, null, srcBase);
6085 // single byte opcode
6086 setMachineCodes(mi++, (byte) 0x23);
6087 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
6088 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
6089 }
6090
6091 /**
6092 * Generate a register--register-offset AND. That is,
6093 * <PRE>
6094 * dstReg &= (quad) [srcIndex<<srcScale + srcDisp]
6095 * </PRE>
6096 *
6097 * @param dstReg the destination register
6098 * @param srcIndex the source index register
6099 * @param srcScale the source shift amount
6100 * @param srcDisp the source displacement
6101 */
6102 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6103 public final void emitAND_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
6104 int miStart = mi;
6105 // no group 1 to 4 prefix byte
6106 generateREXprefix(true, dstReg, srcIndex, null);
6107 // single byte opcode
6108 setMachineCodes(mi++, (byte) 0x23);
6109 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
6110 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
6111 }
6112
6113 /**
6114 * Generate a register--register-offset AND. That is,
6115 * <PRE>
6116 * dstReg &= (quad) [srcDisp]
6117 * </PRE>
6118 *
6119 * @param dstReg the destination register
6120 * @param srcDisp the source displacement
6121 */
6122 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6123 public final void emitAND_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
6124 int miStart = mi;
6125 // no group 1 to 4 prefix byte
6126 generateREXprefix(true, dstReg, null, null);
6127 // single byte opcode
6128 setMachineCodes(mi++, (byte) 0x23);
6129 emitAbsRegOperands(srcDisp, dstReg);
6130 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
6131 }
6132
6133 /**
6134 * Generate a register--register-offset AND. That is,
6135 * <PRE>
6136 * dstReg &= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
6137 * </PRE>
6138 *
6139 * @param dstReg the destination register
6140 * @param srcBase the source base register
6141 * @param srcIndex the source index register
6142 * @param srcScale the source shift amount
6143 * @param srcDisp the source displacement
6144 */
6145 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
6146 public final void emitAND_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
6147 int miStart = mi;
6148 // no group 1 to 4 prefix byte
6149 generateREXprefix(true, dstReg, srcIndex, srcBase);
6150 // single byte opcode
6151 setMachineCodes(mi++, (byte) 0x23);
6152 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
6153 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
6154 }
6155
6156 /**
6157 * Generate a register--register(indirect) AND. That is,
6158 * <PRE>
6159 * dstReg &= (quad) [srcBase]
6160 * </PRE>
6161 *
6162 * @param dstReg the destination register
6163 * @param srcBase the source base register
6164 */
6165 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6166 public final void emitAND_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
6167 int miStart = mi;
6168 // no group 1 to 4 prefix byte
6169 generateREXprefix(true, dstReg, null, srcBase);
6170 // single byte opcode
6171 setMachineCodes(mi++, (byte) 0x23);
6172 emitRegIndirectRegOperands(srcBase, dstReg);
6173 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
6174 }
6175
6176 /**
6177 * Generate a register(indirect)--register AND. That is,
6178 * <PRE>
6179 * [dstBase] &= (byte) srcReg
6180 * </PRE>
6181 *
6182 * @param dstBase the destination base
6183 * @param srcReg the source register
6184 */
6185 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6186 public final void emitAND_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
6187 int miStart = mi;
6188 // no group 1 to 4 prefix byte
6189 generateREXprefix(false, srcReg, null, dstBase);
6190 // single byte opcode
6191 setMachineCodes(mi++, (byte) 0x20);
6192 emitRegIndirectRegOperands(dstBase, srcReg);
6193 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
6194 }
6195
6196 /**
6197 * Generate a register-offset--register AND. That is,
6198 * <PRE>
6199 * [dstReg<<dstScale + dstDisp] &= (byte) srcReg
6200 * </PRE>
6201 *
6202 * @param dstIndex the destination index register
6203 * @param dstScale the destination shift amount
6204 * @param dstDisp the destination displacement
6205 * @param srcReg the source register
6206 */
6207 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
6208 public final void emitAND_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6209 int miStart = mi;
6210 // no group 1 to 4 prefix byte
6211 generateREXprefix(false, srcReg, dstIndex, null);
6212 // single byte opcode
6213 setMachineCodes(mi++, (byte) 0x20);
6214 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
6215 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
6216 }
6217
6218 /**
6219 * Generate a absolute--register AND. That is,
6220 * <PRE>
6221 * [dstDisp] &= (byte) srcReg
6222 * </PRE>
6223 *
6224 * @param dstDisp the destination address
6225 * @param srcReg the source register
6226 */
6227 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
6228 public final void emitAND_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
6229 int miStart = mi;
6230 // no group 1 to 4 prefix byte
6231 generateREXprefix(false, srcReg, null, null);
6232 // single byte opcode
6233 setMachineCodes(mi++, (byte) 0x20);
6234 emitAbsRegOperands(dstDisp, srcReg);
6235 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
6236 }
6237
6238 /**
6239 * Generate a register-index--register AND. That is,
6240 * <PRE>
6241 * [dstBase + dstIndex<<dstScale + dstDisp] &= (byte) srcReg
6242 * </PRE>
6243 *
6244 * @param dstBase the base register
6245 * @param dstIndex the destination index register
6246 * @param dstScale the destination shift amount
6247 * @param dstDisp the destination displacement
6248 * @param srcReg the source register
6249 */
6250 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
6251 public final void emitAND_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6252 int miStart = mi;
6253 // no group 1 to 4 prefix byte
6254 generateREXprefix(false, srcReg, dstIndex, dstBase);
6255 // single byte opcode
6256 setMachineCodes(mi++, (byte) 0x20);
6257 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
6258 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
6259 }
6260
6261 /**
6262 * Generate a register-displacement--register AND. That is,
6263 * <PRE>
6264 * [dstBase + dstDisp] &= (byte) srcReg
6265 * </PRE>
6266 *
6267 * @param dstBase the base register
6268 * @param dstDisp the destination displacement
6269 * @param srcReg the source register
6270 */
6271 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
6272 public final void emitAND_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
6273 int miStart = mi;
6274 // no group 1 to 4 prefix byte
6275 generateREXprefix(false, srcReg, null, dstBase);
6276 // single byte opcode
6277 setMachineCodes(mi++, (byte) 0x20);
6278 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
6279 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
6280 }
6281
6282 /**
6283 * Generate a register--register AND. That is,
6284 * <PRE>
6285 * dstReg &= (byte) srcReg
6286 * </PRE>
6287 *
6288 * @param dstReg the destination register
6289 * @param srcReg the source register
6290 */
6291 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6292 public final void emitAND_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
6293 int miStart = mi;
6294 // no group 1 to 4 prefix byte
6295 generateREXprefix(false, srcReg, null, dstReg);
6296 // single byte opcode
6297 setMachineCodes(mi++, (byte) 0x20);
6298 emitRegRegOperands(dstReg, srcReg);
6299 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
6300 }
6301
6302 /**
6303 * Generate a register--register-displacement AND. That is,
6304 * <PRE>
6305 * dstReg &= (byte) [srcReg + srcDisp]
6306 * </PRE>
6307 *
6308 * @param dstReg the destination register
6309 * @param srcBase the source register
6310 * @param srcDisp the source displacement
6311 */
6312 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6313 public final void emitAND_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
6314 int miStart = mi;
6315 // no group 1 to 4 prefix byte
6316 generateREXprefix(false, dstReg, null, srcBase);
6317 // single byte opcode
6318 setMachineCodes(mi++, (byte) 0x22);
6319 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
6320 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
6321 }
6322
6323 /**
6324 * Generate a register--register-offset AND. That is,
6325 * <PRE>
6326 * dstReg &= (byte) [srcIndex<<srcScale + srcDisp]
6327 * </PRE>
6328 *
6329 * @param dstReg the destination register
6330 * @param srcIndex the source index register
6331 * @param srcScale the source shift amount
6332 * @param srcDisp the source displacement
6333 */
6334 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6335 public final void emitAND_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
6336 int miStart = mi;
6337 // no group 1 to 4 prefix byte
6338 generateREXprefix(false, dstReg, srcIndex, null);
6339 // single byte opcode
6340 setMachineCodes(mi++, (byte) 0x22);
6341 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
6342 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
6343 }
6344
6345 /**
6346 * Generate a register--register-offset AND. That is,
6347 * <PRE>
6348 * dstReg &= (byte) [srcDisp]
6349 * </PRE>
6350 *
6351 * @param dstReg the destination register
6352 * @param srcDisp the source displacement
6353 */
6354 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6355 public final void emitAND_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
6356 int miStart = mi;
6357 // no group 1 to 4 prefix byte
6358 generateREXprefix(false, dstReg, null, null);
6359 // single byte opcode
6360 setMachineCodes(mi++, (byte) 0x22);
6361 emitAbsRegOperands(srcDisp, dstReg);
6362 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
6363 }
6364
6365 /**
6366 * Generate a register--register-offset AND. That is,
6367 * <PRE>
6368 * dstReg &= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
6369 * </PRE>
6370 *
6371 * @param dstReg the destination register
6372 * @param srcBase the source base register
6373 * @param srcIndex the source index register
6374 * @param srcScale the source shift amount
6375 * @param srcDisp the source displacement
6376 */
6377 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
6378 public final void emitAND_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
6379 int miStart = mi;
6380 // no group 1 to 4 prefix byte
6381 generateREXprefix(false, dstReg, srcIndex, srcBase);
6382 // single byte opcode
6383 setMachineCodes(mi++, (byte) 0x22);
6384 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
6385 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
6386 }
6387
6388 /**
6389 * Generate a register--register(indirect) AND. That is,
6390 * <PRE>
6391 * dstReg &= (byte) [srcBase]
6392 * </PRE>
6393 *
6394 * @param dstReg the destination register
6395 * @param srcBase the source base register
6396 */
6397 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6398 public final void emitAND_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
6399 int miStart = mi;
6400 // no group 1 to 4 prefix byte
6401 generateREXprefix(false, dstReg, null, srcBase);
6402 // single byte opcode
6403 setMachineCodes(mi++, (byte) 0x22);
6404 emitRegIndirectRegOperands(srcBase, dstReg);
6405 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
6406 }
6407
6408 /**
6409 * Generate a register--immediate AND. That is,
6410 * <PRE>
6411 * dstReg &= imm
6412 * </PRE>
6413 *
6414 * @param dstReg the destination register
6415 * @param imm immediate
6416 */
6417 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6418 public final void emitAND_Reg_Imm(GPR dstReg, int imm) {
6419 int miStart = mi;
6420 // no group 1 to 4 prefix byte
6421 generateREXprefix(false, null, null, dstReg);
6422 // single byte opcode
6423 if (fits(imm,8)) {
6424 setMachineCodes(mi++, (byte) 0x83);
6425 // "register 0x4" is really part of the opcode
6426 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6427 emitImm8((byte)imm);
6428 } else if (dstReg == EAX) {
6429 setMachineCodes(mi++, (byte) 0x25);
6430 emitImm32(imm);
6431 } else {
6432 setMachineCodes(mi++, (byte) 0x81);
6433 // "register 0x4" is really part of the opcode
6434 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6435 emitImm32(imm);
6436 }
6437 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6438 }
6439
6440 /**
6441 * Generate a register-displacement--immediate AND. That is,
6442 * <PRE>
6443 * [dstBase + dstDisp] &= imm
6444 * </PRE>
6445 *
6446 * @param dstBase the destination register
6447 * @param dstDisp the destination displacement
6448 * @param imm immediate
6449 */
6450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6451 public final void emitAND_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
6452 int miStart = mi;
6453 // no group 1 to 4 prefix byte
6454 generateREXprefix(false, null, null, dstBase);
6455 // single byte opcode
6456 if (fits(imm,8)) {
6457 setMachineCodes(mi++, (byte) 0x83);
6458 // "register 0x4" is really part of the opcode
6459 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6460 emitImm8((byte)imm);
6461 } else {
6462 setMachineCodes(mi++, (byte) 0x81);
6463 // "register 0x4" is really part of the opcode
6464 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6465 emitImm32(imm);
6466 }
6467 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6468 }
6469
6470 /**
6471 * Generate a register-offset--immediate AND. That is,
6472 * <PRE>
6473 * [dstIndex<<dstScale + dstDisp] &= imm
6474 * </PRE>
6475 *
6476 * @param dstIndex the destination index register
6477 * @param dstScale the destination shift amount
6478 * @param dstDisp the destination displacement
6479 * @param imm immediate
6480 */
6481 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6482 public final void emitAND_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6483 int miStart = mi;
6484 // no group 1 to 4 prefix byte
6485 generateREXprefix(false, null, dstIndex, null);
6486 // single byte opcode
6487 if (fits(imm,8)) {
6488 setMachineCodes(mi++, (byte) 0x83);
6489 // "register 0x4" is really part of the opcode
6490 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6491 emitImm8((byte)imm);
6492 } else {
6493 setMachineCodes(mi++, (byte) 0x81);
6494 // "register 0x4" is really part of the opcode
6495 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6496 emitImm32(imm);
6497 }
6498 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6499 }
6500
6501 /**
6502 * Generate a absolute--immediate AND. That is,
6503 * <PRE>
6504 * [dstDisp] &= imm
6505 * </PRE>
6506 *
6507 * @param dstDisp the destination displacement
6508 * @param imm immediate
6509 */
6510 public final void emitAND_Abs_Imm(Address dstDisp, int imm) {
6511 int miStart = mi;
6512 // no group 1 to 4 prefix byte
6513 generateREXprefix(false, null, null, null);
6514 // single byte opcode
6515 if (fits(imm,8)) {
6516 setMachineCodes(mi++, (byte) 0x83);
6517 // "register 0x4" is really part of the opcode
6518 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6519 emitImm8((byte)imm);
6520 } else {
6521 setMachineCodes(mi++, (byte) 0x81);
6522 // "register 0x4" is really part of the opcode
6523 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6524 emitImm32(imm);
6525 }
6526 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6527 }
6528
6529 /**
6530 * Generate a register-index--immediate AND. That is,
6531 * <PRE>
6532 * [dstBase + dstIndex<<dstScale + dstDisp] &= imm
6533 * </PRE>
6534 *
6535 * @param dstBase the destination base register
6536 * @param dstIndex the destination index register
6537 * @param dstScale the destination shift amount
6538 * @param dstDisp the destination displacement
6539 * @param imm immediate
6540 */
6541 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6542 public final void emitAND_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6543 int miStart = mi;
6544 // no group 1 to 4 prefix byte
6545 generateREXprefix(false, null, dstIndex, dstBase);
6546 // single byte opcode
6547 if (fits(imm,8)) {
6548 setMachineCodes(mi++, (byte) 0x83);
6549 // "register 0x4" is really part of the opcode
6550 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6551 emitImm8((byte)imm);
6552 } else {
6553 setMachineCodes(mi++, (byte) 0x81);
6554 // "register 0x4" is really part of the opcode
6555 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6556 emitImm32(imm);
6557 }
6558 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6559 }
6560
6561 /**
6562 * Generate a register(indirect)--immediate AND. That is,
6563 * <PRE>
6564 * [dstBase] &= imm
6565 * </PRE>
6566 *
6567 * @param dstBase the destination base register
6568 * @param imm immediate
6569 */
6570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6571 public final void emitAND_RegInd_Imm(GPR dstBase, int imm) {
6572 int miStart = mi;
6573 // no group 1 to 4 prefix byte
6574 generateREXprefix(false, null, null, dstBase);
6575 // single byte opcode
6576 if (fits(imm,8)) {
6577 setMachineCodes(mi++, (byte) 0x83);
6578 // "register 0x4" is really part of the opcode
6579 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6580 emitImm8((byte)imm);
6581 } else {
6582 setMachineCodes(mi++, (byte) 0x81);
6583 // "register 0x4" is really part of the opcode
6584 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6585 emitImm32(imm);
6586 }
6587 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6588 }
6589
6590 /**
6591 * Generate a register--immediate AND. That is,
6592 * <PRE>
6593 * dstReg &= (word) imm
6594 * </PRE>
6595 *
6596 * @param dstReg the destination register
6597 * @param imm immediate
6598 */
6599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6600 public final void emitAND_Reg_Imm_Word(GPR dstReg, int imm) {
6601 int miStart = mi;
6602 setMachineCodes(mi++, (byte) 0x66);
6603 generateREXprefix(false, null, null, dstReg);
6604 // single byte opcode
6605 if (fits(imm,8)) {
6606 setMachineCodes(mi++, (byte) 0x83);
6607 // "register 0x4" is really part of the opcode
6608 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6609 emitImm8((byte)imm);
6610 } else if (dstReg == EAX) {
6611 setMachineCodes(mi++, (byte) 0x25);
6612 emitImm16(imm);
6613 } else {
6614 setMachineCodes(mi++, (byte) 0x81);
6615 // "register 0x4" is really part of the opcode
6616 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6617 emitImm16(imm);
6618 }
6619 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6620 }
6621
6622 /**
6623 * Generate a register-displacement--immediate AND. That is,
6624 * <PRE>
6625 * [dstBase + dstDisp] &= (word) imm
6626 * </PRE>
6627 *
6628 * @param dstBase the destination register
6629 * @param dstDisp the destination displacement
6630 * @param imm immediate
6631 */
6632 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6633 public final void emitAND_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
6634 int miStart = mi;
6635 setMachineCodes(mi++, (byte) 0x66);
6636 generateREXprefix(false, null, null, dstBase);
6637 // single byte opcode
6638 if (fits(imm,8)) {
6639 setMachineCodes(mi++, (byte) 0x83);
6640 // "register 0x4" is really part of the opcode
6641 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6642 emitImm8((byte)imm);
6643 } else {
6644 setMachineCodes(mi++, (byte) 0x81);
6645 // "register 0x4" is really part of the opcode
6646 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6647 emitImm16(imm);
6648 }
6649 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6650 }
6651
6652 /**
6653 * Generate a register-offset--immediate AND. That is,
6654 * <PRE>
6655 * [dstIndex<<dstScale + dstDisp] &= (word) imm
6656 * </PRE>
6657 *
6658 * @param dstIndex the destination index register
6659 * @param dstScale the destination shift amount
6660 * @param dstDisp the destination displacement
6661 * @param imm immediate
6662 */
6663 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6664 public final void emitAND_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6665 int miStart = mi;
6666 setMachineCodes(mi++, (byte) 0x66);
6667 generateREXprefix(false, null, dstIndex, null);
6668 // single byte opcode
6669 if (fits(imm,8)) {
6670 setMachineCodes(mi++, (byte) 0x83);
6671 // "register 0x4" is really part of the opcode
6672 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6673 emitImm8((byte)imm);
6674 } else {
6675 setMachineCodes(mi++, (byte) 0x81);
6676 // "register 0x4" is really part of the opcode
6677 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6678 emitImm16(imm);
6679 }
6680 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6681 }
6682
6683 /**
6684 * Generate a absolute--immediate AND. That is,
6685 * <PRE>
6686 * [dstDisp] &= (word) imm
6687 * </PRE>
6688 *
6689 * @param dstDisp the destination displacement
6690 * @param imm immediate
6691 */
6692 public final void emitAND_Abs_Imm_Word(Address dstDisp, int imm) {
6693 int miStart = mi;
6694 setMachineCodes(mi++, (byte) 0x66);
6695 generateREXprefix(false, null, null, null);
6696 // single byte opcode
6697 if (fits(imm,8)) {
6698 setMachineCodes(mi++, (byte) 0x83);
6699 // "register 0x4" is really part of the opcode
6700 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6701 emitImm8((byte)imm);
6702 } else {
6703 setMachineCodes(mi++, (byte) 0x81);
6704 // "register 0x4" is really part of the opcode
6705 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6706 emitImm16(imm);
6707 }
6708 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6709 }
6710
6711 /**
6712 * Generate a register-index--immediate AND. That is,
6713 * <PRE>
6714 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) imm
6715 * </PRE>
6716 *
6717 * @param dstBase the destination base register
6718 * @param dstIndex the destination index register
6719 * @param dstScale the destination shift amount
6720 * @param dstDisp the destination displacement
6721 * @param imm immediate
6722 */
6723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6724 public final void emitAND_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6725 int miStart = mi;
6726 setMachineCodes(mi++, (byte) 0x66);
6727 generateREXprefix(false, null, dstIndex, dstBase);
6728 // single byte opcode
6729 if (fits(imm,8)) {
6730 setMachineCodes(mi++, (byte) 0x83);
6731 // "register 0x4" is really part of the opcode
6732 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6733 emitImm8((byte)imm);
6734 } else {
6735 setMachineCodes(mi++, (byte) 0x81);
6736 // "register 0x4" is really part of the opcode
6737 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6738 emitImm16(imm);
6739 }
6740 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6741 }
6742
6743 /**
6744 * Generate a register(indirect)--immediate AND. That is,
6745 * <PRE>
6746 * [dstBase] &= (word) imm
6747 * </PRE>
6748 *
6749 * @param dstBase the destination base register
6750 * @param imm immediate
6751 */
6752 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6753 public final void emitAND_RegInd_Imm_Word(GPR dstBase, int imm) {
6754 int miStart = mi;
6755 setMachineCodes(mi++, (byte) 0x66);
6756 generateREXprefix(false, null, null, dstBase);
6757 // single byte opcode
6758 if (fits(imm,8)) {
6759 setMachineCodes(mi++, (byte) 0x83);
6760 // "register 0x4" is really part of the opcode
6761 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6762 emitImm8((byte)imm);
6763 } else {
6764 setMachineCodes(mi++, (byte) 0x81);
6765 // "register 0x4" is really part of the opcode
6766 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6767 emitImm16(imm);
6768 }
6769 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6770 }
6771
6772 /**
6773 * Generate a register--immediate AND. That is,
6774 * <PRE>
6775 * dstReg &= (quad) imm
6776 * </PRE>
6777 *
6778 * @param dstReg the destination register
6779 * @param imm immediate
6780 */
6781 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6782 public final void emitAND_Reg_Imm_Quad(GPR dstReg, int imm) {
6783 int miStart = mi;
6784 // no group 1 to 4 prefix byte
6785 generateREXprefix(true, null, null, dstReg);
6786 // single byte opcode
6787 if (fits(imm,8)) {
6788 setMachineCodes(mi++, (byte) 0x83);
6789 // "register 0x4" is really part of the opcode
6790 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6791 emitImm8((byte)imm);
6792 } else if (dstReg == EAX) {
6793 setMachineCodes(mi++, (byte) 0x25);
6794 emitImm32(imm);
6795 } else {
6796 setMachineCodes(mi++, (byte) 0x81);
6797 // "register 0x4" is really part of the opcode
6798 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6799 emitImm32(imm);
6800 }
6801 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6802 }
6803
6804 /**
6805 * Generate a register-displacement--immediate AND. That is,
6806 * <PRE>
6807 * [dstBase + dstDisp] &= (quad) imm
6808 * </PRE>
6809 *
6810 * @param dstBase the destination register
6811 * @param dstDisp the destination displacement
6812 * @param imm immediate
6813 */
6814 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6815 public final void emitAND_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
6816 int miStart = mi;
6817 // no group 1 to 4 prefix byte
6818 generateREXprefix(true, null, null, dstBase);
6819 // single byte opcode
6820 if (fits(imm,8)) {
6821 setMachineCodes(mi++, (byte) 0x83);
6822 // "register 0x4" is really part of the opcode
6823 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6824 emitImm8((byte)imm);
6825 } else {
6826 setMachineCodes(mi++, (byte) 0x81);
6827 // "register 0x4" is really part of the opcode
6828 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6829 emitImm32(imm);
6830 }
6831 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6832 }
6833
6834 /**
6835 * Generate a register-offset--immediate AND. That is,
6836 * <PRE>
6837 * [dstIndex<<dstScale + dstDisp] &= (quad) imm
6838 * </PRE>
6839 *
6840 * @param dstIndex the destination index register
6841 * @param dstScale the destination shift amount
6842 * @param dstDisp the destination displacement
6843 * @param imm immediate
6844 */
6845 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6846 public final void emitAND_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6847 int miStart = mi;
6848 // no group 1 to 4 prefix byte
6849 generateREXprefix(true, null, dstIndex, null);
6850 // single byte opcode
6851 if (fits(imm,8)) {
6852 setMachineCodes(mi++, (byte) 0x83);
6853 // "register 0x4" is really part of the opcode
6854 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6855 emitImm8((byte)imm);
6856 } else {
6857 setMachineCodes(mi++, (byte) 0x81);
6858 // "register 0x4" is really part of the opcode
6859 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6860 emitImm32(imm);
6861 }
6862 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6863 }
6864
6865 /**
6866 * Generate a absolute--immediate AND. That is,
6867 * <PRE>
6868 * [dstDisp] &= (quad) imm
6869 * </PRE>
6870 *
6871 * @param dstDisp the destination displacement
6872 * @param imm immediate
6873 */
6874 public final void emitAND_Abs_Imm_Quad(Address dstDisp, int imm) {
6875 int miStart = mi;
6876 // no group 1 to 4 prefix byte
6877 generateREXprefix(true, null, null, null);
6878 // single byte opcode
6879 if (fits(imm,8)) {
6880 setMachineCodes(mi++, (byte) 0x83);
6881 // "register 0x4" is really part of the opcode
6882 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6883 emitImm8((byte)imm);
6884 } else {
6885 setMachineCodes(mi++, (byte) 0x81);
6886 // "register 0x4" is really part of the opcode
6887 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6888 emitImm32(imm);
6889 }
6890 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6891 }
6892
6893 /**
6894 * Generate a register-index--immediate AND. That is,
6895 * <PRE>
6896 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) imm
6897 * </PRE>
6898 *
6899 * @param dstBase the destination base register
6900 * @param dstIndex the destination index register
6901 * @param dstScale the destination shift amount
6902 * @param dstDisp the destination displacement
6903 * @param imm immediate
6904 */
6905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6906 public final void emitAND_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6907 int miStart = mi;
6908 // no group 1 to 4 prefix byte
6909 generateREXprefix(true, null, dstIndex, dstBase);
6910 // single byte opcode
6911 if (fits(imm,8)) {
6912 setMachineCodes(mi++, (byte) 0x83);
6913 // "register 0x4" is really part of the opcode
6914 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6915 emitImm8((byte)imm);
6916 } else {
6917 setMachineCodes(mi++, (byte) 0x81);
6918 // "register 0x4" is really part of the opcode
6919 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6920 emitImm32(imm);
6921 }
6922 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6923 }
6924
6925 /**
6926 * Generate a register(indirect)--immediate AND. That is,
6927 * <PRE>
6928 * [dstBase] &= (quad) imm
6929 * </PRE>
6930 *
6931 * @param dstBase the destination base register
6932 * @param imm immediate
6933 */
6934 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6935 public final void emitAND_RegInd_Imm_Quad(GPR dstBase, int imm) {
6936 int miStart = mi;
6937 // no group 1 to 4 prefix byte
6938 generateREXprefix(true, null, null, dstBase);
6939 // single byte opcode
6940 if (fits(imm,8)) {
6941 setMachineCodes(mi++, (byte) 0x83);
6942 // "register 0x4" is really part of the opcode
6943 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6944 emitImm8((byte)imm);
6945 } else {
6946 setMachineCodes(mi++, (byte) 0x81);
6947 // "register 0x4" is really part of the opcode
6948 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6949 emitImm32(imm);
6950 }
6951 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6952 }
6953
6954 /**
6955 * Generate a register--immediate AND. That is,
6956 * <PRE>
6957 * dstReg &= (byte) imm
6958 * </PRE>
6959 *
6960 * @param dstReg the destination register
6961 * @param imm immediate
6962 */
6963 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6964 public final void emitAND_Reg_Imm_Byte(GPR dstReg, int imm) {
6965 int miStart = mi;
6966 if (dstReg == EAX) {
6967 setMachineCodes(mi++, (byte) 0x24);
6968 emitImm8(imm);
6969 } else {
6970 generateREXprefix(false, null, null, dstReg);
6971 setMachineCodes(mi++, (byte) 0x80);
6972 // "register 0x4" is really part of the opcode
6973 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6974 emitImm8(imm);
6975 }
6976 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6977 }
6978
6979 /**
6980 * Generate a register-displacement--immediate AND. That is,
6981 * <PRE>
6982 * [dstBase + dstDisp] &= (byte) imm
6983 * </PRE>
6984 *
6985 * @param dstBase the destination register
6986 * @param dstDisp the destination displacement
6987 * @param imm immediate
6988 */
6989 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6990 public final void emitAND_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
6991 int miStart = mi;
6992 generateREXprefix(false, null, null, dstBase);
6993 setMachineCodes(mi++, (byte) 0x80);
6994 // "register 0x4" is really part of the opcode
6995 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6996 emitImm8(imm);
6997 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6998 }
6999
7000 /**
7001 * Generate a register-index--immediate AND. That is,
7002 * <PRE>
7003 * [dstBase + dstIndex<<scale + dstDisp] &= (byte) imm
7004 * </PRE>
7005 *
7006 * @param dstBase the destination base register
7007 * @param dstIndex the destination index register
7008 * @param dstScale the destination shift amount
7009 * @param dstDisp the destination displacement
7010 * @param imm immediate
7011 */
7012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7013 public final void emitAND_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
7014 int miStart = mi;
7015 generateREXprefix(false, null, dstIndex, dstBase);
7016 setMachineCodes(mi++, (byte) 0x80);
7017 // "register 0x4" is really part of the opcode
7018 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
7019 emitImm8(imm);
7020 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
7021 }
7022
7023 /**
7024 * Generate a register-offset--immediate AND. That is,
7025 * <PRE>
7026 * [dstIndex<<dstScale + dstDisp] &= (byte) imm
7027 * </PRE>
7028 *
7029 * @param dstIndex the destination index register
7030 * @param dstScale the destination shift amount
7031 * @param dstDisp the destination displacement
7032 * @param imm immediate
7033 */
7034 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7035 public final void emitAND_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
7036 int miStart = mi;
7037 generateREXprefix(false, null, dstIndex, null);
7038 setMachineCodes(mi++, (byte) 0x80);
7039 // "register 0x4" is really part of the opcode
7040 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
7041 emitImm8(imm);
7042 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
7043 }
7044
7045 /**
7046 * Generate a absolute--immediate AND. That is,
7047 * <PRE>
7048 * [dstDisp] &= (byte) imm
7049 * </PRE>
7050 *
7051 * @param dstDisp the destination displacement
7052 * @param imm immediate
7053 */
7054 public final void emitAND_Abs_Imm_Byte(Address dstDisp, int imm) {
7055 int miStart = mi;
7056 generateREXprefix(false, null, null, null);
7057 setMachineCodes(mi++, (byte) 0x80);
7058 // "register 0x4" is really part of the opcode
7059 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
7060 emitImm8(imm);
7061 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
7062 }
7063
7064 /**
7065 * Generate a register(indirect)--immediate AND. That is,
7066 * <PRE>
7067 * [dstBase] &= (byte) imm
7068 * </PRE>
7069 *
7070 * @param dstBase the destination base register
7071 * @param imm immediate
7072 */
7073 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7074 public final void emitAND_RegInd_Imm_Byte(GPR dstBase, int imm) {
7075 int miStart = mi;
7076 generateREXprefix(false, null, null, dstBase);
7077 setMachineCodes(mi++, (byte) 0x80);
7078 // "register 0x4" is really part of the opcode
7079 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
7080 emitImm8(imm);
7081 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
7082 }
7083
7084 /**
7085 * Generate a register(indirect)--register CMP. That is,
7086 * <PRE>
7087 * [dstBase] == srcReg
7088 * </PRE>
7089 *
7090 * @param dstBase the destination base
7091 * @param srcReg the source register
7092 */
7093 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7094 public final void emitCMP_RegInd_Reg(GPR dstBase, GPR srcReg) {
7095 int miStart = mi;
7096 // no group 1 to 4 prefix byte
7097 generateREXprefix(false, srcReg, null, dstBase);
7098 // single byte opcode
7099 setMachineCodes(mi++, (byte) 0x39);
7100 emitRegIndirectRegOperands(dstBase, srcReg);
7101 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7102 }
7103
7104 /**
7105 * Generate a register-offset--register CMP. That is,
7106 * <PRE>
7107 * [dstReg<<dstScale + dstDisp] == srcReg
7108 * </PRE>
7109 *
7110 * @param dstIndex the destination index register
7111 * @param dstScale the destination shift amount
7112 * @param dstDisp the destination displacement
7113 * @param srcReg the source register
7114 */
7115 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7116 public final void emitCMP_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7117 int miStart = mi;
7118 // no group 1 to 4 prefix byte
7119 generateREXprefix(false, srcReg, dstIndex, null);
7120 // single byte opcode
7121 setMachineCodes(mi++, (byte) 0x39);
7122 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7123 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7124 }
7125
7126 /**
7127 * Generate a absolute--register CMP. That is,
7128 * <PRE>
7129 * [dstDisp] == srcReg
7130 * </PRE>
7131 *
7132 * @param dstDisp the destination address
7133 * @param srcReg the source register
7134 */
7135 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7136 public final void emitCMP_Abs_Reg(Address dstDisp, GPR srcReg) {
7137 int miStart = mi;
7138 // no group 1 to 4 prefix byte
7139 generateREXprefix(false, srcReg, null, null);
7140 // single byte opcode
7141 setMachineCodes(mi++, (byte) 0x39);
7142 emitAbsRegOperands(dstDisp, srcReg);
7143 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7144 }
7145
7146 /**
7147 * Generate a register-index--register CMP. That is,
7148 * <PRE>
7149 * [dstBase + dstIndex<<dstScale + dstDisp] == srcReg
7150 * </PRE>
7151 *
7152 * @param dstBase the base register
7153 * @param dstIndex the destination index register
7154 * @param dstScale the destination shift amount
7155 * @param dstDisp the destination displacement
7156 * @param srcReg the source register
7157 */
7158 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7159 public final void emitCMP_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7160 int miStart = mi;
7161 // no group 1 to 4 prefix byte
7162 generateREXprefix(false, srcReg, dstIndex, dstBase);
7163 // single byte opcode
7164 setMachineCodes(mi++, (byte) 0x39);
7165 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7166 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7167 }
7168
7169 /**
7170 * Generate a register-displacement--register CMP. That is,
7171 * <PRE>
7172 * [dstBase + dstDisp] == srcReg
7173 * </PRE>
7174 *
7175 * @param dstBase the base register
7176 * @param dstDisp the destination displacement
7177 * @param srcReg the source register
7178 */
7179 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7180 public final void emitCMP_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
7181 int miStart = mi;
7182 // no group 1 to 4 prefix byte
7183 generateREXprefix(false, srcReg, null, dstBase);
7184 // single byte opcode
7185 setMachineCodes(mi++, (byte) 0x39);
7186 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7187 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7188 }
7189
7190 /**
7191 * Generate a register--register CMP. That is,
7192 * <PRE>
7193 * dstReg == srcReg
7194 * </PRE>
7195 *
7196 * @param dstReg the destination register
7197 * @param srcReg the source register
7198 */
7199 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7200 public final void emitCMP_Reg_Reg(GPR dstReg, GPR srcReg) {
7201 int miStart = mi;
7202 // no group 1 to 4 prefix byte
7203 generateREXprefix(false, srcReg, null, dstReg);
7204 // single byte opcode
7205 setMachineCodes(mi++, (byte) 0x39);
7206 emitRegRegOperands(dstReg, srcReg);
7207 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7208 }
7209
7210 /**
7211 * Generate a register--register-displacement CMP. That is,
7212 * <PRE>
7213 * dstReg == [srcReg + srcDisp]
7214 * </PRE>
7215 *
7216 * @param dstReg the destination register
7217 * @param srcBase the source register
7218 * @param srcDisp the source displacement
7219 */
7220 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7221 public final void emitCMP_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
7222 int miStart = mi;
7223 // no group 1 to 4 prefix byte
7224 generateREXprefix(false, dstReg, null, srcBase);
7225 // single byte opcode
7226 setMachineCodes(mi++, (byte) 0x3B);
7227 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7228 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7229 }
7230
7231 /**
7232 * Generate a register--register-offset CMP. That is,
7233 * <PRE>
7234 * dstReg == [srcIndex<<srcScale + srcDisp]
7235 * </PRE>
7236 *
7237 * @param dstReg the destination register
7238 * @param srcIndex the source index register
7239 * @param srcScale the source shift amount
7240 * @param srcDisp the source displacement
7241 */
7242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7243 public final void emitCMP_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7244 int miStart = mi;
7245 // no group 1 to 4 prefix byte
7246 generateREXprefix(false, dstReg, srcIndex, null);
7247 // single byte opcode
7248 setMachineCodes(mi++, (byte) 0x3B);
7249 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7250 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7251 }
7252
7253 /**
7254 * Generate a register--register-offset CMP. That is,
7255 * <PRE>
7256 * dstReg == [srcDisp]
7257 * </PRE>
7258 *
7259 * @param dstReg the destination register
7260 * @param srcDisp the source displacement
7261 */
7262 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7263 public final void emitCMP_Reg_Abs(GPR dstReg, Address srcDisp) {
7264 int miStart = mi;
7265 // no group 1 to 4 prefix byte
7266 generateREXprefix(false, dstReg, null, null);
7267 // single byte opcode
7268 setMachineCodes(mi++, (byte) 0x3B);
7269 emitAbsRegOperands(srcDisp, dstReg);
7270 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7271 }
7272
7273 /**
7274 * Generate a register--register-offset CMP. That is,
7275 * <PRE>
7276 * dstReg == [srcBase + srcIndex<<srcScale + srcDisp]
7277 * </PRE>
7278 *
7279 * @param dstReg the destination register
7280 * @param srcBase the source base register
7281 * @param srcIndex the source index register
7282 * @param srcScale the source shift amount
7283 * @param srcDisp the source displacement
7284 */
7285 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7286 public final void emitCMP_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7287 int miStart = mi;
7288 // no group 1 to 4 prefix byte
7289 generateREXprefix(false, dstReg, srcIndex, srcBase);
7290 // single byte opcode
7291 setMachineCodes(mi++, (byte) 0x3B);
7292 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7293 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7294 }
7295
7296 /**
7297 * Generate a register--register(indirect) CMP. That is,
7298 * <PRE>
7299 * dstReg == [srcBase]
7300 * </PRE>
7301 *
7302 * @param dstReg the destination register
7303 * @param srcBase the source base register
7304 */
7305 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7306 public final void emitCMP_Reg_RegInd(GPR dstReg, GPR srcBase) {
7307 int miStart = mi;
7308 // no group 1 to 4 prefix byte
7309 generateREXprefix(false, dstReg, null, srcBase);
7310 // single byte opcode
7311 setMachineCodes(mi++, (byte) 0x3B);
7312 emitRegIndirectRegOperands(srcBase, dstReg);
7313 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7314 }
7315
7316 /**
7317 * Generate a register(indirect)--register CMP. That is,
7318 * <PRE>
7319 * [dstBase] == (word) srcReg
7320 * </PRE>
7321 *
7322 * @param dstBase the destination base
7323 * @param srcReg the source register
7324 */
7325 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7326 public final void emitCMP_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
7327 int miStart = mi;
7328 setMachineCodes(mi++, (byte) 0x66);
7329 generateREXprefix(false, srcReg, null, dstBase);
7330 // single byte opcode
7331 setMachineCodes(mi++, (byte) 0x39);
7332 emitRegIndirectRegOperands(dstBase, srcReg);
7333 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7334 }
7335
7336 /**
7337 * Generate a register-offset--register CMP. That is,
7338 * <PRE>
7339 * [dstReg<<dstScale + dstDisp] == (word) srcReg
7340 * </PRE>
7341 *
7342 * @param dstIndex the destination index register
7343 * @param dstScale the destination shift amount
7344 * @param dstDisp the destination displacement
7345 * @param srcReg the source register
7346 */
7347 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7348 public final void emitCMP_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7349 int miStart = mi;
7350 setMachineCodes(mi++, (byte) 0x66);
7351 generateREXprefix(false, srcReg, dstIndex, null);
7352 // single byte opcode
7353 setMachineCodes(mi++, (byte) 0x39);
7354 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7355 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7356 }
7357
7358 /**
7359 * Generate a absolute--register CMP. That is,
7360 * <PRE>
7361 * [dstDisp] == (word) srcReg
7362 * </PRE>
7363 *
7364 * @param dstDisp the destination address
7365 * @param srcReg the source register
7366 */
7367 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7368 public final void emitCMP_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
7369 int miStart = mi;
7370 setMachineCodes(mi++, (byte) 0x66);
7371 generateREXprefix(false, srcReg, null, null);
7372 // single byte opcode
7373 setMachineCodes(mi++, (byte) 0x39);
7374 emitAbsRegOperands(dstDisp, srcReg);
7375 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7376 }
7377
7378 /**
7379 * Generate a register-index--register CMP. That is,
7380 * <PRE>
7381 * [dstBase + dstIndex<<dstScale + dstDisp] == (word) srcReg
7382 * </PRE>
7383 *
7384 * @param dstBase the base register
7385 * @param dstIndex the destination index register
7386 * @param dstScale the destination shift amount
7387 * @param dstDisp the destination displacement
7388 * @param srcReg the source register
7389 */
7390 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7391 public final void emitCMP_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7392 int miStart = mi;
7393 setMachineCodes(mi++, (byte) 0x66);
7394 generateREXprefix(false, srcReg, dstIndex, dstBase);
7395 // single byte opcode
7396 setMachineCodes(mi++, (byte) 0x39);
7397 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7398 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7399 }
7400
7401 /**
7402 * Generate a register-displacement--register CMP. That is,
7403 * <PRE>
7404 * [dstBase + dstDisp] == (word) srcReg
7405 * </PRE>
7406 *
7407 * @param dstBase the base register
7408 * @param dstDisp the destination displacement
7409 * @param srcReg the source register
7410 */
7411 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7412 public final void emitCMP_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
7413 int miStart = mi;
7414 setMachineCodes(mi++, (byte) 0x66);
7415 generateREXprefix(false, srcReg, null, dstBase);
7416 // single byte opcode
7417 setMachineCodes(mi++, (byte) 0x39);
7418 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7419 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7420 }
7421
7422 /**
7423 * Generate a register--register CMP. That is,
7424 * <PRE>
7425 * dstReg == (word) srcReg
7426 * </PRE>
7427 *
7428 * @param dstReg the destination register
7429 * @param srcReg the source register
7430 */
7431 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7432 public final void emitCMP_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
7433 int miStart = mi;
7434 setMachineCodes(mi++, (byte) 0x66);
7435 generateREXprefix(false, srcReg, null, dstReg);
7436 // single byte opcode
7437 setMachineCodes(mi++, (byte) 0x39);
7438 emitRegRegOperands(dstReg, srcReg);
7439 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7440 }
7441
7442 /**
7443 * Generate a register--register-displacement CMP. That is,
7444 * <PRE>
7445 * dstReg == (word) [srcReg + srcDisp]
7446 * </PRE>
7447 *
7448 * @param dstReg the destination register
7449 * @param srcBase the source register
7450 * @param srcDisp the source displacement
7451 */
7452 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7453 public final void emitCMP_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
7454 int miStart = mi;
7455 setMachineCodes(mi++, (byte) 0x66);
7456 generateREXprefix(false, dstReg, null, srcBase);
7457 // single byte opcode
7458 setMachineCodes(mi++, (byte) 0x3B);
7459 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7460 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7461 }
7462
7463 /**
7464 * Generate a register--register-offset CMP. That is,
7465 * <PRE>
7466 * dstReg == (word) [srcIndex<<srcScale + srcDisp]
7467 * </PRE>
7468 *
7469 * @param dstReg the destination register
7470 * @param srcIndex the source index register
7471 * @param srcScale the source shift amount
7472 * @param srcDisp the source displacement
7473 */
7474 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7475 public final void emitCMP_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7476 int miStart = mi;
7477 setMachineCodes(mi++, (byte) 0x66);
7478 generateREXprefix(false, dstReg, srcIndex, null);
7479 // single byte opcode
7480 setMachineCodes(mi++, (byte) 0x3B);
7481 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7482 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7483 }
7484
7485 /**
7486 * Generate a register--register-offset CMP. That is,
7487 * <PRE>
7488 * dstReg == (word) [srcDisp]
7489 * </PRE>
7490 *
7491 * @param dstReg the destination register
7492 * @param srcDisp the source displacement
7493 */
7494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7495 public final void emitCMP_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
7496 int miStart = mi;
7497 setMachineCodes(mi++, (byte) 0x66);
7498 generateREXprefix(false, dstReg, null, null);
7499 // single byte opcode
7500 setMachineCodes(mi++, (byte) 0x3B);
7501 emitAbsRegOperands(srcDisp, dstReg);
7502 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7503 }
7504
7505 /**
7506 * Generate a register--register-offset CMP. That is,
7507 * <PRE>
7508 * dstReg == (word) [srcBase + srcIndex<<srcScale + srcDisp]
7509 * </PRE>
7510 *
7511 * @param dstReg the destination register
7512 * @param srcBase the source base register
7513 * @param srcIndex the source index register
7514 * @param srcScale the source shift amount
7515 * @param srcDisp the source displacement
7516 */
7517 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7518 public final void emitCMP_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7519 int miStart = mi;
7520 setMachineCodes(mi++, (byte) 0x66);
7521 generateREXprefix(false, dstReg, srcIndex, srcBase);
7522 // single byte opcode
7523 setMachineCodes(mi++, (byte) 0x3B);
7524 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7525 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7526 }
7527
7528 /**
7529 * Generate a register--register(indirect) CMP. That is,
7530 * <PRE>
7531 * dstReg == (word) [srcBase]
7532 * </PRE>
7533 *
7534 * @param dstReg the destination register
7535 * @param srcBase the source base register
7536 */
7537 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7538 public final void emitCMP_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
7539 int miStart = mi;
7540 setMachineCodes(mi++, (byte) 0x66);
7541 generateREXprefix(false, dstReg, null, srcBase);
7542 // single byte opcode
7543 setMachineCodes(mi++, (byte) 0x3B);
7544 emitRegIndirectRegOperands(srcBase, dstReg);
7545 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7546 }
7547
7548 /**
7549 * Generate a register(indirect)--register CMP. That is,
7550 * <PRE>
7551 * [dstBase] == (quad) srcReg
7552 * </PRE>
7553 *
7554 * @param dstBase the destination base
7555 * @param srcReg the source register
7556 */
7557 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7558 public final void emitCMP_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
7559 int miStart = mi;
7560 // no group 1 to 4 prefix byte
7561 generateREXprefix(true, srcReg, null, dstBase);
7562 // single byte opcode
7563 setMachineCodes(mi++, (byte) 0x39);
7564 emitRegIndirectRegOperands(dstBase, srcReg);
7565 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7566 }
7567
7568 /**
7569 * Generate a register-offset--register CMP. That is,
7570 * <PRE>
7571 * [dstReg<<dstScale + dstDisp] == (quad) srcReg
7572 * </PRE>
7573 *
7574 * @param dstIndex the destination index register
7575 * @param dstScale the destination shift amount
7576 * @param dstDisp the destination displacement
7577 * @param srcReg the source register
7578 */
7579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7580 public final void emitCMP_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7581 int miStart = mi;
7582 // no group 1 to 4 prefix byte
7583 generateREXprefix(true, srcReg, dstIndex, null);
7584 // single byte opcode
7585 setMachineCodes(mi++, (byte) 0x39);
7586 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7587 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7588 }
7589
7590 /**
7591 * Generate a absolute--register CMP. That is,
7592 * <PRE>
7593 * [dstDisp] == (quad) srcReg
7594 * </PRE>
7595 *
7596 * @param dstDisp the destination address
7597 * @param srcReg the source register
7598 */
7599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7600 public final void emitCMP_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
7601 int miStart = mi;
7602 // no group 1 to 4 prefix byte
7603 generateREXprefix(true, srcReg, null, null);
7604 // single byte opcode
7605 setMachineCodes(mi++, (byte) 0x39);
7606 emitAbsRegOperands(dstDisp, srcReg);
7607 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7608 }
7609
7610 /**
7611 * Generate a register-index--register CMP. That is,
7612 * <PRE>
7613 * [dstBase + dstIndex<<dstScale + dstDisp] == (quad) srcReg
7614 * </PRE>
7615 *
7616 * @param dstBase the base register
7617 * @param dstIndex the destination index register
7618 * @param dstScale the destination shift amount
7619 * @param dstDisp the destination displacement
7620 * @param srcReg the source register
7621 */
7622 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7623 public final void emitCMP_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7624 int miStart = mi;
7625 // no group 1 to 4 prefix byte
7626 generateREXprefix(true, srcReg, dstIndex, dstBase);
7627 // single byte opcode
7628 setMachineCodes(mi++, (byte) 0x39);
7629 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7630 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7631 }
7632
7633 /**
7634 * Generate a register-displacement--register CMP. That is,
7635 * <PRE>
7636 * [dstBase + dstDisp] == (quad) srcReg
7637 * </PRE>
7638 *
7639 * @param dstBase the base register
7640 * @param dstDisp the destination displacement
7641 * @param srcReg the source register
7642 */
7643 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7644 public final void emitCMP_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
7645 int miStart = mi;
7646 // no group 1 to 4 prefix byte
7647 generateREXprefix(true, srcReg, null, dstBase);
7648 // single byte opcode
7649 setMachineCodes(mi++, (byte) 0x39);
7650 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7651 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7652 }
7653
7654 /**
7655 * Generate a register--register CMP. That is,
7656 * <PRE>
7657 * dstReg == (quad) srcReg
7658 * </PRE>
7659 *
7660 * @param dstReg the destination register
7661 * @param srcReg the source register
7662 */
7663 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7664 public final void emitCMP_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
7665 int miStart = mi;
7666 // no group 1 to 4 prefix byte
7667 generateREXprefix(true, srcReg, null, dstReg);
7668 // single byte opcode
7669 setMachineCodes(mi++, (byte) 0x39);
7670 emitRegRegOperands(dstReg, srcReg);
7671 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7672 }
7673
7674 /**
7675 * Generate a register--register-displacement CMP. That is,
7676 * <PRE>
7677 * dstReg == (quad) [srcReg + srcDisp]
7678 * </PRE>
7679 *
7680 * @param dstReg the destination register
7681 * @param srcBase the source register
7682 * @param srcDisp the source displacement
7683 */
7684 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7685 public final void emitCMP_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
7686 int miStart = mi;
7687 // no group 1 to 4 prefix byte
7688 generateREXprefix(true, dstReg, null, srcBase);
7689 // single byte opcode
7690 setMachineCodes(mi++, (byte) 0x3B);
7691 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7692 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7693 }
7694
7695 /**
7696 * Generate a register--register-offset CMP. That is,
7697 * <PRE>
7698 * dstReg == (quad) [srcIndex<<srcScale + srcDisp]
7699 * </PRE>
7700 *
7701 * @param dstReg the destination register
7702 * @param srcIndex the source index register
7703 * @param srcScale the source shift amount
7704 * @param srcDisp the source displacement
7705 */
7706 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7707 public final void emitCMP_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7708 int miStart = mi;
7709 // no group 1 to 4 prefix byte
7710 generateREXprefix(true, dstReg, srcIndex, null);
7711 // single byte opcode
7712 setMachineCodes(mi++, (byte) 0x3B);
7713 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7714 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7715 }
7716
7717 /**
7718 * Generate a register--register-offset CMP. That is,
7719 * <PRE>
7720 * dstReg == (quad) [srcDisp]
7721 * </PRE>
7722 *
7723 * @param dstReg the destination register
7724 * @param srcDisp the source displacement
7725 */
7726 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7727 public final void emitCMP_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
7728 int miStart = mi;
7729 // no group 1 to 4 prefix byte
7730 generateREXprefix(true, dstReg, null, null);
7731 // single byte opcode
7732 setMachineCodes(mi++, (byte) 0x3B);
7733 emitAbsRegOperands(srcDisp, dstReg);
7734 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7735 }
7736
7737 /**
7738 * Generate a register--register-offset CMP. That is,
7739 * <PRE>
7740 * dstReg == (quad) [srcBase + srcIndex<<srcScale + srcDisp]
7741 * </PRE>
7742 *
7743 * @param dstReg the destination register
7744 * @param srcBase the source base register
7745 * @param srcIndex the source index register
7746 * @param srcScale the source shift amount
7747 * @param srcDisp the source displacement
7748 */
7749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7750 public final void emitCMP_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7751 int miStart = mi;
7752 // no group 1 to 4 prefix byte
7753 generateREXprefix(true, dstReg, srcIndex, srcBase);
7754 // single byte opcode
7755 setMachineCodes(mi++, (byte) 0x3B);
7756 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7757 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7758 }
7759
7760 /**
7761 * Generate a register--register(indirect) CMP. That is,
7762 * <PRE>
7763 * dstReg == (quad) [srcBase]
7764 * </PRE>
7765 *
7766 * @param dstReg the destination register
7767 * @param srcBase the source base register
7768 */
7769 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7770 public final void emitCMP_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
7771 int miStart = mi;
7772 // no group 1 to 4 prefix byte
7773 generateREXprefix(true, dstReg, null, srcBase);
7774 // single byte opcode
7775 setMachineCodes(mi++, (byte) 0x3B);
7776 emitRegIndirectRegOperands(srcBase, dstReg);
7777 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7778 }
7779
7780 /**
7781 * Generate a register(indirect)--register CMP. That is,
7782 * <PRE>
7783 * [dstBase] == (byte) srcReg
7784 * </PRE>
7785 *
7786 * @param dstBase the destination base
7787 * @param srcReg the source register
7788 */
7789 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7790 public final void emitCMP_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
7791 int miStart = mi;
7792 // no group 1 to 4 prefix byte
7793 generateREXprefix(false, srcReg, null, dstBase);
7794 // single byte opcode
7795 setMachineCodes(mi++, (byte) 0x38);
7796 emitRegIndirectRegOperands(dstBase, srcReg);
7797 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7798 }
7799
7800 /**
7801 * Generate a register-offset--register CMP. That is,
7802 * <PRE>
7803 * [dstReg<<dstScale + dstDisp] == (byte) srcReg
7804 * </PRE>
7805 *
7806 * @param dstIndex the destination index register
7807 * @param dstScale the destination shift amount
7808 * @param dstDisp the destination displacement
7809 * @param srcReg the source register
7810 */
7811 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7812 public final void emitCMP_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7813 int miStart = mi;
7814 // no group 1 to 4 prefix byte
7815 generateREXprefix(false, srcReg, dstIndex, null);
7816 // single byte opcode
7817 setMachineCodes(mi++, (byte) 0x38);
7818 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7819 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7820 }
7821
7822 /**
7823 * Generate a absolute--register CMP. That is,
7824 * <PRE>
7825 * [dstDisp] == (byte) srcReg
7826 * </PRE>
7827 *
7828 * @param dstDisp the destination address
7829 * @param srcReg the source register
7830 */
7831 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7832 public final void emitCMP_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
7833 int miStart = mi;
7834 // no group 1 to 4 prefix byte
7835 generateREXprefix(false, srcReg, null, null);
7836 // single byte opcode
7837 setMachineCodes(mi++, (byte) 0x38);
7838 emitAbsRegOperands(dstDisp, srcReg);
7839 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7840 }
7841
7842 /**
7843 * Generate a register-index--register CMP. That is,
7844 * <PRE>
7845 * [dstBase + dstIndex<<dstScale + dstDisp] == (byte) srcReg
7846 * </PRE>
7847 *
7848 * @param dstBase the base register
7849 * @param dstIndex the destination index register
7850 * @param dstScale the destination shift amount
7851 * @param dstDisp the destination displacement
7852 * @param srcReg the source register
7853 */
7854 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7855 public final void emitCMP_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7856 int miStart = mi;
7857 // no group 1 to 4 prefix byte
7858 generateREXprefix(false, srcReg, dstIndex, dstBase);
7859 // single byte opcode
7860 setMachineCodes(mi++, (byte) 0x38);
7861 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7862 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7863 }
7864
7865 /**
7866 * Generate a register-displacement--register CMP. That is,
7867 * <PRE>
7868 * [dstBase + dstDisp] == (byte) srcReg
7869 * </PRE>
7870 *
7871 * @param dstBase the base register
7872 * @param dstDisp the destination displacement
7873 * @param srcReg the source register
7874 */
7875 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7876 public final void emitCMP_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
7877 int miStart = mi;
7878 // no group 1 to 4 prefix byte
7879 generateREXprefix(false, srcReg, null, dstBase);
7880 // single byte opcode
7881 setMachineCodes(mi++, (byte) 0x38);
7882 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7883 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7884 }
7885
7886 /**
7887 * Generate a register--register CMP. That is,
7888 * <PRE>
7889 * dstReg == (byte) srcReg
7890 * </PRE>
7891 *
7892 * @param dstReg the destination register
7893 * @param srcReg the source register
7894 */
7895 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7896 public final void emitCMP_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
7897 int miStart = mi;
7898 // no group 1 to 4 prefix byte
7899 generateREXprefix(false, srcReg, null, dstReg);
7900 // single byte opcode
7901 setMachineCodes(mi++, (byte) 0x38);
7902 emitRegRegOperands(dstReg, srcReg);
7903 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7904 }
7905
7906 /**
7907 * Generate a register--register-displacement CMP. That is,
7908 * <PRE>
7909 * dstReg == (byte) [srcReg + srcDisp]
7910 * </PRE>
7911 *
7912 * @param dstReg the destination register
7913 * @param srcBase the source register
7914 * @param srcDisp the source displacement
7915 */
7916 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7917 public final void emitCMP_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
7918 int miStart = mi;
7919 // no group 1 to 4 prefix byte
7920 generateREXprefix(false, dstReg, null, srcBase);
7921 // single byte opcode
7922 setMachineCodes(mi++, (byte) 0x3A);
7923 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7924 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7925 }
7926
7927 /**
7928 * Generate a register--register-offset CMP. That is,
7929 * <PRE>
7930 * dstReg == (byte) [srcIndex<<srcScale + srcDisp]
7931 * </PRE>
7932 *
7933 * @param dstReg the destination register
7934 * @param srcIndex the source index register
7935 * @param srcScale the source shift amount
7936 * @param srcDisp the source displacement
7937 */
7938 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7939 public final void emitCMP_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7940 int miStart = mi;
7941 // no group 1 to 4 prefix byte
7942 generateREXprefix(false, dstReg, srcIndex, null);
7943 // single byte opcode
7944 setMachineCodes(mi++, (byte) 0x3A);
7945 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7946 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7947 }
7948
7949 /**
7950 * Generate a register--register-offset CMP. That is,
7951 * <PRE>
7952 * dstReg == (byte) [srcDisp]
7953 * </PRE>
7954 *
7955 * @param dstReg the destination register
7956 * @param srcDisp the source displacement
7957 */
7958 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7959 public final void emitCMP_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
7960 int miStart = mi;
7961 // no group 1 to 4 prefix byte
7962 generateREXprefix(false, dstReg, null, null);
7963 // single byte opcode
7964 setMachineCodes(mi++, (byte) 0x3A);
7965 emitAbsRegOperands(srcDisp, dstReg);
7966 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7967 }
7968
7969 /**
7970 * Generate a register--register-offset CMP. That is,
7971 * <PRE>
7972 * dstReg == (byte) [srcBase + srcIndex<<srcScale + srcDisp]
7973 * </PRE>
7974 *
7975 * @param dstReg the destination register
7976 * @param srcBase the source base register
7977 * @param srcIndex the source index register
7978 * @param srcScale the source shift amount
7979 * @param srcDisp the source displacement
7980 */
7981 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7982 public final void emitCMP_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7983 int miStart = mi;
7984 // no group 1 to 4 prefix byte
7985 generateREXprefix(false, dstReg, srcIndex, srcBase);
7986 // single byte opcode
7987 setMachineCodes(mi++, (byte) 0x3A);
7988 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7989 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7990 }
7991
7992 /**
7993 * Generate a register--register(indirect) CMP. That is,
7994 * <PRE>
7995 * dstReg == (byte) [srcBase]
7996 * </PRE>
7997 *
7998 * @param dstReg the destination register
7999 * @param srcBase the source base register
8000 */
8001 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8002 public final void emitCMP_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
8003 int miStart = mi;
8004 // no group 1 to 4 prefix byte
8005 generateREXprefix(false, dstReg, null, srcBase);
8006 // single byte opcode
8007 setMachineCodes(mi++, (byte) 0x3A);
8008 emitRegIndirectRegOperands(srcBase, dstReg);
8009 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
8010 }
8011
8012 /**
8013 * Generate a register--immediate CMP. That is,
8014 * <PRE>
8015 * dstReg == imm
8016 * </PRE>
8017 *
8018 * @param dstReg the destination register
8019 * @param imm immediate
8020 */
8021 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8022 public final void emitCMP_Reg_Imm(GPR dstReg, int imm) {
8023 int miStart = mi;
8024 // no group 1 to 4 prefix byte
8025 generateREXprefix(false, null, null, dstReg);
8026 // single byte opcode
8027 if (fits(imm,8)) {
8028 setMachineCodes(mi++, (byte) 0x83);
8029 // "register 0x7" is really part of the opcode
8030 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8031 emitImm8((byte)imm);
8032 } else if (dstReg == EAX) {
8033 setMachineCodes(mi++, (byte) 0x3D);
8034 emitImm32(imm);
8035 } else {
8036 setMachineCodes(mi++, (byte) 0x81);
8037 // "register 0x7" is really part of the opcode
8038 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8039 emitImm32(imm);
8040 }
8041 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8042 }
8043
8044 /**
8045 * Generate a register-displacement--immediate CMP. That is,
8046 * <PRE>
8047 * [dstBase + dstDisp] == imm
8048 * </PRE>
8049 *
8050 * @param dstBase the destination register
8051 * @param dstDisp the destination displacement
8052 * @param imm immediate
8053 */
8054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8055 public final void emitCMP_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
8056 int miStart = mi;
8057 // no group 1 to 4 prefix byte
8058 generateREXprefix(false, null, null, dstBase);
8059 // single byte opcode
8060 if (fits(imm,8)) {
8061 setMachineCodes(mi++, (byte) 0x83);
8062 // "register 0x7" is really part of the opcode
8063 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8064 emitImm8((byte)imm);
8065 } else {
8066 setMachineCodes(mi++, (byte) 0x81);
8067 // "register 0x7" is really part of the opcode
8068 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8069 emitImm32(imm);
8070 }
8071 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8072 }
8073
8074 /**
8075 * Generate a register-offset--immediate CMP. That is,
8076 * <PRE>
8077 * [dstIndex<<dstScale + dstDisp] == imm
8078 * </PRE>
8079 *
8080 * @param dstIndex the destination index register
8081 * @param dstScale the destination shift amount
8082 * @param dstDisp the destination displacement
8083 * @param imm immediate
8084 */
8085 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8086 public final void emitCMP_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8087 int miStart = mi;
8088 // no group 1 to 4 prefix byte
8089 generateREXprefix(false, null, dstIndex, null);
8090 // single byte opcode
8091 if (fits(imm,8)) {
8092 setMachineCodes(mi++, (byte) 0x83);
8093 // "register 0x7" is really part of the opcode
8094 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8095 emitImm8((byte)imm);
8096 } else {
8097 setMachineCodes(mi++, (byte) 0x81);
8098 // "register 0x7" is really part of the opcode
8099 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8100 emitImm32(imm);
8101 }
8102 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8103 }
8104
8105 /**
8106 * Generate a absolute--immediate CMP. That is,
8107 * <PRE>
8108 * [dstDisp] == imm
8109 * </PRE>
8110 *
8111 * @param dstDisp the destination displacement
8112 * @param imm immediate
8113 */
8114 public final void emitCMP_Abs_Imm(Address dstDisp, int imm) {
8115 int miStart = mi;
8116 // no group 1 to 4 prefix byte
8117 generateREXprefix(false, null, null, null);
8118 // single byte opcode
8119 if (fits(imm,8)) {
8120 setMachineCodes(mi++, (byte) 0x83);
8121 // "register 0x7" is really part of the opcode
8122 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8123 emitImm8((byte)imm);
8124 } else {
8125 setMachineCodes(mi++, (byte) 0x81);
8126 // "register 0x7" is really part of the opcode
8127 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8128 emitImm32(imm);
8129 }
8130 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8131 }
8132
8133 /**
8134 * Generate a register-index--immediate CMP. That is,
8135 * <PRE>
8136 * [dstBase + dstIndex<<dstScale + dstDisp] == imm
8137 * </PRE>
8138 *
8139 * @param dstBase the destination base register
8140 * @param dstIndex the destination index register
8141 * @param dstScale the destination shift amount
8142 * @param dstDisp the destination displacement
8143 * @param imm immediate
8144 */
8145 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8146 public final void emitCMP_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8147 int miStart = mi;
8148 // no group 1 to 4 prefix byte
8149 generateREXprefix(false, null, dstIndex, dstBase);
8150 // single byte opcode
8151 if (fits(imm,8)) {
8152 setMachineCodes(mi++, (byte) 0x83);
8153 // "register 0x7" is really part of the opcode
8154 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8155 emitImm8((byte)imm);
8156 } else {
8157 setMachineCodes(mi++, (byte) 0x81);
8158 // "register 0x7" is really part of the opcode
8159 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8160 emitImm32(imm);
8161 }
8162 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8163 }
8164
8165 /**
8166 * Generate a register(indirect)--immediate CMP. That is,
8167 * <PRE>
8168 * [dstBase] == imm
8169 * </PRE>
8170 *
8171 * @param dstBase the destination base register
8172 * @param imm immediate
8173 */
8174 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8175 public final void emitCMP_RegInd_Imm(GPR dstBase, int imm) {
8176 int miStart = mi;
8177 // no group 1 to 4 prefix byte
8178 generateREXprefix(false, null, null, dstBase);
8179 // single byte opcode
8180 if (fits(imm,8)) {
8181 setMachineCodes(mi++, (byte) 0x83);
8182 // "register 0x7" is really part of the opcode
8183 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8184 emitImm8((byte)imm);
8185 } else {
8186 setMachineCodes(mi++, (byte) 0x81);
8187 // "register 0x7" is really part of the opcode
8188 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8189 emitImm32(imm);
8190 }
8191 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8192 }
8193
8194 /**
8195 * Generate a register--immediate CMP. That is,
8196 * <PRE>
8197 * dstReg == (word) imm
8198 * </PRE>
8199 *
8200 * @param dstReg the destination register
8201 * @param imm immediate
8202 */
8203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8204 public final void emitCMP_Reg_Imm_Word(GPR dstReg, int imm) {
8205 int miStart = mi;
8206 setMachineCodes(mi++, (byte) 0x66);
8207 generateREXprefix(false, null, null, dstReg);
8208 // single byte opcode
8209 if (fits(imm,8)) {
8210 setMachineCodes(mi++, (byte) 0x83);
8211 // "register 0x7" is really part of the opcode
8212 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8213 emitImm8((byte)imm);
8214 } else if (dstReg == EAX) {
8215 setMachineCodes(mi++, (byte) 0x3D);
8216 emitImm16(imm);
8217 } else {
8218 setMachineCodes(mi++, (byte) 0x81);
8219 // "register 0x7" is really part of the opcode
8220 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8221 emitImm16(imm);
8222 }
8223 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8224 }
8225
8226 /**
8227 * Generate a register-displacement--immediate CMP. That is,
8228 * <PRE>
8229 * [dstBase + dstDisp] == (word) imm
8230 * </PRE>
8231 *
8232 * @param dstBase the destination register
8233 * @param dstDisp the destination displacement
8234 * @param imm immediate
8235 */
8236 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8237 public final void emitCMP_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
8238 int miStart = mi;
8239 setMachineCodes(mi++, (byte) 0x66);
8240 generateREXprefix(false, null, null, dstBase);
8241 // single byte opcode
8242 if (fits(imm,8)) {
8243 setMachineCodes(mi++, (byte) 0x83);
8244 // "register 0x7" is really part of the opcode
8245 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8246 emitImm8((byte)imm);
8247 } else {
8248 setMachineCodes(mi++, (byte) 0x81);
8249 // "register 0x7" is really part of the opcode
8250 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8251 emitImm16(imm);
8252 }
8253 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8254 }
8255
8256 /**
8257 * Generate a register-offset--immediate CMP. That is,
8258 * <PRE>
8259 * [dstIndex<<dstScale + dstDisp] == (word) imm
8260 * </PRE>
8261 *
8262 * @param dstIndex the destination index register
8263 * @param dstScale the destination shift amount
8264 * @param dstDisp the destination displacement
8265 * @param imm immediate
8266 */
8267 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8268 public final void emitCMP_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8269 int miStart = mi;
8270 setMachineCodes(mi++, (byte) 0x66);
8271 generateREXprefix(false, null, dstIndex, null);
8272 // single byte opcode
8273 if (fits(imm,8)) {
8274 setMachineCodes(mi++, (byte) 0x83);
8275 // "register 0x7" is really part of the opcode
8276 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8277 emitImm8((byte)imm);
8278 } else {
8279 setMachineCodes(mi++, (byte) 0x81);
8280 // "register 0x7" is really part of the opcode
8281 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8282 emitImm16(imm);
8283 }
8284 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8285 }
8286
8287 /**
8288 * Generate a absolute--immediate CMP. That is,
8289 * <PRE>
8290 * [dstDisp] == (word) imm
8291 * </PRE>
8292 *
8293 * @param dstDisp the destination displacement
8294 * @param imm immediate
8295 */
8296 public final void emitCMP_Abs_Imm_Word(Address dstDisp, int imm) {
8297 int miStart = mi;
8298 setMachineCodes(mi++, (byte) 0x66);
8299 generateREXprefix(false, null, null, null);
8300 // single byte opcode
8301 if (fits(imm,8)) {
8302 setMachineCodes(mi++, (byte) 0x83);
8303 // "register 0x7" is really part of the opcode
8304 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8305 emitImm8((byte)imm);
8306 } else {
8307 setMachineCodes(mi++, (byte) 0x81);
8308 // "register 0x7" is really part of the opcode
8309 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8310 emitImm16(imm);
8311 }
8312 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8313 }
8314
8315 /**
8316 * Generate a register-index--immediate CMP. That is,
8317 * <PRE>
8318 * [dstBase + dstIndex<<dstScale + dstDisp] == (word) imm
8319 * </PRE>
8320 *
8321 * @param dstBase the destination base register
8322 * @param dstIndex the destination index register
8323 * @param dstScale the destination shift amount
8324 * @param dstDisp the destination displacement
8325 * @param imm immediate
8326 */
8327 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8328 public final void emitCMP_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8329 int miStart = mi;
8330 setMachineCodes(mi++, (byte) 0x66);
8331 generateREXprefix(false, null, dstIndex, dstBase);
8332 // single byte opcode
8333 if (fits(imm,8)) {
8334 setMachineCodes(mi++, (byte) 0x83);
8335 // "register 0x7" is really part of the opcode
8336 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8337 emitImm8((byte)imm);
8338 } else {
8339 setMachineCodes(mi++, (byte) 0x81);
8340 // "register 0x7" is really part of the opcode
8341 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8342 emitImm16(imm);
8343 }
8344 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8345 }
8346
8347 /**
8348 * Generate a register(indirect)--immediate CMP. That is,
8349 * <PRE>
8350 * [dstBase] == (word) imm
8351 * </PRE>
8352 *
8353 * @param dstBase the destination base register
8354 * @param imm immediate
8355 */
8356 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8357 public final void emitCMP_RegInd_Imm_Word(GPR dstBase, int imm) {
8358 int miStart = mi;
8359 setMachineCodes(mi++, (byte) 0x66);
8360 generateREXprefix(false, null, null, dstBase);
8361 // single byte opcode
8362 if (fits(imm,8)) {
8363 setMachineCodes(mi++, (byte) 0x83);
8364 // "register 0x7" is really part of the opcode
8365 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8366 emitImm8((byte)imm);
8367 } else {
8368 setMachineCodes(mi++, (byte) 0x81);
8369 // "register 0x7" is really part of the opcode
8370 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8371 emitImm16(imm);
8372 }
8373 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8374 }
8375
8376 /**
8377 * Generate a register--immediate CMP. That is,
8378 * <PRE>
8379 * dstReg == (quad) imm
8380 * </PRE>
8381 *
8382 * @param dstReg the destination register
8383 * @param imm immediate
8384 */
8385 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8386 public final void emitCMP_Reg_Imm_Quad(GPR dstReg, int imm) {
8387 int miStart = mi;
8388 // no group 1 to 4 prefix byte
8389 generateREXprefix(true, null, null, dstReg);
8390 // single byte opcode
8391 if (fits(imm,8)) {
8392 setMachineCodes(mi++, (byte) 0x83);
8393 // "register 0x7" is really part of the opcode
8394 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8395 emitImm8((byte)imm);
8396 } else if (dstReg == EAX) {
8397 setMachineCodes(mi++, (byte) 0x3D);
8398 emitImm32(imm);
8399 } else {
8400 setMachineCodes(mi++, (byte) 0x81);
8401 // "register 0x7" is really part of the opcode
8402 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8403 emitImm32(imm);
8404 }
8405 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8406 }
8407
8408 /**
8409 * Generate a register-displacement--immediate CMP. That is,
8410 * <PRE>
8411 * [dstBase + dstDisp] == (quad) imm
8412 * </PRE>
8413 *
8414 * @param dstBase the destination register
8415 * @param dstDisp the destination displacement
8416 * @param imm immediate
8417 */
8418 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8419 public final void emitCMP_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
8420 int miStart = mi;
8421 // no group 1 to 4 prefix byte
8422 generateREXprefix(true, null, null, dstBase);
8423 // single byte opcode
8424 if (fits(imm,8)) {
8425 setMachineCodes(mi++, (byte) 0x83);
8426 // "register 0x7" is really part of the opcode
8427 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8428 emitImm8((byte)imm);
8429 } else {
8430 setMachineCodes(mi++, (byte) 0x81);
8431 // "register 0x7" is really part of the opcode
8432 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8433 emitImm32(imm);
8434 }
8435 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8436 }
8437
8438 /**
8439 * Generate a register-offset--immediate CMP. That is,
8440 * <PRE>
8441 * [dstIndex<<dstScale + dstDisp] == (quad) imm
8442 * </PRE>
8443 *
8444 * @param dstIndex the destination index register
8445 * @param dstScale the destination shift amount
8446 * @param dstDisp the destination displacement
8447 * @param imm immediate
8448 */
8449 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8450 public final void emitCMP_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8451 int miStart = mi;
8452 // no group 1 to 4 prefix byte
8453 generateREXprefix(true, null, dstIndex, null);
8454 // single byte opcode
8455 if (fits(imm,8)) {
8456 setMachineCodes(mi++, (byte) 0x83);
8457 // "register 0x7" is really part of the opcode
8458 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8459 emitImm8((byte)imm);
8460 } else {
8461 setMachineCodes(mi++, (byte) 0x81);
8462 // "register 0x7" is really part of the opcode
8463 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8464 emitImm32(imm);
8465 }
8466 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8467 }
8468
8469 /**
8470 * Generate a absolute--immediate CMP. That is,
8471 * <PRE>
8472 * [dstDisp] == (quad) imm
8473 * </PRE>
8474 *
8475 * @param dstDisp the destination displacement
8476 * @param imm immediate
8477 */
8478 public final void emitCMP_Abs_Imm_Quad(Address dstDisp, int imm) {
8479 int miStart = mi;
8480 // no group 1 to 4 prefix byte
8481 generateREXprefix(true, null, null, null);
8482 // single byte opcode
8483 if (fits(imm,8)) {
8484 setMachineCodes(mi++, (byte) 0x83);
8485 // "register 0x7" is really part of the opcode
8486 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8487 emitImm8((byte)imm);
8488 } else {
8489 setMachineCodes(mi++, (byte) 0x81);
8490 // "register 0x7" is really part of the opcode
8491 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8492 emitImm32(imm);
8493 }
8494 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8495 }
8496
8497 /**
8498 * Generate a register-index--immediate CMP. That is,
8499 * <PRE>
8500 * [dstBase + dstIndex<<dstScale + dstDisp] == (quad) imm
8501 * </PRE>
8502 *
8503 * @param dstBase the destination base register
8504 * @param dstIndex the destination index register
8505 * @param dstScale the destination shift amount
8506 * @param dstDisp the destination displacement
8507 * @param imm immediate
8508 */
8509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8510 public final void emitCMP_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8511 int miStart = mi;
8512 // no group 1 to 4 prefix byte
8513 generateREXprefix(true, null, dstIndex, dstBase);
8514 // single byte opcode
8515 if (fits(imm,8)) {
8516 setMachineCodes(mi++, (byte) 0x83);
8517 // "register 0x7" is really part of the opcode
8518 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8519 emitImm8((byte)imm);
8520 } else {
8521 setMachineCodes(mi++, (byte) 0x81);
8522 // "register 0x7" is really part of the opcode
8523 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8524 emitImm32(imm);
8525 }
8526 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8527 }
8528
8529 /**
8530 * Generate a register(indirect)--immediate CMP. That is,
8531 * <PRE>
8532 * [dstBase] == (quad) imm
8533 * </PRE>
8534 *
8535 * @param dstBase the destination base register
8536 * @param imm immediate
8537 */
8538 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8539 public final void emitCMP_RegInd_Imm_Quad(GPR dstBase, int imm) {
8540 int miStart = mi;
8541 // no group 1 to 4 prefix byte
8542 generateREXprefix(true, null, null, dstBase);
8543 // single byte opcode
8544 if (fits(imm,8)) {
8545 setMachineCodes(mi++, (byte) 0x83);
8546 // "register 0x7" is really part of the opcode
8547 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8548 emitImm8((byte)imm);
8549 } else {
8550 setMachineCodes(mi++, (byte) 0x81);
8551 // "register 0x7" is really part of the opcode
8552 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8553 emitImm32(imm);
8554 }
8555 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8556 }
8557
8558 /**
8559 * Generate a register--immediate CMP. That is,
8560 * <PRE>
8561 * dstReg == (byte) imm
8562 * </PRE>
8563 *
8564 * @param dstReg the destination register
8565 * @param imm immediate
8566 */
8567 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8568 public final void emitCMP_Reg_Imm_Byte(GPR dstReg, int imm) {
8569 int miStart = mi;
8570 if (dstReg == EAX) {
8571 setMachineCodes(mi++, (byte) 0x3C);
8572 emitImm8(imm);
8573 } else {
8574 generateREXprefix(false, null, null, dstReg);
8575 setMachineCodes(mi++, (byte) 0x80);
8576 // "register 0x7" is really part of the opcode
8577 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8578 emitImm8(imm);
8579 }
8580 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8581 }
8582
8583 /**
8584 * Generate a register-displacement--immediate CMP. That is,
8585 * <PRE>
8586 * [dstBase + dstDisp] == (byte) imm
8587 * </PRE>
8588 *
8589 * @param dstBase the destination register
8590 * @param dstDisp the destination displacement
8591 * @param imm immediate
8592 */
8593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8594 public final void emitCMP_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
8595 int miStart = mi;
8596 generateREXprefix(false, null, null, dstBase);
8597 setMachineCodes(mi++, (byte) 0x80);
8598 // "register 0x7" is really part of the opcode
8599 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8600 emitImm8(imm);
8601 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8602 }
8603
8604 /**
8605 * Generate a register-index--immediate CMP. That is,
8606 * <PRE>
8607 * [dstBase + dstIndex<<scale + dstDisp] == (byte) imm
8608 * </PRE>
8609 *
8610 * @param dstBase the destination base register
8611 * @param dstIndex the destination index register
8612 * @param dstScale the destination shift amount
8613 * @param dstDisp the destination displacement
8614 * @param imm immediate
8615 */
8616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8617 public final void emitCMP_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8618 int miStart = mi;
8619 generateREXprefix(false, null, dstIndex, dstBase);
8620 setMachineCodes(mi++, (byte) 0x80);
8621 // "register 0x7" is really part of the opcode
8622 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8623 emitImm8(imm);
8624 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8625 }
8626
8627 /**
8628 * Generate a register-offset--immediate CMP. That is,
8629 * <PRE>
8630 * [dstIndex<<dstScale + dstDisp] == (byte) imm
8631 * </PRE>
8632 *
8633 * @param dstIndex the destination index register
8634 * @param dstScale the destination shift amount
8635 * @param dstDisp the destination displacement
8636 * @param imm immediate
8637 */
8638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8639 public final void emitCMP_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8640 int miStart = mi;
8641 generateREXprefix(false, null, dstIndex, null);
8642 setMachineCodes(mi++, (byte) 0x80);
8643 // "register 0x7" is really part of the opcode
8644 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8645 emitImm8(imm);
8646 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8647 }
8648
8649 /**
8650 * Generate a absolute--immediate CMP. That is,
8651 * <PRE>
8652 * [dstDisp] == (byte) imm
8653 * </PRE>
8654 *
8655 * @param dstDisp the destination displacement
8656 * @param imm immediate
8657 */
8658 public final void emitCMP_Abs_Imm_Byte(Address dstDisp, int imm) {
8659 int miStart = mi;
8660 generateREXprefix(false, null, null, null);
8661 setMachineCodes(mi++, (byte) 0x80);
8662 // "register 0x7" is really part of the opcode
8663 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8664 emitImm8(imm);
8665 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8666 }
8667
8668 /**
8669 * Generate a register(indirect)--immediate CMP. That is,
8670 * <PRE>
8671 * [dstBase] == (byte) imm
8672 * </PRE>
8673 *
8674 * @param dstBase the destination base register
8675 * @param imm immediate
8676 */
8677 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8678 public final void emitCMP_RegInd_Imm_Byte(GPR dstBase, int imm) {
8679 int miStart = mi;
8680 generateREXprefix(false, null, null, dstBase);
8681 setMachineCodes(mi++, (byte) 0x80);
8682 // "register 0x7" is really part of the opcode
8683 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8684 emitImm8(imm);
8685 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8686 }
8687
8688 /**
8689 * Generate a register(indirect)--register OR. That is,
8690 * <PRE>
8691 * [dstBase] |= srcReg
8692 * </PRE>
8693 *
8694 * @param dstBase the destination base
8695 * @param srcReg the source register
8696 */
8697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8698 public final void emitOR_RegInd_Reg(GPR dstBase, GPR srcReg) {
8699 int miStart = mi;
8700 // no group 1 to 4 prefix byte
8701 generateREXprefix(false, srcReg, null, dstBase);
8702 // single byte opcode
8703 setMachineCodes(mi++, (byte) 0x09);
8704 emitRegIndirectRegOperands(dstBase, srcReg);
8705 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
8706 }
8707
8708 /**
8709 * Generate a register-offset--register OR. That is,
8710 * <PRE>
8711 * [dstReg<<dstScale + dstDisp] |= srcReg
8712 * </PRE>
8713 *
8714 * @param dstIndex the destination index register
8715 * @param dstScale the destination shift amount
8716 * @param dstDisp the destination displacement
8717 * @param srcReg the source register
8718 */
8719 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
8720 public final void emitOR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8721 int miStart = mi;
8722 // no group 1 to 4 prefix byte
8723 generateREXprefix(false, srcReg, dstIndex, null);
8724 // single byte opcode
8725 setMachineCodes(mi++, (byte) 0x09);
8726 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
8727 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
8728 }
8729
8730 /**
8731 * Generate a absolute--register OR. That is,
8732 * <PRE>
8733 * [dstDisp] |= srcReg
8734 * </PRE>
8735 *
8736 * @param dstDisp the destination address
8737 * @param srcReg the source register
8738 */
8739 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
8740 public final void emitOR_Abs_Reg(Address dstDisp, GPR srcReg) {
8741 int miStart = mi;
8742 // no group 1 to 4 prefix byte
8743 generateREXprefix(false, srcReg, null, null);
8744 // single byte opcode
8745 setMachineCodes(mi++, (byte) 0x09);
8746 emitAbsRegOperands(dstDisp, srcReg);
8747 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
8748 }
8749
8750 /**
8751 * Generate a register-index--register OR. That is,
8752 * <PRE>
8753 * [dstBase + dstIndex<<dstScale + dstDisp] |= srcReg
8754 * </PRE>
8755 *
8756 * @param dstBase the base register
8757 * @param dstIndex the destination index register
8758 * @param dstScale the destination shift amount
8759 * @param dstDisp the destination displacement
8760 * @param srcReg the source register
8761 */
8762 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
8763 public final void emitOR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8764 int miStart = mi;
8765 // no group 1 to 4 prefix byte
8766 generateREXprefix(false, srcReg, dstIndex, dstBase);
8767 // single byte opcode
8768 setMachineCodes(mi++, (byte) 0x09);
8769 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
8770 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
8771 }
8772
8773 /**
8774 * Generate a register-displacement--register OR. That is,
8775 * <PRE>
8776 * [dstBase + dstDisp] |= srcReg
8777 * </PRE>
8778 *
8779 * @param dstBase the base register
8780 * @param dstDisp the destination displacement
8781 * @param srcReg the source register
8782 */
8783 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
8784 public final void emitOR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
8785 int miStart = mi;
8786 // no group 1 to 4 prefix byte
8787 generateREXprefix(false, srcReg, null, dstBase);
8788 // single byte opcode
8789 setMachineCodes(mi++, (byte) 0x09);
8790 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
8791 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
8792 }
8793
8794 /**
8795 * Generate a register--register OR. That is,
8796 * <PRE>
8797 * dstReg |= srcReg
8798 * </PRE>
8799 *
8800 * @param dstReg the destination register
8801 * @param srcReg the source register
8802 */
8803 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8804 public final void emitOR_Reg_Reg(GPR dstReg, GPR srcReg) {
8805 int miStart = mi;
8806 // no group 1 to 4 prefix byte
8807 generateREXprefix(false, srcReg, null, dstReg);
8808 // single byte opcode
8809 setMachineCodes(mi++, (byte) 0x09);
8810 emitRegRegOperands(dstReg, srcReg);
8811 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
8812 }
8813
8814 /**
8815 * Generate a register--register-displacement OR. That is,
8816 * <PRE>
8817 * dstReg |= [srcReg + srcDisp]
8818 * </PRE>
8819 *
8820 * @param dstReg the destination register
8821 * @param srcBase the source register
8822 * @param srcDisp the source displacement
8823 */
8824 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8825 public final void emitOR_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
8826 int miStart = mi;
8827 // no group 1 to 4 prefix byte
8828 generateREXprefix(false, dstReg, null, srcBase);
8829 // single byte opcode
8830 setMachineCodes(mi++, (byte) 0x0B);
8831 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
8832 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
8833 }
8834
8835 /**
8836 * Generate a register--register-offset OR. That is,
8837 * <PRE>
8838 * dstReg |= [srcIndex<<srcScale + srcDisp]
8839 * </PRE>
8840 *
8841 * @param dstReg the destination register
8842 * @param srcIndex the source index register
8843 * @param srcScale the source shift amount
8844 * @param srcDisp the source displacement
8845 */
8846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8847 public final void emitOR_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
8848 int miStart = mi;
8849 // no group 1 to 4 prefix byte
8850 generateREXprefix(false, dstReg, srcIndex, null);
8851 // single byte opcode
8852 setMachineCodes(mi++, (byte) 0x0B);
8853 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
8854 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
8855 }
8856
8857 /**
8858 * Generate a register--register-offset OR. That is,
8859 * <PRE>
8860 * dstReg |= [srcDisp]
8861 * </PRE>
8862 *
8863 * @param dstReg the destination register
8864 * @param srcDisp the source displacement
8865 */
8866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8867 public final void emitOR_Reg_Abs(GPR dstReg, Address srcDisp) {
8868 int miStart = mi;
8869 // no group 1 to 4 prefix byte
8870 generateREXprefix(false, dstReg, null, null);
8871 // single byte opcode
8872 setMachineCodes(mi++, (byte) 0x0B);
8873 emitAbsRegOperands(srcDisp, dstReg);
8874 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
8875 }
8876
8877 /**
8878 * Generate a register--register-offset OR. That is,
8879 * <PRE>
8880 * dstReg |= [srcBase + srcIndex<<srcScale + srcDisp]
8881 * </PRE>
8882 *
8883 * @param dstReg the destination register
8884 * @param srcBase the source base register
8885 * @param srcIndex the source index register
8886 * @param srcScale the source shift amount
8887 * @param srcDisp the source displacement
8888 */
8889 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
8890 public final void emitOR_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
8891 int miStart = mi;
8892 // no group 1 to 4 prefix byte
8893 generateREXprefix(false, dstReg, srcIndex, srcBase);
8894 // single byte opcode
8895 setMachineCodes(mi++, (byte) 0x0B);
8896 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
8897 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
8898 }
8899
8900 /**
8901 * Generate a register--register(indirect) OR. That is,
8902 * <PRE>
8903 * dstReg |= [srcBase]
8904 * </PRE>
8905 *
8906 * @param dstReg the destination register
8907 * @param srcBase the source base register
8908 */
8909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8910 public final void emitOR_Reg_RegInd(GPR dstReg, GPR srcBase) {
8911 int miStart = mi;
8912 // no group 1 to 4 prefix byte
8913 generateREXprefix(false, dstReg, null, srcBase);
8914 // single byte opcode
8915 setMachineCodes(mi++, (byte) 0x0B);
8916 emitRegIndirectRegOperands(srcBase, dstReg);
8917 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
8918 }
8919
8920 /**
8921 * Generate a register(indirect)--register OR. That is,
8922 * <PRE>
8923 * [dstBase] |= (word) srcReg
8924 * </PRE>
8925 *
8926 * @param dstBase the destination base
8927 * @param srcReg the source register
8928 */
8929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8930 public final void emitOR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
8931 int miStart = mi;
8932 setMachineCodes(mi++, (byte) 0x66);
8933 generateREXprefix(false, srcReg, null, dstBase);
8934 // single byte opcode
8935 setMachineCodes(mi++, (byte) 0x09);
8936 emitRegIndirectRegOperands(dstBase, srcReg);
8937 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
8938 }
8939
8940 /**
8941 * Generate a register-offset--register OR. That is,
8942 * <PRE>
8943 * [dstReg<<dstScale + dstDisp] |= (word) srcReg
8944 * </PRE>
8945 *
8946 * @param dstIndex the destination index register
8947 * @param dstScale the destination shift amount
8948 * @param dstDisp the destination displacement
8949 * @param srcReg the source register
8950 */
8951 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
8952 public final void emitOR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8953 int miStart = mi;
8954 setMachineCodes(mi++, (byte) 0x66);
8955 generateREXprefix(false, srcReg, dstIndex, null);
8956 // single byte opcode
8957 setMachineCodes(mi++, (byte) 0x09);
8958 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
8959 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
8960 }
8961
8962 /**
8963 * Generate a absolute--register OR. That is,
8964 * <PRE>
8965 * [dstDisp] |= (word) srcReg
8966 * </PRE>
8967 *
8968 * @param dstDisp the destination address
8969 * @param srcReg the source register
8970 */
8971 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
8972 public final void emitOR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
8973 int miStart = mi;
8974 setMachineCodes(mi++, (byte) 0x66);
8975 generateREXprefix(false, srcReg, null, null);
8976 // single byte opcode
8977 setMachineCodes(mi++, (byte) 0x09);
8978 emitAbsRegOperands(dstDisp, srcReg);
8979 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
8980 }
8981
8982 /**
8983 * Generate a register-index--register OR. That is,
8984 * <PRE>
8985 * [dstBase + dstIndex<<dstScale + dstDisp] |= (word) srcReg
8986 * </PRE>
8987 *
8988 * @param dstBase the base register
8989 * @param dstIndex the destination index register
8990 * @param dstScale the destination shift amount
8991 * @param dstDisp the destination displacement
8992 * @param srcReg the source register
8993 */
8994 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
8995 public final void emitOR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8996 int miStart = mi;
8997 setMachineCodes(mi++, (byte) 0x66);
8998 generateREXprefix(false, srcReg, dstIndex, dstBase);
8999 // single byte opcode
9000 setMachineCodes(mi++, (byte) 0x09);
9001 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9002 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9003 }
9004
9005 /**
9006 * Generate a register-displacement--register OR. That is,
9007 * <PRE>
9008 * [dstBase + dstDisp] |= (word) srcReg
9009 * </PRE>
9010 *
9011 * @param dstBase the base register
9012 * @param dstDisp the destination displacement
9013 * @param srcReg the source register
9014 */
9015 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9016 public final void emitOR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
9017 int miStart = mi;
9018 setMachineCodes(mi++, (byte) 0x66);
9019 generateREXprefix(false, srcReg, null, dstBase);
9020 // single byte opcode
9021 setMachineCodes(mi++, (byte) 0x09);
9022 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9023 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9024 }
9025
9026 /**
9027 * Generate a register--register OR. That is,
9028 * <PRE>
9029 * dstReg |= (word) srcReg
9030 * </PRE>
9031 *
9032 * @param dstReg the destination register
9033 * @param srcReg the source register
9034 */
9035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9036 public final void emitOR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
9037 int miStart = mi;
9038 setMachineCodes(mi++, (byte) 0x66);
9039 generateREXprefix(false, srcReg, null, dstReg);
9040 // single byte opcode
9041 setMachineCodes(mi++, (byte) 0x09);
9042 emitRegRegOperands(dstReg, srcReg);
9043 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9044 }
9045
9046 /**
9047 * Generate a register--register-displacement OR. That is,
9048 * <PRE>
9049 * dstReg |= (word) [srcReg + srcDisp]
9050 * </PRE>
9051 *
9052 * @param dstReg the destination register
9053 * @param srcBase the source register
9054 * @param srcDisp the source displacement
9055 */
9056 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9057 public final void emitOR_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
9058 int miStart = mi;
9059 setMachineCodes(mi++, (byte) 0x66);
9060 generateREXprefix(false, dstReg, null, srcBase);
9061 // single byte opcode
9062 setMachineCodes(mi++, (byte) 0x0B);
9063 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9064 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9065 }
9066
9067 /**
9068 * Generate a register--register-offset OR. That is,
9069 * <PRE>
9070 * dstReg |= (word) [srcIndex<<srcScale + srcDisp]
9071 * </PRE>
9072 *
9073 * @param dstReg the destination register
9074 * @param srcIndex the source index register
9075 * @param srcScale the source shift amount
9076 * @param srcDisp the source displacement
9077 */
9078 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9079 public final void emitOR_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9080 int miStart = mi;
9081 setMachineCodes(mi++, (byte) 0x66);
9082 generateREXprefix(false, dstReg, srcIndex, null);
9083 // single byte opcode
9084 setMachineCodes(mi++, (byte) 0x0B);
9085 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9086 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9087 }
9088
9089 /**
9090 * Generate a register--register-offset OR. That is,
9091 * <PRE>
9092 * dstReg |= (word) [srcDisp]
9093 * </PRE>
9094 *
9095 * @param dstReg the destination register
9096 * @param srcDisp the source displacement
9097 */
9098 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9099 public final void emitOR_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
9100 int miStart = mi;
9101 setMachineCodes(mi++, (byte) 0x66);
9102 generateREXprefix(false, dstReg, null, null);
9103 // single byte opcode
9104 setMachineCodes(mi++, (byte) 0x0B);
9105 emitAbsRegOperands(srcDisp, dstReg);
9106 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9107 }
9108
9109 /**
9110 * Generate a register--register-offset OR. That is,
9111 * <PRE>
9112 * dstReg |= (word) [srcBase + srcIndex<<srcScale + srcDisp]
9113 * </PRE>
9114 *
9115 * @param dstReg the destination register
9116 * @param srcBase the source base register
9117 * @param srcIndex the source index register
9118 * @param srcScale the source shift amount
9119 * @param srcDisp the source displacement
9120 */
9121 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9122 public final void emitOR_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9123 int miStart = mi;
9124 setMachineCodes(mi++, (byte) 0x66);
9125 generateREXprefix(false, dstReg, srcIndex, srcBase);
9126 // single byte opcode
9127 setMachineCodes(mi++, (byte) 0x0B);
9128 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9129 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9130 }
9131
9132 /**
9133 * Generate a register--register(indirect) OR. That is,
9134 * <PRE>
9135 * dstReg |= (word) [srcBase]
9136 * </PRE>
9137 *
9138 * @param dstReg the destination register
9139 * @param srcBase the source base register
9140 */
9141 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9142 public final void emitOR_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
9143 int miStart = mi;
9144 setMachineCodes(mi++, (byte) 0x66);
9145 generateREXprefix(false, dstReg, null, srcBase);
9146 // single byte opcode
9147 setMachineCodes(mi++, (byte) 0x0B);
9148 emitRegIndirectRegOperands(srcBase, dstReg);
9149 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9150 }
9151
9152 /**
9153 * Generate a register(indirect)--register OR. That is,
9154 * <PRE>
9155 * [dstBase] |= (quad) srcReg
9156 * </PRE>
9157 *
9158 * @param dstBase the destination base
9159 * @param srcReg the source register
9160 */
9161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9162 public final void emitOR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
9163 int miStart = mi;
9164 // no group 1 to 4 prefix byte
9165 generateREXprefix(true, srcReg, null, dstBase);
9166 // single byte opcode
9167 setMachineCodes(mi++, (byte) 0x09);
9168 emitRegIndirectRegOperands(dstBase, srcReg);
9169 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
9170 }
9171
9172 /**
9173 * Generate a register-offset--register OR. That is,
9174 * <PRE>
9175 * [dstReg<<dstScale + dstDisp] |= (quad) srcReg
9176 * </PRE>
9177 *
9178 * @param dstIndex the destination index register
9179 * @param dstScale the destination shift amount
9180 * @param dstDisp the destination displacement
9181 * @param srcReg the source register
9182 */
9183 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
9184 public final void emitOR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9185 int miStart = mi;
9186 // no group 1 to 4 prefix byte
9187 generateREXprefix(true, srcReg, dstIndex, null);
9188 // single byte opcode
9189 setMachineCodes(mi++, (byte) 0x09);
9190 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
9191 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
9192 }
9193
9194 /**
9195 * Generate a absolute--register OR. That is,
9196 * <PRE>
9197 * [dstDisp] |= (quad) srcReg
9198 * </PRE>
9199 *
9200 * @param dstDisp the destination address
9201 * @param srcReg the source register
9202 */
9203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
9204 public final void emitOR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
9205 int miStart = mi;
9206 // no group 1 to 4 prefix byte
9207 generateREXprefix(true, srcReg, null, null);
9208 // single byte opcode
9209 setMachineCodes(mi++, (byte) 0x09);
9210 emitAbsRegOperands(dstDisp, srcReg);
9211 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
9212 }
9213
9214 /**
9215 * Generate a register-index--register OR. That is,
9216 * <PRE>
9217 * [dstBase + dstIndex<<dstScale + dstDisp] |= (quad) srcReg
9218 * </PRE>
9219 *
9220 * @param dstBase the base register
9221 * @param dstIndex the destination index register
9222 * @param dstScale the destination shift amount
9223 * @param dstDisp the destination displacement
9224 * @param srcReg the source register
9225 */
9226 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
9227 public final void emitOR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9228 int miStart = mi;
9229 // no group 1 to 4 prefix byte
9230 generateREXprefix(true, srcReg, dstIndex, dstBase);
9231 // single byte opcode
9232 setMachineCodes(mi++, (byte) 0x09);
9233 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9234 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9235 }
9236
9237 /**
9238 * Generate a register-displacement--register OR. That is,
9239 * <PRE>
9240 * [dstBase + dstDisp] |= (quad) srcReg
9241 * </PRE>
9242 *
9243 * @param dstBase the base register
9244 * @param dstDisp the destination displacement
9245 * @param srcReg the source register
9246 */
9247 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9248 public final void emitOR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
9249 int miStart = mi;
9250 // no group 1 to 4 prefix byte
9251 generateREXprefix(true, srcReg, null, dstBase);
9252 // single byte opcode
9253 setMachineCodes(mi++, (byte) 0x09);
9254 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9255 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9256 }
9257
9258 /**
9259 * Generate a register--register OR. That is,
9260 * <PRE>
9261 * dstReg |= (quad) srcReg
9262 * </PRE>
9263 *
9264 * @param dstReg the destination register
9265 * @param srcReg the source register
9266 */
9267 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9268 public final void emitOR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
9269 int miStart = mi;
9270 // no group 1 to 4 prefix byte
9271 generateREXprefix(true, srcReg, null, dstReg);
9272 // single byte opcode
9273 setMachineCodes(mi++, (byte) 0x09);
9274 emitRegRegOperands(dstReg, srcReg);
9275 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9276 }
9277
9278 /**
9279 * Generate a register--register-displacement OR. That is,
9280 * <PRE>
9281 * dstReg |= (quad) [srcReg + srcDisp]
9282 * </PRE>
9283 *
9284 * @param dstReg the destination register
9285 * @param srcBase the source register
9286 * @param srcDisp the source displacement
9287 */
9288 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9289 public final void emitOR_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
9290 int miStart = mi;
9291 // no group 1 to 4 prefix byte
9292 generateREXprefix(true, dstReg, null, srcBase);
9293 // single byte opcode
9294 setMachineCodes(mi++, (byte) 0x0B);
9295 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9296 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9297 }
9298
9299 /**
9300 * Generate a register--register-offset OR. That is,
9301 * <PRE>
9302 * dstReg |= (quad) [srcIndex<<srcScale + srcDisp]
9303 * </PRE>
9304 *
9305 * @param dstReg the destination register
9306 * @param srcIndex the source index register
9307 * @param srcScale the source shift amount
9308 * @param srcDisp the source displacement
9309 */
9310 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9311 public final void emitOR_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9312 int miStart = mi;
9313 // no group 1 to 4 prefix byte
9314 generateREXprefix(true, dstReg, srcIndex, null);
9315 // single byte opcode
9316 setMachineCodes(mi++, (byte) 0x0B);
9317 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9318 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9319 }
9320
9321 /**
9322 * Generate a register--register-offset OR. That is,
9323 * <PRE>
9324 * dstReg |= (quad) [srcDisp]
9325 * </PRE>
9326 *
9327 * @param dstReg the destination register
9328 * @param srcDisp the source displacement
9329 */
9330 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9331 public final void emitOR_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
9332 int miStart = mi;
9333 // no group 1 to 4 prefix byte
9334 generateREXprefix(true, dstReg, null, null);
9335 // single byte opcode
9336 setMachineCodes(mi++, (byte) 0x0B);
9337 emitAbsRegOperands(srcDisp, dstReg);
9338 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9339 }
9340
9341 /**
9342 * Generate a register--register-offset OR. That is,
9343 * <PRE>
9344 * dstReg |= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
9345 * </PRE>
9346 *
9347 * @param dstReg the destination register
9348 * @param srcBase the source base register
9349 * @param srcIndex the source index register
9350 * @param srcScale the source shift amount
9351 * @param srcDisp the source displacement
9352 */
9353 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9354 public final void emitOR_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9355 int miStart = mi;
9356 // no group 1 to 4 prefix byte
9357 generateREXprefix(true, dstReg, srcIndex, srcBase);
9358 // single byte opcode
9359 setMachineCodes(mi++, (byte) 0x0B);
9360 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9361 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9362 }
9363
9364 /**
9365 * Generate a register--register(indirect) OR. That is,
9366 * <PRE>
9367 * dstReg |= (quad) [srcBase]
9368 * </PRE>
9369 *
9370 * @param dstReg the destination register
9371 * @param srcBase the source base register
9372 */
9373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9374 public final void emitOR_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
9375 int miStart = mi;
9376 // no group 1 to 4 prefix byte
9377 generateREXprefix(true, dstReg, null, srcBase);
9378 // single byte opcode
9379 setMachineCodes(mi++, (byte) 0x0B);
9380 emitRegIndirectRegOperands(srcBase, dstReg);
9381 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9382 }
9383
9384 /**
9385 * Generate a register(indirect)--register OR. That is,
9386 * <PRE>
9387 * [dstBase] |= (byte) srcReg
9388 * </PRE>
9389 *
9390 * @param dstBase the destination base
9391 * @param srcReg the source register
9392 */
9393 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9394 public final void emitOR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
9395 int miStart = mi;
9396 // no group 1 to 4 prefix byte
9397 generateREXprefix(false, srcReg, null, dstBase);
9398 // single byte opcode
9399 setMachineCodes(mi++, (byte) 0x08);
9400 emitRegIndirectRegOperands(dstBase, srcReg);
9401 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
9402 }
9403
9404 /**
9405 * Generate a register-offset--register OR. That is,
9406 * <PRE>
9407 * [dstReg<<dstScale + dstDisp] |= (byte) srcReg
9408 * </PRE>
9409 *
9410 * @param dstIndex the destination index register
9411 * @param dstScale the destination shift amount
9412 * @param dstDisp the destination displacement
9413 * @param srcReg the source register
9414 */
9415 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
9416 public final void emitOR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9417 int miStart = mi;
9418 // no group 1 to 4 prefix byte
9419 generateREXprefix(false, srcReg, dstIndex, null);
9420 // single byte opcode
9421 setMachineCodes(mi++, (byte) 0x08);
9422 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
9423 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
9424 }
9425
9426 /**
9427 * Generate a absolute--register OR. That is,
9428 * <PRE>
9429 * [dstDisp] |= (byte) srcReg
9430 * </PRE>
9431 *
9432 * @param dstDisp the destination address
9433 * @param srcReg the source register
9434 */
9435 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
9436 public final void emitOR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
9437 int miStart = mi;
9438 // no group 1 to 4 prefix byte
9439 generateREXprefix(false, srcReg, null, null);
9440 // single byte opcode
9441 setMachineCodes(mi++, (byte) 0x08);
9442 emitAbsRegOperands(dstDisp, srcReg);
9443 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
9444 }
9445
9446 /**
9447 * Generate a register-index--register OR. That is,
9448 * <PRE>
9449 * [dstBase + dstIndex<<dstScale + dstDisp] |= (byte) srcReg
9450 * </PRE>
9451 *
9452 * @param dstBase the base register
9453 * @param dstIndex the destination index register
9454 * @param dstScale the destination shift amount
9455 * @param dstDisp the destination displacement
9456 * @param srcReg the source register
9457 */
9458 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
9459 public final void emitOR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9460 int miStart = mi;
9461 // no group 1 to 4 prefix byte
9462 generateREXprefix(false, srcReg, dstIndex, dstBase);
9463 // single byte opcode
9464 setMachineCodes(mi++, (byte) 0x08);
9465 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9466 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9467 }
9468
9469 /**
9470 * Generate a register-displacement--register OR. That is,
9471 * <PRE>
9472 * [dstBase + dstDisp] |= (byte) srcReg
9473 * </PRE>
9474 *
9475 * @param dstBase the base register
9476 * @param dstDisp the destination displacement
9477 * @param srcReg the source register
9478 */
9479 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9480 public final void emitOR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
9481 int miStart = mi;
9482 // no group 1 to 4 prefix byte
9483 generateREXprefix(false, srcReg, null, dstBase);
9484 // single byte opcode
9485 setMachineCodes(mi++, (byte) 0x08);
9486 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9487 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9488 }
9489
9490 /**
9491 * Generate a register--register OR. That is,
9492 * <PRE>
9493 * dstReg |= (byte) srcReg
9494 * </PRE>
9495 *
9496 * @param dstReg the destination register
9497 * @param srcReg the source register
9498 */
9499 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9500 public final void emitOR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
9501 int miStart = mi;
9502 // no group 1 to 4 prefix byte
9503 generateREXprefix(false, srcReg, null, dstReg);
9504 // single byte opcode
9505 setMachineCodes(mi++, (byte) 0x08);
9506 emitRegRegOperands(dstReg, srcReg);
9507 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9508 }
9509
9510 /**
9511 * Generate a register--register-displacement OR. That is,
9512 * <PRE>
9513 * dstReg |= (byte) [srcReg + srcDisp]
9514 * </PRE>
9515 *
9516 * @param dstReg the destination register
9517 * @param srcBase the source register
9518 * @param srcDisp the source displacement
9519 */
9520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9521 public final void emitOR_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
9522 int miStart = mi;
9523 // no group 1 to 4 prefix byte
9524 generateREXprefix(false, dstReg, null, srcBase);
9525 // single byte opcode
9526 setMachineCodes(mi++, (byte) 0x0A);
9527 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9528 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9529 }
9530
9531 /**
9532 * Generate a register--register-offset OR. That is,
9533 * <PRE>
9534 * dstReg |= (byte) [srcIndex<<srcScale + srcDisp]
9535 * </PRE>
9536 *
9537 * @param dstReg the destination register
9538 * @param srcIndex the source index register
9539 * @param srcScale the source shift amount
9540 * @param srcDisp the source displacement
9541 */
9542 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9543 public final void emitOR_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9544 int miStart = mi;
9545 // no group 1 to 4 prefix byte
9546 generateREXprefix(false, dstReg, srcIndex, null);
9547 // single byte opcode
9548 setMachineCodes(mi++, (byte) 0x0A);
9549 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9550 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9551 }
9552
9553 /**
9554 * Generate a register--register-offset OR. That is,
9555 * <PRE>
9556 * dstReg |= (byte) [srcDisp]
9557 * </PRE>
9558 *
9559 * @param dstReg the destination register
9560 * @param srcDisp the source displacement
9561 */
9562 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9563 public final void emitOR_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
9564 int miStart = mi;
9565 // no group 1 to 4 prefix byte
9566 generateREXprefix(false, dstReg, null, null);
9567 // single byte opcode
9568 setMachineCodes(mi++, (byte) 0x0A);
9569 emitAbsRegOperands(srcDisp, dstReg);
9570 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9571 }
9572
9573 /**
9574 * Generate a register--register-offset OR. That is,
9575 * <PRE>
9576 * dstReg |= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
9577 * </PRE>
9578 *
9579 * @param dstReg the destination register
9580 * @param srcBase the source base register
9581 * @param srcIndex the source index register
9582 * @param srcScale the source shift amount
9583 * @param srcDisp the source displacement
9584 */
9585 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9586 public final void emitOR_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9587 int miStart = mi;
9588 // no group 1 to 4 prefix byte
9589 generateREXprefix(false, dstReg, srcIndex, srcBase);
9590 // single byte opcode
9591 setMachineCodes(mi++, (byte) 0x0A);
9592 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9593 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9594 }
9595
9596 /**
9597 * Generate a register--register(indirect) OR. That is,
9598 * <PRE>
9599 * dstReg |= (byte) [srcBase]
9600 * </PRE>
9601 *
9602 * @param dstReg the destination register
9603 * @param srcBase the source base register
9604 */
9605 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9606 public final void emitOR_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
9607 int miStart = mi;
9608 // no group 1 to 4 prefix byte
9609 generateREXprefix(false, dstReg, null, srcBase);
9610 // single byte opcode
9611 setMachineCodes(mi++, (byte) 0x0A);
9612 emitRegIndirectRegOperands(srcBase, dstReg);
9613 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9614 }
9615
9616 /**
9617 * Generate a register--immediate OR. That is,
9618 * <PRE>
9619 * dstReg |= imm
9620 * </PRE>
9621 *
9622 * @param dstReg the destination register
9623 * @param imm immediate
9624 */
9625 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9626 public final void emitOR_Reg_Imm(GPR dstReg, int imm) {
9627 int miStart = mi;
9628 // no group 1 to 4 prefix byte
9629 generateREXprefix(false, null, null, dstReg);
9630 // single byte opcode
9631 if (fits(imm,8)) {
9632 setMachineCodes(mi++, (byte) 0x83);
9633 // "register 0x1" is really part of the opcode
9634 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9635 emitImm8((byte)imm);
9636 } else if (dstReg == EAX) {
9637 setMachineCodes(mi++, (byte) 0x0D);
9638 emitImm32(imm);
9639 } else {
9640 setMachineCodes(mi++, (byte) 0x81);
9641 // "register 0x1" is really part of the opcode
9642 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9643 emitImm32(imm);
9644 }
9645 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
9646 }
9647
9648 /**
9649 * Generate a register-displacement--immediate OR. That is,
9650 * <PRE>
9651 * [dstBase + dstDisp] |= imm
9652 * </PRE>
9653 *
9654 * @param dstBase the destination register
9655 * @param dstDisp the destination displacement
9656 * @param imm immediate
9657 */
9658 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9659 public final void emitOR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
9660 int miStart = mi;
9661 // no group 1 to 4 prefix byte
9662 generateREXprefix(false, null, null, dstBase);
9663 // single byte opcode
9664 if (fits(imm,8)) {
9665 setMachineCodes(mi++, (byte) 0x83);
9666 // "register 0x1" is really part of the opcode
9667 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9668 emitImm8((byte)imm);
9669 } else {
9670 setMachineCodes(mi++, (byte) 0x81);
9671 // "register 0x1" is really part of the opcode
9672 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9673 emitImm32(imm);
9674 }
9675 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
9676 }
9677
9678 /**
9679 * Generate a register-offset--immediate OR. That is,
9680 * <PRE>
9681 * [dstIndex<<dstScale + dstDisp] |= imm
9682 * </PRE>
9683 *
9684 * @param dstIndex the destination index register
9685 * @param dstScale the destination shift amount
9686 * @param dstDisp the destination displacement
9687 * @param imm immediate
9688 */
9689 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9690 public final void emitOR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9691 int miStart = mi;
9692 // no group 1 to 4 prefix byte
9693 generateREXprefix(false, null, dstIndex, null);
9694 // single byte opcode
9695 if (fits(imm,8)) {
9696 setMachineCodes(mi++, (byte) 0x83);
9697 // "register 0x1" is really part of the opcode
9698 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9699 emitImm8((byte)imm);
9700 } else {
9701 setMachineCodes(mi++, (byte) 0x81);
9702 // "register 0x1" is really part of the opcode
9703 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9704 emitImm32(imm);
9705 }
9706 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
9707 }
9708
9709 /**
9710 * Generate a absolute--immediate OR. That is,
9711 * <PRE>
9712 * [dstDisp] |= imm
9713 * </PRE>
9714 *
9715 * @param dstDisp the destination displacement
9716 * @param imm immediate
9717 */
9718 public final void emitOR_Abs_Imm(Address dstDisp, int imm) {
9719 int miStart = mi;
9720 // no group 1 to 4 prefix byte
9721 generateREXprefix(false, null, null, null);
9722 // single byte opcode
9723 if (fits(imm,8)) {
9724 setMachineCodes(mi++, (byte) 0x83);
9725 // "register 0x1" is really part of the opcode
9726 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9727 emitImm8((byte)imm);
9728 } else {
9729 setMachineCodes(mi++, (byte) 0x81);
9730 // "register 0x1" is really part of the opcode
9731 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9732 emitImm32(imm);
9733 }
9734 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
9735 }
9736
9737 /**
9738 * Generate a register-index--immediate OR. That is,
9739 * <PRE>
9740 * [dstBase + dstIndex<<dstScale + dstDisp] |= imm
9741 * </PRE>
9742 *
9743 * @param dstBase the destination base register
9744 * @param dstIndex the destination index register
9745 * @param dstScale the destination shift amount
9746 * @param dstDisp the destination displacement
9747 * @param imm immediate
9748 */
9749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9750 public final void emitOR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9751 int miStart = mi;
9752 // no group 1 to 4 prefix byte
9753 generateREXprefix(false, null, dstIndex, dstBase);
9754 // single byte opcode
9755 if (fits(imm,8)) {
9756 setMachineCodes(mi++, (byte) 0x83);
9757 // "register 0x1" is really part of the opcode
9758 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9759 emitImm8((byte)imm);
9760 } else {
9761 setMachineCodes(mi++, (byte) 0x81);
9762 // "register 0x1" is really part of the opcode
9763 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9764 emitImm32(imm);
9765 }
9766 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
9767 }
9768
9769 /**
9770 * Generate a register(indirect)--immediate OR. That is,
9771 * <PRE>
9772 * [dstBase] |= imm
9773 * </PRE>
9774 *
9775 * @param dstBase the destination base register
9776 * @param imm immediate
9777 */
9778 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9779 public final void emitOR_RegInd_Imm(GPR dstBase, int imm) {
9780 int miStart = mi;
9781 // no group 1 to 4 prefix byte
9782 generateREXprefix(false, null, null, dstBase);
9783 // single byte opcode
9784 if (fits(imm,8)) {
9785 setMachineCodes(mi++, (byte) 0x83);
9786 // "register 0x1" is really part of the opcode
9787 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9788 emitImm8((byte)imm);
9789 } else {
9790 setMachineCodes(mi++, (byte) 0x81);
9791 // "register 0x1" is really part of the opcode
9792 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9793 emitImm32(imm);
9794 }
9795 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
9796 }
9797
9798 /**
9799 * Generate a register--immediate OR. That is,
9800 * <PRE>
9801 * dstReg |= (word) imm
9802 * </PRE>
9803 *
9804 * @param dstReg the destination register
9805 * @param imm immediate
9806 */
9807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9808 public final void emitOR_Reg_Imm_Word(GPR dstReg, int imm) {
9809 int miStart = mi;
9810 setMachineCodes(mi++, (byte) 0x66);
9811 generateREXprefix(false, null, null, dstReg);
9812 // single byte opcode
9813 if (fits(imm,8)) {
9814 setMachineCodes(mi++, (byte) 0x83);
9815 // "register 0x1" is really part of the opcode
9816 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9817 emitImm8((byte)imm);
9818 } else if (dstReg == EAX) {
9819 setMachineCodes(mi++, (byte) 0x0D);
9820 emitImm16(imm);
9821 } else {
9822 setMachineCodes(mi++, (byte) 0x81);
9823 // "register 0x1" is really part of the opcode
9824 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9825 emitImm16(imm);
9826 }
9827 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
9828 }
9829
9830 /**
9831 * Generate a register-displacement--immediate OR. That is,
9832 * <PRE>
9833 * [dstBase + dstDisp] |= (word) imm
9834 * </PRE>
9835 *
9836 * @param dstBase the destination register
9837 * @param dstDisp the destination displacement
9838 * @param imm immediate
9839 */
9840 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9841 public final void emitOR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
9842 int miStart = mi;
9843 setMachineCodes(mi++, (byte) 0x66);
9844 generateREXprefix(false, null, null, dstBase);
9845 // single byte opcode
9846 if (fits(imm,8)) {
9847 setMachineCodes(mi++, (byte) 0x83);
9848 // "register 0x1" is really part of the opcode
9849 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9850 emitImm8((byte)imm);
9851 } else {
9852 setMachineCodes(mi++, (byte) 0x81);
9853 // "register 0x1" is really part of the opcode
9854 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9855 emitImm16(imm);
9856 }
9857 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
9858 }
9859
9860 /**
9861 * Generate a register-offset--immediate OR. That is,
9862 * <PRE>
9863 * [dstIndex<<dstScale + dstDisp] |= (word) imm
9864 * </PRE>
9865 *
9866 * @param dstIndex the destination index register
9867 * @param dstScale the destination shift amount
9868 * @param dstDisp the destination displacement
9869 * @param imm immediate
9870 */
9871 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9872 public final void emitOR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9873 int miStart = mi;
9874 setMachineCodes(mi++, (byte) 0x66);
9875 generateREXprefix(false, null, dstIndex, null);
9876 // single byte opcode
9877 if (fits(imm,8)) {
9878 setMachineCodes(mi++, (byte) 0x83);
9879 // "register 0x1" is really part of the opcode
9880 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9881 emitImm8((byte)imm);
9882 } else {
9883 setMachineCodes(mi++, (byte) 0x81);
9884 // "register 0x1" is really part of the opcode
9885 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9886 emitImm16(imm);
9887 }
9888 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
9889 }
9890
9891 /**
9892 * Generate a absolute--immediate OR. That is,
9893 * <PRE>
9894 * [dstDisp] |= (word) imm
9895 * </PRE>
9896 *
9897 * @param dstDisp the destination displacement
9898 * @param imm immediate
9899 */
9900 public final void emitOR_Abs_Imm_Word(Address dstDisp, int imm) {
9901 int miStart = mi;
9902 setMachineCodes(mi++, (byte) 0x66);
9903 generateREXprefix(false, null, null, null);
9904 // single byte opcode
9905 if (fits(imm,8)) {
9906 setMachineCodes(mi++, (byte) 0x83);
9907 // "register 0x1" is really part of the opcode
9908 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9909 emitImm8((byte)imm);
9910 } else {
9911 setMachineCodes(mi++, (byte) 0x81);
9912 // "register 0x1" is really part of the opcode
9913 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9914 emitImm16(imm);
9915 }
9916 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
9917 }
9918
9919 /**
9920 * Generate a register-index--immediate OR. That is,
9921 * <PRE>
9922 * [dstBase + dstIndex<<dstScale + dstDisp] |= (word) imm
9923 * </PRE>
9924 *
9925 * @param dstBase the destination base register
9926 * @param dstIndex the destination index register
9927 * @param dstScale the destination shift amount
9928 * @param dstDisp the destination displacement
9929 * @param imm immediate
9930 */
9931 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9932 public final void emitOR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9933 int miStart = mi;
9934 setMachineCodes(mi++, (byte) 0x66);
9935 generateREXprefix(false, null, dstIndex, dstBase);
9936 // single byte opcode
9937 if (fits(imm,8)) {
9938 setMachineCodes(mi++, (byte) 0x83);
9939 // "register 0x1" is really part of the opcode
9940 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9941 emitImm8((byte)imm);
9942 } else {
9943 setMachineCodes(mi++, (byte) 0x81);
9944 // "register 0x1" is really part of the opcode
9945 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9946 emitImm16(imm);
9947 }
9948 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
9949 }
9950
9951 /**
9952 * Generate a register(indirect)--immediate OR. That is,
9953 * <PRE>
9954 * [dstBase] |= (word) imm
9955 * </PRE>
9956 *
9957 * @param dstBase the destination base register
9958 * @param imm immediate
9959 */
9960 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9961 public final void emitOR_RegInd_Imm_Word(GPR dstBase, int imm) {
9962 int miStart = mi;
9963 setMachineCodes(mi++, (byte) 0x66);
9964 generateREXprefix(false, null, null, dstBase);
9965 // single byte opcode
9966 if (fits(imm,8)) {
9967 setMachineCodes(mi++, (byte) 0x83);
9968 // "register 0x1" is really part of the opcode
9969 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9970 emitImm8((byte)imm);
9971 } else {
9972 setMachineCodes(mi++, (byte) 0x81);
9973 // "register 0x1" is really part of the opcode
9974 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9975 emitImm16(imm);
9976 }
9977 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
9978 }
9979
9980 /**
9981 * Generate a register--immediate OR. That is,
9982 * <PRE>
9983 * dstReg |= (quad) imm
9984 * </PRE>
9985 *
9986 * @param dstReg the destination register
9987 * @param imm immediate
9988 */
9989 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9990 public final void emitOR_Reg_Imm_Quad(GPR dstReg, int imm) {
9991 int miStart = mi;
9992 // no group 1 to 4 prefix byte
9993 generateREXprefix(true, null, null, dstReg);
9994 // single byte opcode
9995 if (fits(imm,8)) {
9996 setMachineCodes(mi++, (byte) 0x83);
9997 // "register 0x1" is really part of the opcode
9998 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9999 emitImm8((byte)imm);
10000 } else if (dstReg == EAX) {
10001 setMachineCodes(mi++, (byte) 0x0D);
10002 emitImm32(imm);
10003 } else {
10004 setMachineCodes(mi++, (byte) 0x81);
10005 // "register 0x1" is really part of the opcode
10006 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
10007 emitImm32(imm);
10008 }
10009 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
10010 }
10011
10012 /**
10013 * Generate a register-displacement--immediate OR. That is,
10014 * <PRE>
10015 * [dstBase + dstDisp] |= (quad) imm
10016 * </PRE>
10017 *
10018 * @param dstBase the destination register
10019 * @param dstDisp the destination displacement
10020 * @param imm immediate
10021 */
10022 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10023 public final void emitOR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
10024 int miStart = mi;
10025 // no group 1 to 4 prefix byte
10026 generateREXprefix(true, null, null, dstBase);
10027 // single byte opcode
10028 if (fits(imm,8)) {
10029 setMachineCodes(mi++, (byte) 0x83);
10030 // "register 0x1" is really part of the opcode
10031 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10032 emitImm8((byte)imm);
10033 } else {
10034 setMachineCodes(mi++, (byte) 0x81);
10035 // "register 0x1" is really part of the opcode
10036 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10037 emitImm32(imm);
10038 }
10039 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
10040 }
10041
10042 /**
10043 * Generate a register-offset--immediate OR. That is,
10044 * <PRE>
10045 * [dstIndex<<dstScale + dstDisp] |= (quad) imm
10046 * </PRE>
10047 *
10048 * @param dstIndex the destination index register
10049 * @param dstScale the destination shift amount
10050 * @param dstDisp the destination displacement
10051 * @param imm immediate
10052 */
10053 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10054 public final void emitOR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10055 int miStart = mi;
10056 // no group 1 to 4 prefix byte
10057 generateREXprefix(true, null, dstIndex, null);
10058 // single byte opcode
10059 if (fits(imm,8)) {
10060 setMachineCodes(mi++, (byte) 0x83);
10061 // "register 0x1" is really part of the opcode
10062 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10063 emitImm8((byte)imm);
10064 } else {
10065 setMachineCodes(mi++, (byte) 0x81);
10066 // "register 0x1" is really part of the opcode
10067 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10068 emitImm32(imm);
10069 }
10070 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
10071 }
10072
10073 /**
10074 * Generate a absolute--immediate OR. That is,
10075 * <PRE>
10076 * [dstDisp] |= (quad) imm
10077 * </PRE>
10078 *
10079 * @param dstDisp the destination displacement
10080 * @param imm immediate
10081 */
10082 public final void emitOR_Abs_Imm_Quad(Address dstDisp, int imm) {
10083 int miStart = mi;
10084 // no group 1 to 4 prefix byte
10085 generateREXprefix(true, null, null, null);
10086 // single byte opcode
10087 if (fits(imm,8)) {
10088 setMachineCodes(mi++, (byte) 0x83);
10089 // "register 0x1" is really part of the opcode
10090 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10091 emitImm8((byte)imm);
10092 } else {
10093 setMachineCodes(mi++, (byte) 0x81);
10094 // "register 0x1" is really part of the opcode
10095 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10096 emitImm32(imm);
10097 }
10098 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
10099 }
10100
10101 /**
10102 * Generate a register-index--immediate OR. That is,
10103 * <PRE>
10104 * [dstBase + dstIndex<<dstScale + dstDisp] |= (quad) imm
10105 * </PRE>
10106 *
10107 * @param dstBase the destination base register
10108 * @param dstIndex the destination index register
10109 * @param dstScale the destination shift amount
10110 * @param dstDisp the destination displacement
10111 * @param imm immediate
10112 */
10113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10114 public final void emitOR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10115 int miStart = mi;
10116 // no group 1 to 4 prefix byte
10117 generateREXprefix(true, null, dstIndex, dstBase);
10118 // single byte opcode
10119 if (fits(imm,8)) {
10120 setMachineCodes(mi++, (byte) 0x83);
10121 // "register 0x1" is really part of the opcode
10122 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10123 emitImm8((byte)imm);
10124 } else {
10125 setMachineCodes(mi++, (byte) 0x81);
10126 // "register 0x1" is really part of the opcode
10127 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10128 emitImm32(imm);
10129 }
10130 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
10131 }
10132
10133 /**
10134 * Generate a register(indirect)--immediate OR. That is,
10135 * <PRE>
10136 * [dstBase] |= (quad) imm
10137 * </PRE>
10138 *
10139 * @param dstBase the destination base register
10140 * @param imm immediate
10141 */
10142 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10143 public final void emitOR_RegInd_Imm_Quad(GPR dstBase, int imm) {
10144 int miStart = mi;
10145 // no group 1 to 4 prefix byte
10146 generateREXprefix(true, null, null, dstBase);
10147 // single byte opcode
10148 if (fits(imm,8)) {
10149 setMachineCodes(mi++, (byte) 0x83);
10150 // "register 0x1" is really part of the opcode
10151 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10152 emitImm8((byte)imm);
10153 } else {
10154 setMachineCodes(mi++, (byte) 0x81);
10155 // "register 0x1" is really part of the opcode
10156 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10157 emitImm32(imm);
10158 }
10159 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
10160 }
10161
10162 /**
10163 * Generate a register--immediate OR. That is,
10164 * <PRE>
10165 * dstReg |= (byte) imm
10166 * </PRE>
10167 *
10168 * @param dstReg the destination register
10169 * @param imm immediate
10170 */
10171 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10172 public final void emitOR_Reg_Imm_Byte(GPR dstReg, int imm) {
10173 int miStart = mi;
10174 if (dstReg == EAX) {
10175 setMachineCodes(mi++, (byte) 0x0C);
10176 emitImm8(imm);
10177 } else {
10178 generateREXprefix(false, null, null, dstReg);
10179 setMachineCodes(mi++, (byte) 0x80);
10180 // "register 0x1" is really part of the opcode
10181 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
10182 emitImm8(imm);
10183 }
10184 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
10185 }
10186
10187 /**
10188 * Generate a register-displacement--immediate OR. That is,
10189 * <PRE>
10190 * [dstBase + dstDisp] |= (byte) imm
10191 * </PRE>
10192 *
10193 * @param dstBase the destination register
10194 * @param dstDisp the destination displacement
10195 * @param imm immediate
10196 */
10197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10198 public final void emitOR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
10199 int miStart = mi;
10200 generateREXprefix(false, null, null, dstBase);
10201 setMachineCodes(mi++, (byte) 0x80);
10202 // "register 0x1" is really part of the opcode
10203 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10204 emitImm8(imm);
10205 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
10206 }
10207
10208 /**
10209 * Generate a register-index--immediate OR. That is,
10210 * <PRE>
10211 * [dstBase + dstIndex<<scale + dstDisp] |= (byte) imm
10212 * </PRE>
10213 *
10214 * @param dstBase the destination base register
10215 * @param dstIndex the destination index register
10216 * @param dstScale the destination shift amount
10217 * @param dstDisp the destination displacement
10218 * @param imm immediate
10219 */
10220 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10221 public final void emitOR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10222 int miStart = mi;
10223 generateREXprefix(false, null, dstIndex, dstBase);
10224 setMachineCodes(mi++, (byte) 0x80);
10225 // "register 0x1" is really part of the opcode
10226 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10227 emitImm8(imm);
10228 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
10229 }
10230
10231 /**
10232 * Generate a register-offset--immediate OR. That is,
10233 * <PRE>
10234 * [dstIndex<<dstScale + dstDisp] |= (byte) imm
10235 * </PRE>
10236 *
10237 * @param dstIndex the destination index register
10238 * @param dstScale the destination shift amount
10239 * @param dstDisp the destination displacement
10240 * @param imm immediate
10241 */
10242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10243 public final void emitOR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10244 int miStart = mi;
10245 generateREXprefix(false, null, dstIndex, null);
10246 setMachineCodes(mi++, (byte) 0x80);
10247 // "register 0x1" is really part of the opcode
10248 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10249 emitImm8(imm);
10250 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
10251 }
10252
10253 /**
10254 * Generate a absolute--immediate OR. That is,
10255 * <PRE>
10256 * [dstDisp] |= (byte) imm
10257 * </PRE>
10258 *
10259 * @param dstDisp the destination displacement
10260 * @param imm immediate
10261 */
10262 public final void emitOR_Abs_Imm_Byte(Address dstDisp, int imm) {
10263 int miStart = mi;
10264 generateREXprefix(false, null, null, null);
10265 setMachineCodes(mi++, (byte) 0x80);
10266 // "register 0x1" is really part of the opcode
10267 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10268 emitImm8(imm);
10269 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
10270 }
10271
10272 /**
10273 * Generate a register(indirect)--immediate OR. That is,
10274 * <PRE>
10275 * [dstBase] |= (byte) imm
10276 * </PRE>
10277 *
10278 * @param dstBase the destination base register
10279 * @param imm immediate
10280 */
10281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10282 public final void emitOR_RegInd_Imm_Byte(GPR dstBase, int imm) {
10283 int miStart = mi;
10284 generateREXprefix(false, null, null, dstBase);
10285 setMachineCodes(mi++, (byte) 0x80);
10286 // "register 0x1" is really part of the opcode
10287 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10288 emitImm8(imm);
10289 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
10290 }
10291
10292 /**
10293 * Generate a register(indirect)--register SBB. That is,
10294 * <PRE>
10295 * [dstBase] -CF= srcReg
10296 * </PRE>
10297 *
10298 * @param dstBase the destination base
10299 * @param srcReg the source register
10300 */
10301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10302 public final void emitSBB_RegInd_Reg(GPR dstBase, GPR srcReg) {
10303 int miStart = mi;
10304 // no group 1 to 4 prefix byte
10305 generateREXprefix(false, srcReg, null, dstBase);
10306 // single byte opcode
10307 setMachineCodes(mi++, (byte) 0x19);
10308 emitRegIndirectRegOperands(dstBase, srcReg);
10309 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10310 }
10311
10312 /**
10313 * Generate a register-offset--register SBB. That is,
10314 * <PRE>
10315 * [dstReg<<dstScale + dstDisp] -CF= srcReg
10316 * </PRE>
10317 *
10318 * @param dstIndex the destination index register
10319 * @param dstScale the destination shift amount
10320 * @param dstDisp the destination displacement
10321 * @param srcReg the source register
10322 */
10323 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10324 public final void emitSBB_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10325 int miStart = mi;
10326 // no group 1 to 4 prefix byte
10327 generateREXprefix(false, srcReg, dstIndex, null);
10328 // single byte opcode
10329 setMachineCodes(mi++, (byte) 0x19);
10330 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10331 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10332 }
10333
10334 /**
10335 * Generate a absolute--register SBB. That is,
10336 * <PRE>
10337 * [dstDisp] -CF= srcReg
10338 * </PRE>
10339 *
10340 * @param dstDisp the destination address
10341 * @param srcReg the source register
10342 */
10343 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10344 public final void emitSBB_Abs_Reg(Address dstDisp, GPR srcReg) {
10345 int miStart = mi;
10346 // no group 1 to 4 prefix byte
10347 generateREXprefix(false, srcReg, null, null);
10348 // single byte opcode
10349 setMachineCodes(mi++, (byte) 0x19);
10350 emitAbsRegOperands(dstDisp, srcReg);
10351 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10352 }
10353
10354 /**
10355 * Generate a register-index--register SBB. That is,
10356 * <PRE>
10357 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= srcReg
10358 * </PRE>
10359 *
10360 * @param dstBase the base register
10361 * @param dstIndex the destination index register
10362 * @param dstScale the destination shift amount
10363 * @param dstDisp the destination displacement
10364 * @param srcReg the source register
10365 */
10366 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10367 public final void emitSBB_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10368 int miStart = mi;
10369 // no group 1 to 4 prefix byte
10370 generateREXprefix(false, srcReg, dstIndex, dstBase);
10371 // single byte opcode
10372 setMachineCodes(mi++, (byte) 0x19);
10373 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10374 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10375 }
10376
10377 /**
10378 * Generate a register-displacement--register SBB. That is,
10379 * <PRE>
10380 * [dstBase + dstDisp] -CF= srcReg
10381 * </PRE>
10382 *
10383 * @param dstBase the base register
10384 * @param dstDisp the destination displacement
10385 * @param srcReg the source register
10386 */
10387 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10388 public final void emitSBB_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
10389 int miStart = mi;
10390 // no group 1 to 4 prefix byte
10391 generateREXprefix(false, srcReg, null, dstBase);
10392 // single byte opcode
10393 setMachineCodes(mi++, (byte) 0x19);
10394 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10395 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10396 }
10397
10398 /**
10399 * Generate a register--register SBB. That is,
10400 * <PRE>
10401 * dstReg -CF= srcReg
10402 * </PRE>
10403 *
10404 * @param dstReg the destination register
10405 * @param srcReg the source register
10406 */
10407 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10408 public final void emitSBB_Reg_Reg(GPR dstReg, GPR srcReg) {
10409 int miStart = mi;
10410 // no group 1 to 4 prefix byte
10411 generateREXprefix(false, srcReg, null, dstReg);
10412 // single byte opcode
10413 setMachineCodes(mi++, (byte) 0x19);
10414 emitRegRegOperands(dstReg, srcReg);
10415 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10416 }
10417
10418 /**
10419 * Generate a register--register-displacement SBB. That is,
10420 * <PRE>
10421 * dstReg -CF= [srcReg + srcDisp]
10422 * </PRE>
10423 *
10424 * @param dstReg the destination register
10425 * @param srcBase the source register
10426 * @param srcDisp the source displacement
10427 */
10428 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10429 public final void emitSBB_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
10430 int miStart = mi;
10431 // no group 1 to 4 prefix byte
10432 generateREXprefix(false, dstReg, null, srcBase);
10433 // single byte opcode
10434 setMachineCodes(mi++, (byte) 0x1B);
10435 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10436 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10437 }
10438
10439 /**
10440 * Generate a register--register-offset SBB. That is,
10441 * <PRE>
10442 * dstReg -CF= [srcIndex<<srcScale + srcDisp]
10443 * </PRE>
10444 *
10445 * @param dstReg the destination register
10446 * @param srcIndex the source index register
10447 * @param srcScale the source shift amount
10448 * @param srcDisp the source displacement
10449 */
10450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10451 public final void emitSBB_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10452 int miStart = mi;
10453 // no group 1 to 4 prefix byte
10454 generateREXprefix(false, dstReg, srcIndex, null);
10455 // single byte opcode
10456 setMachineCodes(mi++, (byte) 0x1B);
10457 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10458 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10459 }
10460
10461 /**
10462 * Generate a register--register-offset SBB. That is,
10463 * <PRE>
10464 * dstReg -CF= [srcDisp]
10465 * </PRE>
10466 *
10467 * @param dstReg the destination register
10468 * @param srcDisp the source displacement
10469 */
10470 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10471 public final void emitSBB_Reg_Abs(GPR dstReg, Address srcDisp) {
10472 int miStart = mi;
10473 // no group 1 to 4 prefix byte
10474 generateREXprefix(false, dstReg, null, null);
10475 // single byte opcode
10476 setMachineCodes(mi++, (byte) 0x1B);
10477 emitAbsRegOperands(srcDisp, dstReg);
10478 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10479 }
10480
10481 /**
10482 * Generate a register--register-offset SBB. That is,
10483 * <PRE>
10484 * dstReg -CF= [srcBase + srcIndex<<srcScale + srcDisp]
10485 * </PRE>
10486 *
10487 * @param dstReg the destination register
10488 * @param srcBase the source base register
10489 * @param srcIndex the source index register
10490 * @param srcScale the source shift amount
10491 * @param srcDisp the source displacement
10492 */
10493 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10494 public final void emitSBB_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10495 int miStart = mi;
10496 // no group 1 to 4 prefix byte
10497 generateREXprefix(false, dstReg, srcIndex, srcBase);
10498 // single byte opcode
10499 setMachineCodes(mi++, (byte) 0x1B);
10500 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10501 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10502 }
10503
10504 /**
10505 * Generate a register--register(indirect) SBB. That is,
10506 * <PRE>
10507 * dstReg -CF= [srcBase]
10508 * </PRE>
10509 *
10510 * @param dstReg the destination register
10511 * @param srcBase the source base register
10512 */
10513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10514 public final void emitSBB_Reg_RegInd(GPR dstReg, GPR srcBase) {
10515 int miStart = mi;
10516 // no group 1 to 4 prefix byte
10517 generateREXprefix(false, dstReg, null, srcBase);
10518 // single byte opcode
10519 setMachineCodes(mi++, (byte) 0x1B);
10520 emitRegIndirectRegOperands(srcBase, dstReg);
10521 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
10522 }
10523
10524 /**
10525 * Generate a register(indirect)--register SBB. That is,
10526 * <PRE>
10527 * [dstBase] -CF= (word) srcReg
10528 * </PRE>
10529 *
10530 * @param dstBase the destination base
10531 * @param srcReg the source register
10532 */
10533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10534 public final void emitSBB_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
10535 int miStart = mi;
10536 setMachineCodes(mi++, (byte) 0x66);
10537 generateREXprefix(false, srcReg, null, dstBase);
10538 // single byte opcode
10539 setMachineCodes(mi++, (byte) 0x19);
10540 emitRegIndirectRegOperands(dstBase, srcReg);
10541 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10542 }
10543
10544 /**
10545 * Generate a register-offset--register SBB. That is,
10546 * <PRE>
10547 * [dstReg<<dstScale + dstDisp] -CF= (word) srcReg
10548 * </PRE>
10549 *
10550 * @param dstIndex the destination index register
10551 * @param dstScale the destination shift amount
10552 * @param dstDisp the destination displacement
10553 * @param srcReg the source register
10554 */
10555 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10556 public final void emitSBB_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10557 int miStart = mi;
10558 setMachineCodes(mi++, (byte) 0x66);
10559 generateREXprefix(false, srcReg, dstIndex, null);
10560 // single byte opcode
10561 setMachineCodes(mi++, (byte) 0x19);
10562 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10563 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10564 }
10565
10566 /**
10567 * Generate a absolute--register SBB. That is,
10568 * <PRE>
10569 * [dstDisp] -CF= (word) srcReg
10570 * </PRE>
10571 *
10572 * @param dstDisp the destination address
10573 * @param srcReg the source register
10574 */
10575 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10576 public final void emitSBB_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
10577 int miStart = mi;
10578 setMachineCodes(mi++, (byte) 0x66);
10579 generateREXprefix(false, srcReg, null, null);
10580 // single byte opcode
10581 setMachineCodes(mi++, (byte) 0x19);
10582 emitAbsRegOperands(dstDisp, srcReg);
10583 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10584 }
10585
10586 /**
10587 * Generate a register-index--register SBB. That is,
10588 * <PRE>
10589 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (word) srcReg
10590 * </PRE>
10591 *
10592 * @param dstBase the base register
10593 * @param dstIndex the destination index register
10594 * @param dstScale the destination shift amount
10595 * @param dstDisp the destination displacement
10596 * @param srcReg the source register
10597 */
10598 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10599 public final void emitSBB_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10600 int miStart = mi;
10601 setMachineCodes(mi++, (byte) 0x66);
10602 generateREXprefix(false, srcReg, dstIndex, dstBase);
10603 // single byte opcode
10604 setMachineCodes(mi++, (byte) 0x19);
10605 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10606 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10607 }
10608
10609 /**
10610 * Generate a register-displacement--register SBB. That is,
10611 * <PRE>
10612 * [dstBase + dstDisp] -CF= (word) srcReg
10613 * </PRE>
10614 *
10615 * @param dstBase the base register
10616 * @param dstDisp the destination displacement
10617 * @param srcReg the source register
10618 */
10619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10620 public final void emitSBB_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
10621 int miStart = mi;
10622 setMachineCodes(mi++, (byte) 0x66);
10623 generateREXprefix(false, srcReg, null, dstBase);
10624 // single byte opcode
10625 setMachineCodes(mi++, (byte) 0x19);
10626 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10627 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10628 }
10629
10630 /**
10631 * Generate a register--register SBB. That is,
10632 * <PRE>
10633 * dstReg -CF= (word) srcReg
10634 * </PRE>
10635 *
10636 * @param dstReg the destination register
10637 * @param srcReg the source register
10638 */
10639 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10640 public final void emitSBB_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
10641 int miStart = mi;
10642 setMachineCodes(mi++, (byte) 0x66);
10643 generateREXprefix(false, srcReg, null, dstReg);
10644 // single byte opcode
10645 setMachineCodes(mi++, (byte) 0x19);
10646 emitRegRegOperands(dstReg, srcReg);
10647 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10648 }
10649
10650 /**
10651 * Generate a register--register-displacement SBB. That is,
10652 * <PRE>
10653 * dstReg -CF= (word) [srcReg + srcDisp]
10654 * </PRE>
10655 *
10656 * @param dstReg the destination register
10657 * @param srcBase the source register
10658 * @param srcDisp the source displacement
10659 */
10660 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10661 public final void emitSBB_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
10662 int miStart = mi;
10663 setMachineCodes(mi++, (byte) 0x66);
10664 generateREXprefix(false, dstReg, null, srcBase);
10665 // single byte opcode
10666 setMachineCodes(mi++, (byte) 0x1B);
10667 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10668 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10669 }
10670
10671 /**
10672 * Generate a register--register-offset SBB. That is,
10673 * <PRE>
10674 * dstReg -CF= (word) [srcIndex<<srcScale + srcDisp]
10675 * </PRE>
10676 *
10677 * @param dstReg the destination register
10678 * @param srcIndex the source index register
10679 * @param srcScale the source shift amount
10680 * @param srcDisp the source displacement
10681 */
10682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10683 public final void emitSBB_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10684 int miStart = mi;
10685 setMachineCodes(mi++, (byte) 0x66);
10686 generateREXprefix(false, dstReg, srcIndex, null);
10687 // single byte opcode
10688 setMachineCodes(mi++, (byte) 0x1B);
10689 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10690 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10691 }
10692
10693 /**
10694 * Generate a register--register-offset SBB. That is,
10695 * <PRE>
10696 * dstReg -CF= (word) [srcDisp]
10697 * </PRE>
10698 *
10699 * @param dstReg the destination register
10700 * @param srcDisp the source displacement
10701 */
10702 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10703 public final void emitSBB_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
10704 int miStart = mi;
10705 setMachineCodes(mi++, (byte) 0x66);
10706 generateREXprefix(false, dstReg, null, null);
10707 // single byte opcode
10708 setMachineCodes(mi++, (byte) 0x1B);
10709 emitAbsRegOperands(srcDisp, dstReg);
10710 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10711 }
10712
10713 /**
10714 * Generate a register--register-offset SBB. That is,
10715 * <PRE>
10716 * dstReg -CF= (word) [srcBase + srcIndex<<srcScale + srcDisp]
10717 * </PRE>
10718 *
10719 * @param dstReg the destination register
10720 * @param srcBase the source base register
10721 * @param srcIndex the source index register
10722 * @param srcScale the source shift amount
10723 * @param srcDisp the source displacement
10724 */
10725 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10726 public final void emitSBB_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10727 int miStart = mi;
10728 setMachineCodes(mi++, (byte) 0x66);
10729 generateREXprefix(false, dstReg, srcIndex, srcBase);
10730 // single byte opcode
10731 setMachineCodes(mi++, (byte) 0x1B);
10732 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10733 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10734 }
10735
10736 /**
10737 * Generate a register--register(indirect) SBB. That is,
10738 * <PRE>
10739 * dstReg -CF= (word) [srcBase]
10740 * </PRE>
10741 *
10742 * @param dstReg the destination register
10743 * @param srcBase the source base register
10744 */
10745 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10746 public final void emitSBB_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
10747 int miStart = mi;
10748 setMachineCodes(mi++, (byte) 0x66);
10749 generateREXprefix(false, dstReg, null, srcBase);
10750 // single byte opcode
10751 setMachineCodes(mi++, (byte) 0x1B);
10752 emitRegIndirectRegOperands(srcBase, dstReg);
10753 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
10754 }
10755
10756 /**
10757 * Generate a register(indirect)--register SBB. That is,
10758 * <PRE>
10759 * [dstBase] -CF= (quad) srcReg
10760 * </PRE>
10761 *
10762 * @param dstBase the destination base
10763 * @param srcReg the source register
10764 */
10765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10766 public final void emitSBB_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
10767 int miStart = mi;
10768 // no group 1 to 4 prefix byte
10769 generateREXprefix(true, srcReg, null, dstBase);
10770 // single byte opcode
10771 setMachineCodes(mi++, (byte) 0x19);
10772 emitRegIndirectRegOperands(dstBase, srcReg);
10773 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10774 }
10775
10776 /**
10777 * Generate a register-offset--register SBB. That is,
10778 * <PRE>
10779 * [dstReg<<dstScale + dstDisp] -CF= (quad) srcReg
10780 * </PRE>
10781 *
10782 * @param dstIndex the destination index register
10783 * @param dstScale the destination shift amount
10784 * @param dstDisp the destination displacement
10785 * @param srcReg the source register
10786 */
10787 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10788 public final void emitSBB_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10789 int miStart = mi;
10790 // no group 1 to 4 prefix byte
10791 generateREXprefix(true, srcReg, dstIndex, null);
10792 // single byte opcode
10793 setMachineCodes(mi++, (byte) 0x19);
10794 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10795 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10796 }
10797
10798 /**
10799 * Generate a absolute--register SBB. That is,
10800 * <PRE>
10801 * [dstDisp] -CF= (quad) srcReg
10802 * </PRE>
10803 *
10804 * @param dstDisp the destination address
10805 * @param srcReg the source register
10806 */
10807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10808 public final void emitSBB_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
10809 int miStart = mi;
10810 // no group 1 to 4 prefix byte
10811 generateREXprefix(true, srcReg, null, null);
10812 // single byte opcode
10813 setMachineCodes(mi++, (byte) 0x19);
10814 emitAbsRegOperands(dstDisp, srcReg);
10815 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10816 }
10817
10818 /**
10819 * Generate a register-index--register SBB. That is,
10820 * <PRE>
10821 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (quad) srcReg
10822 * </PRE>
10823 *
10824 * @param dstBase the base register
10825 * @param dstIndex the destination index register
10826 * @param dstScale the destination shift amount
10827 * @param dstDisp the destination displacement
10828 * @param srcReg the source register
10829 */
10830 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10831 public final void emitSBB_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10832 int miStart = mi;
10833 // no group 1 to 4 prefix byte
10834 generateREXprefix(true, srcReg, dstIndex, dstBase);
10835 // single byte opcode
10836 setMachineCodes(mi++, (byte) 0x19);
10837 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10838 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10839 }
10840
10841 /**
10842 * Generate a register-displacement--register SBB. That is,
10843 * <PRE>
10844 * [dstBase + dstDisp] -CF= (quad) srcReg
10845 * </PRE>
10846 *
10847 * @param dstBase the base register
10848 * @param dstDisp the destination displacement
10849 * @param srcReg the source register
10850 */
10851 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10852 public final void emitSBB_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
10853 int miStart = mi;
10854 // no group 1 to 4 prefix byte
10855 generateREXprefix(true, srcReg, null, dstBase);
10856 // single byte opcode
10857 setMachineCodes(mi++, (byte) 0x19);
10858 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10859 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10860 }
10861
10862 /**
10863 * Generate a register--register SBB. That is,
10864 * <PRE>
10865 * dstReg -CF= (quad) srcReg
10866 * </PRE>
10867 *
10868 * @param dstReg the destination register
10869 * @param srcReg the source register
10870 */
10871 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10872 public final void emitSBB_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
10873 int miStart = mi;
10874 // no group 1 to 4 prefix byte
10875 generateREXprefix(true, srcReg, null, dstReg);
10876 // single byte opcode
10877 setMachineCodes(mi++, (byte) 0x19);
10878 emitRegRegOperands(dstReg, srcReg);
10879 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10880 }
10881
10882 /**
10883 * Generate a register--register-displacement SBB. That is,
10884 * <PRE>
10885 * dstReg -CF= (quad) [srcReg + srcDisp]
10886 * </PRE>
10887 *
10888 * @param dstReg the destination register
10889 * @param srcBase the source register
10890 * @param srcDisp the source displacement
10891 */
10892 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10893 public final void emitSBB_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
10894 int miStart = mi;
10895 // no group 1 to 4 prefix byte
10896 generateREXprefix(true, dstReg, null, srcBase);
10897 // single byte opcode
10898 setMachineCodes(mi++, (byte) 0x1B);
10899 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10900 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10901 }
10902
10903 /**
10904 * Generate a register--register-offset SBB. That is,
10905 * <PRE>
10906 * dstReg -CF= (quad) [srcIndex<<srcScale + srcDisp]
10907 * </PRE>
10908 *
10909 * @param dstReg the destination register
10910 * @param srcIndex the source index register
10911 * @param srcScale the source shift amount
10912 * @param srcDisp the source displacement
10913 */
10914 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10915 public final void emitSBB_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10916 int miStart = mi;
10917 // no group 1 to 4 prefix byte
10918 generateREXprefix(true, dstReg, srcIndex, null);
10919 // single byte opcode
10920 setMachineCodes(mi++, (byte) 0x1B);
10921 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10922 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10923 }
10924
10925 /**
10926 * Generate a register--register-offset SBB. That is,
10927 * <PRE>
10928 * dstReg -CF= (quad) [srcDisp]
10929 * </PRE>
10930 *
10931 * @param dstReg the destination register
10932 * @param srcDisp the source displacement
10933 */
10934 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10935 public final void emitSBB_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
10936 int miStart = mi;
10937 // no group 1 to 4 prefix byte
10938 generateREXprefix(true, dstReg, null, null);
10939 // single byte opcode
10940 setMachineCodes(mi++, (byte) 0x1B);
10941 emitAbsRegOperands(srcDisp, dstReg);
10942 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10943 }
10944
10945 /**
10946 * Generate a register--register-offset SBB. That is,
10947 * <PRE>
10948 * dstReg -CF= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
10949 * </PRE>
10950 *
10951 * @param dstReg the destination register
10952 * @param srcBase the source base register
10953 * @param srcIndex the source index register
10954 * @param srcScale the source shift amount
10955 * @param srcDisp the source displacement
10956 */
10957 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10958 public final void emitSBB_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10959 int miStart = mi;
10960 // no group 1 to 4 prefix byte
10961 generateREXprefix(true, dstReg, srcIndex, srcBase);
10962 // single byte opcode
10963 setMachineCodes(mi++, (byte) 0x1B);
10964 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10965 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10966 }
10967
10968 /**
10969 * Generate a register--register(indirect) SBB. That is,
10970 * <PRE>
10971 * dstReg -CF= (quad) [srcBase]
10972 * </PRE>
10973 *
10974 * @param dstReg the destination register
10975 * @param srcBase the source base register
10976 */
10977 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10978 public final void emitSBB_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
10979 int miStart = mi;
10980 // no group 1 to 4 prefix byte
10981 generateREXprefix(true, dstReg, null, srcBase);
10982 // single byte opcode
10983 setMachineCodes(mi++, (byte) 0x1B);
10984 emitRegIndirectRegOperands(srcBase, dstReg);
10985 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
10986 }
10987
10988 /**
10989 * Generate a register(indirect)--register SBB. That is,
10990 * <PRE>
10991 * [dstBase] -CF= (byte) srcReg
10992 * </PRE>
10993 *
10994 * @param dstBase the destination base
10995 * @param srcReg the source register
10996 */
10997 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10998 public final void emitSBB_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
10999 int miStart = mi;
11000 // no group 1 to 4 prefix byte
11001 generateREXprefix(false, srcReg, null, dstBase);
11002 // single byte opcode
11003 setMachineCodes(mi++, (byte) 0x18);
11004 emitRegIndirectRegOperands(dstBase, srcReg);
11005 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
11006 }
11007
11008 /**
11009 * Generate a register-offset--register SBB. That is,
11010 * <PRE>
11011 * [dstReg<<dstScale + dstDisp] -CF= (byte) srcReg
11012 * </PRE>
11013 *
11014 * @param dstIndex the destination index register
11015 * @param dstScale the destination shift amount
11016 * @param dstDisp the destination displacement
11017 * @param srcReg the source register
11018 */
11019 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
11020 public final void emitSBB_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11021 int miStart = mi;
11022 // no group 1 to 4 prefix byte
11023 generateREXprefix(false, srcReg, dstIndex, null);
11024 // single byte opcode
11025 setMachineCodes(mi++, (byte) 0x18);
11026 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
11027 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
11028 }
11029
11030 /**
11031 * Generate a absolute--register SBB. That is,
11032 * <PRE>
11033 * [dstDisp] -CF= (byte) srcReg
11034 * </PRE>
11035 *
11036 * @param dstDisp the destination address
11037 * @param srcReg the source register
11038 */
11039 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
11040 public final void emitSBB_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
11041 int miStart = mi;
11042 // no group 1 to 4 prefix byte
11043 generateREXprefix(false, srcReg, null, null);
11044 // single byte opcode
11045 setMachineCodes(mi++, (byte) 0x18);
11046 emitAbsRegOperands(dstDisp, srcReg);
11047 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
11048 }
11049
11050 /**
11051 * Generate a register-index--register SBB. That is,
11052 * <PRE>
11053 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (byte) srcReg
11054 * </PRE>
11055 *
11056 * @param dstBase the base register
11057 * @param dstIndex the destination index register
11058 * @param dstScale the destination shift amount
11059 * @param dstDisp the destination displacement
11060 * @param srcReg the source register
11061 */
11062 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
11063 public final void emitSBB_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11064 int miStart = mi;
11065 // no group 1 to 4 prefix byte
11066 generateREXprefix(false, srcReg, dstIndex, dstBase);
11067 // single byte opcode
11068 setMachineCodes(mi++, (byte) 0x18);
11069 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
11070 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
11071 }
11072
11073 /**
11074 * Generate a register-displacement--register SBB. That is,
11075 * <PRE>
11076 * [dstBase + dstDisp] -CF= (byte) srcReg
11077 * </PRE>
11078 *
11079 * @param dstBase the base register
11080 * @param dstDisp the destination displacement
11081 * @param srcReg the source register
11082 */
11083 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
11084 public final void emitSBB_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
11085 int miStart = mi;
11086 // no group 1 to 4 prefix byte
11087 generateREXprefix(false, srcReg, null, dstBase);
11088 // single byte opcode
11089 setMachineCodes(mi++, (byte) 0x18);
11090 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
11091 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
11092 }
11093
11094 /**
11095 * Generate a register--register SBB. That is,
11096 * <PRE>
11097 * dstReg -CF= (byte) srcReg
11098 * </PRE>
11099 *
11100 * @param dstReg the destination register
11101 * @param srcReg the source register
11102 */
11103 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11104 public final void emitSBB_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
11105 int miStart = mi;
11106 // no group 1 to 4 prefix byte
11107 generateREXprefix(false, srcReg, null, dstReg);
11108 // single byte opcode
11109 setMachineCodes(mi++, (byte) 0x18);
11110 emitRegRegOperands(dstReg, srcReg);
11111 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
11112 }
11113
11114 /**
11115 * Generate a register--register-displacement SBB. That is,
11116 * <PRE>
11117 * dstReg -CF= (byte) [srcReg + srcDisp]
11118 * </PRE>
11119 *
11120 * @param dstReg the destination register
11121 * @param srcBase the source register
11122 * @param srcDisp the source displacement
11123 */
11124 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11125 public final void emitSBB_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
11126 int miStart = mi;
11127 // no group 1 to 4 prefix byte
11128 generateREXprefix(false, dstReg, null, srcBase);
11129 // single byte opcode
11130 setMachineCodes(mi++, (byte) 0x1A);
11131 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
11132 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
11133 }
11134
11135 /**
11136 * Generate a register--register-offset SBB. That is,
11137 * <PRE>
11138 * dstReg -CF= (byte) [srcIndex<<srcScale + srcDisp]
11139 * </PRE>
11140 *
11141 * @param dstReg the destination register
11142 * @param srcIndex the source index register
11143 * @param srcScale the source shift amount
11144 * @param srcDisp the source displacement
11145 */
11146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11147 public final void emitSBB_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
11148 int miStart = mi;
11149 // no group 1 to 4 prefix byte
11150 generateREXprefix(false, dstReg, srcIndex, null);
11151 // single byte opcode
11152 setMachineCodes(mi++, (byte) 0x1A);
11153 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
11154 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
11155 }
11156
11157 /**
11158 * Generate a register--register-offset SBB. That is,
11159 * <PRE>
11160 * dstReg -CF= (byte) [srcDisp]
11161 * </PRE>
11162 *
11163 * @param dstReg the destination register
11164 * @param srcDisp the source displacement
11165 */
11166 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11167 public final void emitSBB_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
11168 int miStart = mi;
11169 // no group 1 to 4 prefix byte
11170 generateREXprefix(false, dstReg, null, null);
11171 // single byte opcode
11172 setMachineCodes(mi++, (byte) 0x1A);
11173 emitAbsRegOperands(srcDisp, dstReg);
11174 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
11175 }
11176
11177 /**
11178 * Generate a register--register-offset SBB. That is,
11179 * <PRE>
11180 * dstReg -CF= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
11181 * </PRE>
11182 *
11183 * @param dstReg the destination register
11184 * @param srcBase the source base register
11185 * @param srcIndex the source index register
11186 * @param srcScale the source shift amount
11187 * @param srcDisp the source displacement
11188 */
11189 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
11190 public final void emitSBB_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
11191 int miStart = mi;
11192 // no group 1 to 4 prefix byte
11193 generateREXprefix(false, dstReg, srcIndex, srcBase);
11194 // single byte opcode
11195 setMachineCodes(mi++, (byte) 0x1A);
11196 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
11197 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
11198 }
11199
11200 /**
11201 * Generate a register--register(indirect) SBB. That is,
11202 * <PRE>
11203 * dstReg -CF= (byte) [srcBase]
11204 * </PRE>
11205 *
11206 * @param dstReg the destination register
11207 * @param srcBase the source base register
11208 */
11209 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11210 public final void emitSBB_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
11211 int miStart = mi;
11212 // no group 1 to 4 prefix byte
11213 generateREXprefix(false, dstReg, null, srcBase);
11214 // single byte opcode
11215 setMachineCodes(mi++, (byte) 0x1A);
11216 emitRegIndirectRegOperands(srcBase, dstReg);
11217 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
11218 }
11219
11220 /**
11221 * Generate a register--immediate SBB. That is,
11222 * <PRE>
11223 * dstReg -CF= imm
11224 * </PRE>
11225 *
11226 * @param dstReg the destination register
11227 * @param imm immediate
11228 */
11229 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11230 public final void emitSBB_Reg_Imm(GPR dstReg, int imm) {
11231 int miStart = mi;
11232 // no group 1 to 4 prefix byte
11233 generateREXprefix(false, null, null, dstReg);
11234 // single byte opcode
11235 if (fits(imm,8)) {
11236 setMachineCodes(mi++, (byte) 0x83);
11237 // "register 0x3" is really part of the opcode
11238 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11239 emitImm8((byte)imm);
11240 } else if (dstReg == EAX) {
11241 setMachineCodes(mi++, (byte) 0x1D);
11242 emitImm32(imm);
11243 } else {
11244 setMachineCodes(mi++, (byte) 0x81);
11245 // "register 0x3" is really part of the opcode
11246 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11247 emitImm32(imm);
11248 }
11249 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11250 }
11251
11252 /**
11253 * Generate a register-displacement--immediate SBB. That is,
11254 * <PRE>
11255 * [dstBase + dstDisp] -CF= imm
11256 * </PRE>
11257 *
11258 * @param dstBase the destination register
11259 * @param dstDisp the destination displacement
11260 * @param imm immediate
11261 */
11262 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11263 public final void emitSBB_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
11264 int miStart = mi;
11265 // no group 1 to 4 prefix byte
11266 generateREXprefix(false, null, null, dstBase);
11267 // single byte opcode
11268 if (fits(imm,8)) {
11269 setMachineCodes(mi++, (byte) 0x83);
11270 // "register 0x3" is really part of the opcode
11271 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11272 emitImm8((byte)imm);
11273 } else {
11274 setMachineCodes(mi++, (byte) 0x81);
11275 // "register 0x3" is really part of the opcode
11276 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11277 emitImm32(imm);
11278 }
11279 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11280 }
11281
11282 /**
11283 * Generate a register-offset--immediate SBB. That is,
11284 * <PRE>
11285 * [dstIndex<<dstScale + dstDisp] -CF= imm
11286 * </PRE>
11287 *
11288 * @param dstIndex the destination index register
11289 * @param dstScale the destination shift amount
11290 * @param dstDisp the destination displacement
11291 * @param imm immediate
11292 */
11293 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11294 public final void emitSBB_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11295 int miStart = mi;
11296 // no group 1 to 4 prefix byte
11297 generateREXprefix(false, null, dstIndex, null);
11298 // single byte opcode
11299 if (fits(imm,8)) {
11300 setMachineCodes(mi++, (byte) 0x83);
11301 // "register 0x3" is really part of the opcode
11302 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11303 emitImm8((byte)imm);
11304 } else {
11305 setMachineCodes(mi++, (byte) 0x81);
11306 // "register 0x3" is really part of the opcode
11307 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11308 emitImm32(imm);
11309 }
11310 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11311 }
11312
11313 /**
11314 * Generate a absolute--immediate SBB. That is,
11315 * <PRE>
11316 * [dstDisp] -CF= imm
11317 * </PRE>
11318 *
11319 * @param dstDisp the destination displacement
11320 * @param imm immediate
11321 */
11322 public final void emitSBB_Abs_Imm(Address dstDisp, int imm) {
11323 int miStart = mi;
11324 // no group 1 to 4 prefix byte
11325 generateREXprefix(false, null, null, null);
11326 // single byte opcode
11327 if (fits(imm,8)) {
11328 setMachineCodes(mi++, (byte) 0x83);
11329 // "register 0x3" is really part of the opcode
11330 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11331 emitImm8((byte)imm);
11332 } else {
11333 setMachineCodes(mi++, (byte) 0x81);
11334 // "register 0x3" is really part of the opcode
11335 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11336 emitImm32(imm);
11337 }
11338 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11339 }
11340
11341 /**
11342 * Generate a register-index--immediate SBB. That is,
11343 * <PRE>
11344 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= imm
11345 * </PRE>
11346 *
11347 * @param dstBase the destination base register
11348 * @param dstIndex the destination index register
11349 * @param dstScale the destination shift amount
11350 * @param dstDisp the destination displacement
11351 * @param imm immediate
11352 */
11353 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11354 public final void emitSBB_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11355 int miStart = mi;
11356 // no group 1 to 4 prefix byte
11357 generateREXprefix(false, null, dstIndex, dstBase);
11358 // single byte opcode
11359 if (fits(imm,8)) {
11360 setMachineCodes(mi++, (byte) 0x83);
11361 // "register 0x3" is really part of the opcode
11362 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11363 emitImm8((byte)imm);
11364 } else {
11365 setMachineCodes(mi++, (byte) 0x81);
11366 // "register 0x3" is really part of the opcode
11367 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11368 emitImm32(imm);
11369 }
11370 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11371 }
11372
11373 /**
11374 * Generate a register(indirect)--immediate SBB. That is,
11375 * <PRE>
11376 * [dstBase] -CF= imm
11377 * </PRE>
11378 *
11379 * @param dstBase the destination base register
11380 * @param imm immediate
11381 */
11382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11383 public final void emitSBB_RegInd_Imm(GPR dstBase, int imm) {
11384 int miStart = mi;
11385 // no group 1 to 4 prefix byte
11386 generateREXprefix(false, null, null, dstBase);
11387 // single byte opcode
11388 if (fits(imm,8)) {
11389 setMachineCodes(mi++, (byte) 0x83);
11390 // "register 0x3" is really part of the opcode
11391 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11392 emitImm8((byte)imm);
11393 } else {
11394 setMachineCodes(mi++, (byte) 0x81);
11395 // "register 0x3" is really part of the opcode
11396 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11397 emitImm32(imm);
11398 }
11399 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11400 }
11401
11402 /**
11403 * Generate a register--immediate SBB. That is,
11404 * <PRE>
11405 * dstReg -CF= (word) imm
11406 * </PRE>
11407 *
11408 * @param dstReg the destination register
11409 * @param imm immediate
11410 */
11411 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11412 public final void emitSBB_Reg_Imm_Word(GPR dstReg, int imm) {
11413 int miStart = mi;
11414 setMachineCodes(mi++, (byte) 0x66);
11415 generateREXprefix(false, null, null, dstReg);
11416 // single byte opcode
11417 if (fits(imm,8)) {
11418 setMachineCodes(mi++, (byte) 0x83);
11419 // "register 0x3" is really part of the opcode
11420 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11421 emitImm8((byte)imm);
11422 } else if (dstReg == EAX) {
11423 setMachineCodes(mi++, (byte) 0x1D);
11424 emitImm16(imm);
11425 } else {
11426 setMachineCodes(mi++, (byte) 0x81);
11427 // "register 0x3" is really part of the opcode
11428 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11429 emitImm16(imm);
11430 }
11431 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11432 }
11433
11434 /**
11435 * Generate a register-displacement--immediate SBB. That is,
11436 * <PRE>
11437 * [dstBase + dstDisp] -CF= (word) imm
11438 * </PRE>
11439 *
11440 * @param dstBase the destination register
11441 * @param dstDisp the destination displacement
11442 * @param imm immediate
11443 */
11444 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11445 public final void emitSBB_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
11446 int miStart = mi;
11447 setMachineCodes(mi++, (byte) 0x66);
11448 generateREXprefix(false, null, null, dstBase);
11449 // single byte opcode
11450 if (fits(imm,8)) {
11451 setMachineCodes(mi++, (byte) 0x83);
11452 // "register 0x3" is really part of the opcode
11453 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11454 emitImm8((byte)imm);
11455 } else {
11456 setMachineCodes(mi++, (byte) 0x81);
11457 // "register 0x3" is really part of the opcode
11458 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11459 emitImm16(imm);
11460 }
11461 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11462 }
11463
11464 /**
11465 * Generate a register-offset--immediate SBB. That is,
11466 * <PRE>
11467 * [dstIndex<<dstScale + dstDisp] -CF= (word) imm
11468 * </PRE>
11469 *
11470 * @param dstIndex the destination index register
11471 * @param dstScale the destination shift amount
11472 * @param dstDisp the destination displacement
11473 * @param imm immediate
11474 */
11475 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11476 public final void emitSBB_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11477 int miStart = mi;
11478 setMachineCodes(mi++, (byte) 0x66);
11479 generateREXprefix(false, null, dstIndex, null);
11480 // single byte opcode
11481 if (fits(imm,8)) {
11482 setMachineCodes(mi++, (byte) 0x83);
11483 // "register 0x3" is really part of the opcode
11484 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11485 emitImm8((byte)imm);
11486 } else {
11487 setMachineCodes(mi++, (byte) 0x81);
11488 // "register 0x3" is really part of the opcode
11489 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11490 emitImm16(imm);
11491 }
11492 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11493 }
11494
11495 /**
11496 * Generate a absolute--immediate SBB. That is,
11497 * <PRE>
11498 * [dstDisp] -CF= (word) imm
11499 * </PRE>
11500 *
11501 * @param dstDisp the destination displacement
11502 * @param imm immediate
11503 */
11504 public final void emitSBB_Abs_Imm_Word(Address dstDisp, int imm) {
11505 int miStart = mi;
11506 setMachineCodes(mi++, (byte) 0x66);
11507 generateREXprefix(false, null, null, null);
11508 // single byte opcode
11509 if (fits(imm,8)) {
11510 setMachineCodes(mi++, (byte) 0x83);
11511 // "register 0x3" is really part of the opcode
11512 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11513 emitImm8((byte)imm);
11514 } else {
11515 setMachineCodes(mi++, (byte) 0x81);
11516 // "register 0x3" is really part of the opcode
11517 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11518 emitImm16(imm);
11519 }
11520 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11521 }
11522
11523 /**
11524 * Generate a register-index--immediate SBB. That is,
11525 * <PRE>
11526 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (word) imm
11527 * </PRE>
11528 *
11529 * @param dstBase the destination base register
11530 * @param dstIndex the destination index register
11531 * @param dstScale the destination shift amount
11532 * @param dstDisp the destination displacement
11533 * @param imm immediate
11534 */
11535 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11536 public final void emitSBB_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11537 int miStart = mi;
11538 setMachineCodes(mi++, (byte) 0x66);
11539 generateREXprefix(false, null, dstIndex, dstBase);
11540 // single byte opcode
11541 if (fits(imm,8)) {
11542 setMachineCodes(mi++, (byte) 0x83);
11543 // "register 0x3" is really part of the opcode
11544 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11545 emitImm8((byte)imm);
11546 } else {
11547 setMachineCodes(mi++, (byte) 0x81);
11548 // "register 0x3" is really part of the opcode
11549 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11550 emitImm16(imm);
11551 }
11552 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11553 }
11554
11555 /**
11556 * Generate a register(indirect)--immediate SBB. That is,
11557 * <PRE>
11558 * [dstBase] -CF= (word) imm
11559 * </PRE>
11560 *
11561 * @param dstBase the destination base register
11562 * @param imm immediate
11563 */
11564 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11565 public final void emitSBB_RegInd_Imm_Word(GPR dstBase, int imm) {
11566 int miStart = mi;
11567 setMachineCodes(mi++, (byte) 0x66);
11568 generateREXprefix(false, null, null, dstBase);
11569 // single byte opcode
11570 if (fits(imm,8)) {
11571 setMachineCodes(mi++, (byte) 0x83);
11572 // "register 0x3" is really part of the opcode
11573 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11574 emitImm8((byte)imm);
11575 } else {
11576 setMachineCodes(mi++, (byte) 0x81);
11577 // "register 0x3" is really part of the opcode
11578 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11579 emitImm16(imm);
11580 }
11581 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11582 }
11583
11584 /**
11585 * Generate a register--immediate SBB. That is,
11586 * <PRE>
11587 * dstReg -CF= (quad) imm
11588 * </PRE>
11589 *
11590 * @param dstReg the destination register
11591 * @param imm immediate
11592 */
11593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11594 public final void emitSBB_Reg_Imm_Quad(GPR dstReg, int imm) {
11595 int miStart = mi;
11596 // no group 1 to 4 prefix byte
11597 generateREXprefix(true, null, null, dstReg);
11598 // single byte opcode
11599 if (fits(imm,8)) {
11600 setMachineCodes(mi++, (byte) 0x83);
11601 // "register 0x3" is really part of the opcode
11602 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11603 emitImm8((byte)imm);
11604 } else if (dstReg == EAX) {
11605 setMachineCodes(mi++, (byte) 0x1D);
11606 emitImm32(imm);
11607 } else {
11608 setMachineCodes(mi++, (byte) 0x81);
11609 // "register 0x3" is really part of the opcode
11610 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11611 emitImm32(imm);
11612 }
11613 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11614 }
11615
11616 /**
11617 * Generate a register-displacement--immediate SBB. That is,
11618 * <PRE>
11619 * [dstBase + dstDisp] -CF= (quad) imm
11620 * </PRE>
11621 *
11622 * @param dstBase the destination register
11623 * @param dstDisp the destination displacement
11624 * @param imm immediate
11625 */
11626 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11627 public final void emitSBB_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
11628 int miStart = mi;
11629 // no group 1 to 4 prefix byte
11630 generateREXprefix(true, null, null, dstBase);
11631 // single byte opcode
11632 if (fits(imm,8)) {
11633 setMachineCodes(mi++, (byte) 0x83);
11634 // "register 0x3" is really part of the opcode
11635 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11636 emitImm8((byte)imm);
11637 } else {
11638 setMachineCodes(mi++, (byte) 0x81);
11639 // "register 0x3" is really part of the opcode
11640 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11641 emitImm32(imm);
11642 }
11643 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11644 }
11645
11646 /**
11647 * Generate a register-offset--immediate SBB. That is,
11648 * <PRE>
11649 * [dstIndex<<dstScale + dstDisp] -CF= (quad) imm
11650 * </PRE>
11651 *
11652 * @param dstIndex the destination index register
11653 * @param dstScale the destination shift amount
11654 * @param dstDisp the destination displacement
11655 * @param imm immediate
11656 */
11657 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11658 public final void emitSBB_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11659 int miStart = mi;
11660 // no group 1 to 4 prefix byte
11661 generateREXprefix(true, null, dstIndex, null);
11662 // single byte opcode
11663 if (fits(imm,8)) {
11664 setMachineCodes(mi++, (byte) 0x83);
11665 // "register 0x3" is really part of the opcode
11666 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11667 emitImm8((byte)imm);
11668 } else {
11669 setMachineCodes(mi++, (byte) 0x81);
11670 // "register 0x3" is really part of the opcode
11671 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11672 emitImm32(imm);
11673 }
11674 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11675 }
11676
11677 /**
11678 * Generate a absolute--immediate SBB. That is,
11679 * <PRE>
11680 * [dstDisp] -CF= (quad) imm
11681 * </PRE>
11682 *
11683 * @param dstDisp the destination displacement
11684 * @param imm immediate
11685 */
11686 public final void emitSBB_Abs_Imm_Quad(Address dstDisp, int imm) {
11687 int miStart = mi;
11688 // no group 1 to 4 prefix byte
11689 generateREXprefix(true, null, null, null);
11690 // single byte opcode
11691 if (fits(imm,8)) {
11692 setMachineCodes(mi++, (byte) 0x83);
11693 // "register 0x3" is really part of the opcode
11694 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11695 emitImm8((byte)imm);
11696 } else {
11697 setMachineCodes(mi++, (byte) 0x81);
11698 // "register 0x3" is really part of the opcode
11699 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11700 emitImm32(imm);
11701 }
11702 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11703 }
11704
11705 /**
11706 * Generate a register-index--immediate SBB. That is,
11707 * <PRE>
11708 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (quad) imm
11709 * </PRE>
11710 *
11711 * @param dstBase the destination base register
11712 * @param dstIndex the destination index register
11713 * @param dstScale the destination shift amount
11714 * @param dstDisp the destination displacement
11715 * @param imm immediate
11716 */
11717 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11718 public final void emitSBB_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11719 int miStart = mi;
11720 // no group 1 to 4 prefix byte
11721 generateREXprefix(true, null, dstIndex, dstBase);
11722 // single byte opcode
11723 if (fits(imm,8)) {
11724 setMachineCodes(mi++, (byte) 0x83);
11725 // "register 0x3" is really part of the opcode
11726 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11727 emitImm8((byte)imm);
11728 } else {
11729 setMachineCodes(mi++, (byte) 0x81);
11730 // "register 0x3" is really part of the opcode
11731 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11732 emitImm32(imm);
11733 }
11734 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11735 }
11736
11737 /**
11738 * Generate a register(indirect)--immediate SBB. That is,
11739 * <PRE>
11740 * [dstBase] -CF= (quad) imm
11741 * </PRE>
11742 *
11743 * @param dstBase the destination base register
11744 * @param imm immediate
11745 */
11746 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11747 public final void emitSBB_RegInd_Imm_Quad(GPR dstBase, int imm) {
11748 int miStart = mi;
11749 // no group 1 to 4 prefix byte
11750 generateREXprefix(true, null, null, dstBase);
11751 // single byte opcode
11752 if (fits(imm,8)) {
11753 setMachineCodes(mi++, (byte) 0x83);
11754 // "register 0x3" is really part of the opcode
11755 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11756 emitImm8((byte)imm);
11757 } else {
11758 setMachineCodes(mi++, (byte) 0x81);
11759 // "register 0x3" is really part of the opcode
11760 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11761 emitImm32(imm);
11762 }
11763 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11764 }
11765
11766 /**
11767 * Generate a register--immediate SBB. That is,
11768 * <PRE>
11769 * dstReg -CF= (byte) imm
11770 * </PRE>
11771 *
11772 * @param dstReg the destination register
11773 * @param imm immediate
11774 */
11775 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11776 public final void emitSBB_Reg_Imm_Byte(GPR dstReg, int imm) {
11777 int miStart = mi;
11778 if (dstReg == EAX) {
11779 setMachineCodes(mi++, (byte) 0x1C);
11780 emitImm8(imm);
11781 } else {
11782 generateREXprefix(false, null, null, dstReg);
11783 setMachineCodes(mi++, (byte) 0x80);
11784 // "register 0x3" is really part of the opcode
11785 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11786 emitImm8(imm);
11787 }
11788 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11789 }
11790
11791 /**
11792 * Generate a register-displacement--immediate SBB. That is,
11793 * <PRE>
11794 * [dstBase + dstDisp] -CF= (byte) imm
11795 * </PRE>
11796 *
11797 * @param dstBase the destination register
11798 * @param dstDisp the destination displacement
11799 * @param imm immediate
11800 */
11801 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11802 public final void emitSBB_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
11803 int miStart = mi;
11804 generateREXprefix(false, null, null, dstBase);
11805 setMachineCodes(mi++, (byte) 0x80);
11806 // "register 0x3" is really part of the opcode
11807 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11808 emitImm8(imm);
11809 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11810 }
11811
11812 /**
11813 * Generate a register-index--immediate SBB. That is,
11814 * <PRE>
11815 * [dstBase + dstIndex<<scale + dstDisp] -CF= (byte) imm
11816 * </PRE>
11817 *
11818 * @param dstBase the destination base register
11819 * @param dstIndex the destination index register
11820 * @param dstScale the destination shift amount
11821 * @param dstDisp the destination displacement
11822 * @param imm immediate
11823 */
11824 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11825 public final void emitSBB_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11826 int miStart = mi;
11827 generateREXprefix(false, null, dstIndex, dstBase);
11828 setMachineCodes(mi++, (byte) 0x80);
11829 // "register 0x3" is really part of the opcode
11830 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11831 emitImm8(imm);
11832 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11833 }
11834
11835 /**
11836 * Generate a register-offset--immediate SBB. That is,
11837 * <PRE>
11838 * [dstIndex<<dstScale + dstDisp] -CF= (byte) imm
11839 * </PRE>
11840 *
11841 * @param dstIndex the destination index register
11842 * @param dstScale the destination shift amount
11843 * @param dstDisp the destination displacement
11844 * @param imm immediate
11845 */
11846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11847 public final void emitSBB_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11848 int miStart = mi;
11849 generateREXprefix(false, null, dstIndex, null);
11850 setMachineCodes(mi++, (byte) 0x80);
11851 // "register 0x3" is really part of the opcode
11852 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11853 emitImm8(imm);
11854 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11855 }
11856
11857 /**
11858 * Generate a absolute--immediate SBB. That is,
11859 * <PRE>
11860 * [dstDisp] -CF= (byte) imm
11861 * </PRE>
11862 *
11863 * @param dstDisp the destination displacement
11864 * @param imm immediate
11865 */
11866 public final void emitSBB_Abs_Imm_Byte(Address dstDisp, int imm) {
11867 int miStart = mi;
11868 generateREXprefix(false, null, null, null);
11869 setMachineCodes(mi++, (byte) 0x80);
11870 // "register 0x3" is really part of the opcode
11871 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11872 emitImm8(imm);
11873 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11874 }
11875
11876 /**
11877 * Generate a register(indirect)--immediate SBB. That is,
11878 * <PRE>
11879 * [dstBase] -CF= (byte) imm
11880 * </PRE>
11881 *
11882 * @param dstBase the destination base register
11883 * @param imm immediate
11884 */
11885 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11886 public final void emitSBB_RegInd_Imm_Byte(GPR dstBase, int imm) {
11887 int miStart = mi;
11888 generateREXprefix(false, null, null, dstBase);
11889 setMachineCodes(mi++, (byte) 0x80);
11890 // "register 0x3" is really part of the opcode
11891 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11892 emitImm8(imm);
11893 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11894 }
11895
11896 /**
11897 * Generate a register(indirect)--register SUB. That is,
11898 * <PRE>
11899 * [dstBase] -= srcReg
11900 * </PRE>
11901 *
11902 * @param dstBase the destination base
11903 * @param srcReg the source register
11904 */
11905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11906 public final void emitSUB_RegInd_Reg(GPR dstBase, GPR srcReg) {
11907 int miStart = mi;
11908 // no group 1 to 4 prefix byte
11909 generateREXprefix(false, srcReg, null, dstBase);
11910 // single byte opcode
11911 setMachineCodes(mi++, (byte) 0x29);
11912 emitRegIndirectRegOperands(dstBase, srcReg);
11913 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
11914 }
11915
11916 /**
11917 * Generate a register-offset--register SUB. That is,
11918 * <PRE>
11919 * [dstReg<<dstScale + dstDisp] -= srcReg
11920 * </PRE>
11921 *
11922 * @param dstIndex the destination index register
11923 * @param dstScale the destination shift amount
11924 * @param dstDisp the destination displacement
11925 * @param srcReg the source register
11926 */
11927 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
11928 public final void emitSUB_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11929 int miStart = mi;
11930 // no group 1 to 4 prefix byte
11931 generateREXprefix(false, srcReg, dstIndex, null);
11932 // single byte opcode
11933 setMachineCodes(mi++, (byte) 0x29);
11934 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
11935 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
11936 }
11937
11938 /**
11939 * Generate a absolute--register SUB. That is,
11940 * <PRE>
11941 * [dstDisp] -= srcReg
11942 * </PRE>
11943 *
11944 * @param dstDisp the destination address
11945 * @param srcReg the source register
11946 */
11947 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
11948 public final void emitSUB_Abs_Reg(Address dstDisp, GPR srcReg) {
11949 int miStart = mi;
11950 // no group 1 to 4 prefix byte
11951 generateREXprefix(false, srcReg, null, null);
11952 // single byte opcode
11953 setMachineCodes(mi++, (byte) 0x29);
11954 emitAbsRegOperands(dstDisp, srcReg);
11955 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
11956 }
11957
11958 /**
11959 * Generate a register-index--register SUB. That is,
11960 * <PRE>
11961 * [dstBase + dstIndex<<dstScale + dstDisp] -= srcReg
11962 * </PRE>
11963 *
11964 * @param dstBase the base register
11965 * @param dstIndex the destination index register
11966 * @param dstScale the destination shift amount
11967 * @param dstDisp the destination displacement
11968 * @param srcReg the source register
11969 */
11970 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
11971 public final void emitSUB_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11972 int miStart = mi;
11973 // no group 1 to 4 prefix byte
11974 generateREXprefix(false, srcReg, dstIndex, dstBase);
11975 // single byte opcode
11976 setMachineCodes(mi++, (byte) 0x29);
11977 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
11978 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
11979 }
11980
11981 /**
11982 * Generate a register-displacement--register SUB. That is,
11983 * <PRE>
11984 * [dstBase + dstDisp] -= srcReg
11985 * </PRE>
11986 *
11987 * @param dstBase the base register
11988 * @param dstDisp the destination displacement
11989 * @param srcReg the source register
11990 */
11991 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
11992 public final void emitSUB_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
11993 int miStart = mi;
11994 // no group 1 to 4 prefix byte
11995 generateREXprefix(false, srcReg, null, dstBase);
11996 // single byte opcode
11997 setMachineCodes(mi++, (byte) 0x29);
11998 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
11999 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12000 }
12001
12002 /**
12003 * Generate a register--register SUB. That is,
12004 * <PRE>
12005 * dstReg -= srcReg
12006 * </PRE>
12007 *
12008 * @param dstReg the destination register
12009 * @param srcReg the source register
12010 */
12011 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12012 public final void emitSUB_Reg_Reg(GPR dstReg, GPR srcReg) {
12013 int miStart = mi;
12014 // no group 1 to 4 prefix byte
12015 generateREXprefix(false, srcReg, null, dstReg);
12016 // single byte opcode
12017 setMachineCodes(mi++, (byte) 0x29);
12018 emitRegRegOperands(dstReg, srcReg);
12019 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12020 }
12021
12022 /**
12023 * Generate a register--register-displacement SUB. That is,
12024 * <PRE>
12025 * dstReg -= [srcReg + srcDisp]
12026 * </PRE>
12027 *
12028 * @param dstReg the destination register
12029 * @param srcBase the source register
12030 * @param srcDisp the source displacement
12031 */
12032 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12033 public final void emitSUB_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
12034 int miStart = mi;
12035 // no group 1 to 4 prefix byte
12036 generateREXprefix(false, dstReg, null, srcBase);
12037 // single byte opcode
12038 setMachineCodes(mi++, (byte) 0x2B);
12039 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12040 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12041 }
12042
12043 /**
12044 * Generate a register--register-offset SUB. That is,
12045 * <PRE>
12046 * dstReg -= [srcIndex<<srcScale + srcDisp]
12047 * </PRE>
12048 *
12049 * @param dstReg the destination register
12050 * @param srcIndex the source index register
12051 * @param srcScale the source shift amount
12052 * @param srcDisp the source displacement
12053 */
12054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12055 public final void emitSUB_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12056 int miStart = mi;
12057 // no group 1 to 4 prefix byte
12058 generateREXprefix(false, dstReg, srcIndex, null);
12059 // single byte opcode
12060 setMachineCodes(mi++, (byte) 0x2B);
12061 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12062 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12063 }
12064
12065 /**
12066 * Generate a register--register-offset SUB. That is,
12067 * <PRE>
12068 * dstReg -= [srcDisp]
12069 * </PRE>
12070 *
12071 * @param dstReg the destination register
12072 * @param srcDisp the source displacement
12073 */
12074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12075 public final void emitSUB_Reg_Abs(GPR dstReg, Address srcDisp) {
12076 int miStart = mi;
12077 // no group 1 to 4 prefix byte
12078 generateREXprefix(false, dstReg, null, null);
12079 // single byte opcode
12080 setMachineCodes(mi++, (byte) 0x2B);
12081 emitAbsRegOperands(srcDisp, dstReg);
12082 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12083 }
12084
12085 /**
12086 * Generate a register--register-offset SUB. That is,
12087 * <PRE>
12088 * dstReg -= [srcBase + srcIndex<<srcScale + srcDisp]
12089 * </PRE>
12090 *
12091 * @param dstReg the destination register
12092 * @param srcBase the source base register
12093 * @param srcIndex the source index register
12094 * @param srcScale the source shift amount
12095 * @param srcDisp the source displacement
12096 */
12097 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12098 public final void emitSUB_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12099 int miStart = mi;
12100 // no group 1 to 4 prefix byte
12101 generateREXprefix(false, dstReg, srcIndex, srcBase);
12102 // single byte opcode
12103 setMachineCodes(mi++, (byte) 0x2B);
12104 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12105 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12106 }
12107
12108 /**
12109 * Generate a register--register(indirect) SUB. That is,
12110 * <PRE>
12111 * dstReg -= [srcBase]
12112 * </PRE>
12113 *
12114 * @param dstReg the destination register
12115 * @param srcBase the source base register
12116 */
12117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12118 public final void emitSUB_Reg_RegInd(GPR dstReg, GPR srcBase) {
12119 int miStart = mi;
12120 // no group 1 to 4 prefix byte
12121 generateREXprefix(false, dstReg, null, srcBase);
12122 // single byte opcode
12123 setMachineCodes(mi++, (byte) 0x2B);
12124 emitRegIndirectRegOperands(srcBase, dstReg);
12125 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12126 }
12127
12128 /**
12129 * Generate a register(indirect)--register SUB. That is,
12130 * <PRE>
12131 * [dstBase] -= (word) srcReg
12132 * </PRE>
12133 *
12134 * @param dstBase the destination base
12135 * @param srcReg the source register
12136 */
12137 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12138 public final void emitSUB_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
12139 int miStart = mi;
12140 setMachineCodes(mi++, (byte) 0x66);
12141 generateREXprefix(false, srcReg, null, dstBase);
12142 // single byte opcode
12143 setMachineCodes(mi++, (byte) 0x29);
12144 emitRegIndirectRegOperands(dstBase, srcReg);
12145 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12146 }
12147
12148 /**
12149 * Generate a register-offset--register SUB. That is,
12150 * <PRE>
12151 * [dstReg<<dstScale + dstDisp] -= (word) srcReg
12152 * </PRE>
12153 *
12154 * @param dstIndex the destination index register
12155 * @param dstScale the destination shift amount
12156 * @param dstDisp the destination displacement
12157 * @param srcReg the source register
12158 */
12159 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12160 public final void emitSUB_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12161 int miStart = mi;
12162 setMachineCodes(mi++, (byte) 0x66);
12163 generateREXprefix(false, srcReg, dstIndex, null);
12164 // single byte opcode
12165 setMachineCodes(mi++, (byte) 0x29);
12166 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12167 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12168 }
12169
12170 /**
12171 * Generate a absolute--register SUB. That is,
12172 * <PRE>
12173 * [dstDisp] -= (word) srcReg
12174 * </PRE>
12175 *
12176 * @param dstDisp the destination address
12177 * @param srcReg the source register
12178 */
12179 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12180 public final void emitSUB_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
12181 int miStart = mi;
12182 setMachineCodes(mi++, (byte) 0x66);
12183 generateREXprefix(false, srcReg, null, null);
12184 // single byte opcode
12185 setMachineCodes(mi++, (byte) 0x29);
12186 emitAbsRegOperands(dstDisp, srcReg);
12187 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12188 }
12189
12190 /**
12191 * Generate a register-index--register SUB. That is,
12192 * <PRE>
12193 * [dstBase + dstIndex<<dstScale + dstDisp] -= (word) srcReg
12194 * </PRE>
12195 *
12196 * @param dstBase the base register
12197 * @param dstIndex the destination index register
12198 * @param dstScale the destination shift amount
12199 * @param dstDisp the destination displacement
12200 * @param srcReg the source register
12201 */
12202 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12203 public final void emitSUB_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12204 int miStart = mi;
12205 setMachineCodes(mi++, (byte) 0x66);
12206 generateREXprefix(false, srcReg, dstIndex, dstBase);
12207 // single byte opcode
12208 setMachineCodes(mi++, (byte) 0x29);
12209 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12210 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12211 }
12212
12213 /**
12214 * Generate a register-displacement--register SUB. That is,
12215 * <PRE>
12216 * [dstBase + dstDisp] -= (word) srcReg
12217 * </PRE>
12218 *
12219 * @param dstBase the base register
12220 * @param dstDisp the destination displacement
12221 * @param srcReg the source register
12222 */
12223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12224 public final void emitSUB_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
12225 int miStart = mi;
12226 setMachineCodes(mi++, (byte) 0x66);
12227 generateREXprefix(false, srcReg, null, dstBase);
12228 // single byte opcode
12229 setMachineCodes(mi++, (byte) 0x29);
12230 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12231 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12232 }
12233
12234 /**
12235 * Generate a register--register SUB. That is,
12236 * <PRE>
12237 * dstReg -= (word) srcReg
12238 * </PRE>
12239 *
12240 * @param dstReg the destination register
12241 * @param srcReg the source register
12242 */
12243 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12244 public final void emitSUB_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
12245 int miStart = mi;
12246 setMachineCodes(mi++, (byte) 0x66);
12247 generateREXprefix(false, srcReg, null, dstReg);
12248 // single byte opcode
12249 setMachineCodes(mi++, (byte) 0x29);
12250 emitRegRegOperands(dstReg, srcReg);
12251 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12252 }
12253
12254 /**
12255 * Generate a register--register-displacement SUB. That is,
12256 * <PRE>
12257 * dstReg -= (word) [srcReg + srcDisp]
12258 * </PRE>
12259 *
12260 * @param dstReg the destination register
12261 * @param srcBase the source register
12262 * @param srcDisp the source displacement
12263 */
12264 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12265 public final void emitSUB_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
12266 int miStart = mi;
12267 setMachineCodes(mi++, (byte) 0x66);
12268 generateREXprefix(false, dstReg, null, srcBase);
12269 // single byte opcode
12270 setMachineCodes(mi++, (byte) 0x2B);
12271 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12272 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12273 }
12274
12275 /**
12276 * Generate a register--register-offset SUB. That is,
12277 * <PRE>
12278 * dstReg -= (word) [srcIndex<<srcScale + srcDisp]
12279 * </PRE>
12280 *
12281 * @param dstReg the destination register
12282 * @param srcIndex the source index register
12283 * @param srcScale the source shift amount
12284 * @param srcDisp the source displacement
12285 */
12286 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12287 public final void emitSUB_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12288 int miStart = mi;
12289 setMachineCodes(mi++, (byte) 0x66);
12290 generateREXprefix(false, dstReg, srcIndex, null);
12291 // single byte opcode
12292 setMachineCodes(mi++, (byte) 0x2B);
12293 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12294 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12295 }
12296
12297 /**
12298 * Generate a register--register-offset SUB. That is,
12299 * <PRE>
12300 * dstReg -= (word) [srcDisp]
12301 * </PRE>
12302 *
12303 * @param dstReg the destination register
12304 * @param srcDisp the source displacement
12305 */
12306 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12307 public final void emitSUB_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
12308 int miStart = mi;
12309 setMachineCodes(mi++, (byte) 0x66);
12310 generateREXprefix(false, dstReg, null, null);
12311 // single byte opcode
12312 setMachineCodes(mi++, (byte) 0x2B);
12313 emitAbsRegOperands(srcDisp, dstReg);
12314 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12315 }
12316
12317 /**
12318 * Generate a register--register-offset SUB. That is,
12319 * <PRE>
12320 * dstReg -= (word) [srcBase + srcIndex<<srcScale + srcDisp]
12321 * </PRE>
12322 *
12323 * @param dstReg the destination register
12324 * @param srcBase the source base register
12325 * @param srcIndex the source index register
12326 * @param srcScale the source shift amount
12327 * @param srcDisp the source displacement
12328 */
12329 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12330 public final void emitSUB_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12331 int miStart = mi;
12332 setMachineCodes(mi++, (byte) 0x66);
12333 generateREXprefix(false, dstReg, srcIndex, srcBase);
12334 // single byte opcode
12335 setMachineCodes(mi++, (byte) 0x2B);
12336 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12337 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12338 }
12339
12340 /**
12341 * Generate a register--register(indirect) SUB. That is,
12342 * <PRE>
12343 * dstReg -= (word) [srcBase]
12344 * </PRE>
12345 *
12346 * @param dstReg the destination register
12347 * @param srcBase the source base register
12348 */
12349 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12350 public final void emitSUB_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
12351 int miStart = mi;
12352 setMachineCodes(mi++, (byte) 0x66);
12353 generateREXprefix(false, dstReg, null, srcBase);
12354 // single byte opcode
12355 setMachineCodes(mi++, (byte) 0x2B);
12356 emitRegIndirectRegOperands(srcBase, dstReg);
12357 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12358 }
12359
12360 /**
12361 * Generate a register(indirect)--register SUB. That is,
12362 * <PRE>
12363 * [dstBase] -= (quad) srcReg
12364 * </PRE>
12365 *
12366 * @param dstBase the destination base
12367 * @param srcReg the source register
12368 */
12369 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12370 public final void emitSUB_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
12371 int miStart = mi;
12372 // no group 1 to 4 prefix byte
12373 generateREXprefix(true, srcReg, null, dstBase);
12374 // single byte opcode
12375 setMachineCodes(mi++, (byte) 0x29);
12376 emitRegIndirectRegOperands(dstBase, srcReg);
12377 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12378 }
12379
12380 /**
12381 * Generate a register-offset--register SUB. That is,
12382 * <PRE>
12383 * [dstReg<<dstScale + dstDisp] -= (quad) srcReg
12384 * </PRE>
12385 *
12386 * @param dstIndex the destination index register
12387 * @param dstScale the destination shift amount
12388 * @param dstDisp the destination displacement
12389 * @param srcReg the source register
12390 */
12391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12392 public final void emitSUB_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12393 int miStart = mi;
12394 // no group 1 to 4 prefix byte
12395 generateREXprefix(true, srcReg, dstIndex, null);
12396 // single byte opcode
12397 setMachineCodes(mi++, (byte) 0x29);
12398 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12399 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12400 }
12401
12402 /**
12403 * Generate a absolute--register SUB. That is,
12404 * <PRE>
12405 * [dstDisp] -= (quad) srcReg
12406 * </PRE>
12407 *
12408 * @param dstDisp the destination address
12409 * @param srcReg the source register
12410 */
12411 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12412 public final void emitSUB_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
12413 int miStart = mi;
12414 // no group 1 to 4 prefix byte
12415 generateREXprefix(true, srcReg, null, null);
12416 // single byte opcode
12417 setMachineCodes(mi++, (byte) 0x29);
12418 emitAbsRegOperands(dstDisp, srcReg);
12419 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12420 }
12421
12422 /**
12423 * Generate a register-index--register SUB. That is,
12424 * <PRE>
12425 * [dstBase + dstIndex<<dstScale + dstDisp] -= (quad) srcReg
12426 * </PRE>
12427 *
12428 * @param dstBase the base register
12429 * @param dstIndex the destination index register
12430 * @param dstScale the destination shift amount
12431 * @param dstDisp the destination displacement
12432 * @param srcReg the source register
12433 */
12434 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12435 public final void emitSUB_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12436 int miStart = mi;
12437 // no group 1 to 4 prefix byte
12438 generateREXprefix(true, srcReg, dstIndex, dstBase);
12439 // single byte opcode
12440 setMachineCodes(mi++, (byte) 0x29);
12441 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12442 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12443 }
12444
12445 /**
12446 * Generate a register-displacement--register SUB. That is,
12447 * <PRE>
12448 * [dstBase + dstDisp] -= (quad) srcReg
12449 * </PRE>
12450 *
12451 * @param dstBase the base register
12452 * @param dstDisp the destination displacement
12453 * @param srcReg the source register
12454 */
12455 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12456 public final void emitSUB_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
12457 int miStart = mi;
12458 // no group 1 to 4 prefix byte
12459 generateREXprefix(true, srcReg, null, dstBase);
12460 // single byte opcode
12461 setMachineCodes(mi++, (byte) 0x29);
12462 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12463 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12464 }
12465
12466 /**
12467 * Generate a register--register SUB. That is,
12468 * <PRE>
12469 * dstReg -= (quad) srcReg
12470 * </PRE>
12471 *
12472 * @param dstReg the destination register
12473 * @param srcReg the source register
12474 */
12475 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12476 public final void emitSUB_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
12477 int miStart = mi;
12478 // no group 1 to 4 prefix byte
12479 generateREXprefix(true, srcReg, null, dstReg);
12480 // single byte opcode
12481 setMachineCodes(mi++, (byte) 0x29);
12482 emitRegRegOperands(dstReg, srcReg);
12483 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12484 }
12485
12486 /**
12487 * Generate a register--register-displacement SUB. That is,
12488 * <PRE>
12489 * dstReg -= (quad) [srcReg + srcDisp]
12490 * </PRE>
12491 *
12492 * @param dstReg the destination register
12493 * @param srcBase the source register
12494 * @param srcDisp the source displacement
12495 */
12496 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12497 public final void emitSUB_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
12498 int miStart = mi;
12499 // no group 1 to 4 prefix byte
12500 generateREXprefix(true, dstReg, null, srcBase);
12501 // single byte opcode
12502 setMachineCodes(mi++, (byte) 0x2B);
12503 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12504 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12505 }
12506
12507 /**
12508 * Generate a register--register-offset SUB. That is,
12509 * <PRE>
12510 * dstReg -= (quad) [srcIndex<<srcScale + srcDisp]
12511 * </PRE>
12512 *
12513 * @param dstReg the destination register
12514 * @param srcIndex the source index register
12515 * @param srcScale the source shift amount
12516 * @param srcDisp the source displacement
12517 */
12518 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12519 public final void emitSUB_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12520 int miStart = mi;
12521 // no group 1 to 4 prefix byte
12522 generateREXprefix(true, dstReg, srcIndex, null);
12523 // single byte opcode
12524 setMachineCodes(mi++, (byte) 0x2B);
12525 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12526 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12527 }
12528
12529 /**
12530 * Generate a register--register-offset SUB. That is,
12531 * <PRE>
12532 * dstReg -= (quad) [srcDisp]
12533 * </PRE>
12534 *
12535 * @param dstReg the destination register
12536 * @param srcDisp the source displacement
12537 */
12538 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12539 public final void emitSUB_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
12540 int miStart = mi;
12541 // no group 1 to 4 prefix byte
12542 generateREXprefix(true, dstReg, null, null);
12543 // single byte opcode
12544 setMachineCodes(mi++, (byte) 0x2B);
12545 emitAbsRegOperands(srcDisp, dstReg);
12546 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12547 }
12548
12549 /**
12550 * Generate a register--register-offset SUB. That is,
12551 * <PRE>
12552 * dstReg -= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
12553 * </PRE>
12554 *
12555 * @param dstReg the destination register
12556 * @param srcBase the source base register
12557 * @param srcIndex the source index register
12558 * @param srcScale the source shift amount
12559 * @param srcDisp the source displacement
12560 */
12561 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12562 public final void emitSUB_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12563 int miStart = mi;
12564 // no group 1 to 4 prefix byte
12565 generateREXprefix(true, dstReg, srcIndex, srcBase);
12566 // single byte opcode
12567 setMachineCodes(mi++, (byte) 0x2B);
12568 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12569 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12570 }
12571
12572 /**
12573 * Generate a register--register(indirect) SUB. That is,
12574 * <PRE>
12575 * dstReg -= (quad) [srcBase]
12576 * </PRE>
12577 *
12578 * @param dstReg the destination register
12579 * @param srcBase the source base register
12580 */
12581 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12582 public final void emitSUB_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
12583 int miStart = mi;
12584 // no group 1 to 4 prefix byte
12585 generateREXprefix(true, dstReg, null, srcBase);
12586 // single byte opcode
12587 setMachineCodes(mi++, (byte) 0x2B);
12588 emitRegIndirectRegOperands(srcBase, dstReg);
12589 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12590 }
12591
12592 /**
12593 * Generate a register(indirect)--register SUB. That is,
12594 * <PRE>
12595 * [dstBase] -= (byte) srcReg
12596 * </PRE>
12597 *
12598 * @param dstBase the destination base
12599 * @param srcReg the source register
12600 */
12601 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12602 public final void emitSUB_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
12603 int miStart = mi;
12604 // no group 1 to 4 prefix byte
12605 generateREXprefix(false, srcReg, null, dstBase);
12606 // single byte opcode
12607 setMachineCodes(mi++, (byte) 0x28);
12608 emitRegIndirectRegOperands(dstBase, srcReg);
12609 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12610 }
12611
12612 /**
12613 * Generate a register-offset--register SUB. That is,
12614 * <PRE>
12615 * [dstReg<<dstScale + dstDisp] -= (byte) srcReg
12616 * </PRE>
12617 *
12618 * @param dstIndex the destination index register
12619 * @param dstScale the destination shift amount
12620 * @param dstDisp the destination displacement
12621 * @param srcReg the source register
12622 */
12623 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12624 public final void emitSUB_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12625 int miStart = mi;
12626 // no group 1 to 4 prefix byte
12627 generateREXprefix(false, srcReg, dstIndex, null);
12628 // single byte opcode
12629 setMachineCodes(mi++, (byte) 0x28);
12630 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12631 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12632 }
12633
12634 /**
12635 * Generate a absolute--register SUB. That is,
12636 * <PRE>
12637 * [dstDisp] -= (byte) srcReg
12638 * </PRE>
12639 *
12640 * @param dstDisp the destination address
12641 * @param srcReg the source register
12642 */
12643 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12644 public final void emitSUB_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
12645 int miStart = mi;
12646 // no group 1 to 4 prefix byte
12647 generateREXprefix(false, srcReg, null, null);
12648 // single byte opcode
12649 setMachineCodes(mi++, (byte) 0x28);
12650 emitAbsRegOperands(dstDisp, srcReg);
12651 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12652 }
12653
12654 /**
12655 * Generate a register-index--register SUB. That is,
12656 * <PRE>
12657 * [dstBase + dstIndex<<dstScale + dstDisp] -= (byte) srcReg
12658 * </PRE>
12659 *
12660 * @param dstBase the base register
12661 * @param dstIndex the destination index register
12662 * @param dstScale the destination shift amount
12663 * @param dstDisp the destination displacement
12664 * @param srcReg the source register
12665 */
12666 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12667 public final void emitSUB_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12668 int miStart = mi;
12669 // no group 1 to 4 prefix byte
12670 generateREXprefix(false, srcReg, dstIndex, dstBase);
12671 // single byte opcode
12672 setMachineCodes(mi++, (byte) 0x28);
12673 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12674 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12675 }
12676
12677 /**
12678 * Generate a register-displacement--register SUB. That is,
12679 * <PRE>
12680 * [dstBase + dstDisp] -= (byte) srcReg
12681 * </PRE>
12682 *
12683 * @param dstBase the base register
12684 * @param dstDisp the destination displacement
12685 * @param srcReg the source register
12686 */
12687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12688 public final void emitSUB_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
12689 int miStart = mi;
12690 // no group 1 to 4 prefix byte
12691 generateREXprefix(false, srcReg, null, dstBase);
12692 // single byte opcode
12693 setMachineCodes(mi++, (byte) 0x28);
12694 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12695 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12696 }
12697
12698 /**
12699 * Generate a register--register SUB. That is,
12700 * <PRE>
12701 * dstReg -= (byte) srcReg
12702 * </PRE>
12703 *
12704 * @param dstReg the destination register
12705 * @param srcReg the source register
12706 */
12707 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12708 public final void emitSUB_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
12709 int miStart = mi;
12710 // no group 1 to 4 prefix byte
12711 generateREXprefix(false, srcReg, null, dstReg);
12712 // single byte opcode
12713 setMachineCodes(mi++, (byte) 0x28);
12714 emitRegRegOperands(dstReg, srcReg);
12715 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12716 }
12717
12718 /**
12719 * Generate a register--register-displacement SUB. That is,
12720 * <PRE>
12721 * dstReg -= (byte) [srcReg + srcDisp]
12722 * </PRE>
12723 *
12724 * @param dstReg the destination register
12725 * @param srcBase the source register
12726 * @param srcDisp the source displacement
12727 */
12728 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12729 public final void emitSUB_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
12730 int miStart = mi;
12731 // no group 1 to 4 prefix byte
12732 generateREXprefix(false, dstReg, null, srcBase);
12733 // single byte opcode
12734 setMachineCodes(mi++, (byte) 0x2A);
12735 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12736 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12737 }
12738
12739 /**
12740 * Generate a register--register-offset SUB. That is,
12741 * <PRE>
12742 * dstReg -= (byte) [srcIndex<<srcScale + srcDisp]
12743 * </PRE>
12744 *
12745 * @param dstReg the destination register
12746 * @param srcIndex the source index register
12747 * @param srcScale the source shift amount
12748 * @param srcDisp the source displacement
12749 */
12750 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12751 public final void emitSUB_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12752 int miStart = mi;
12753 // no group 1 to 4 prefix byte
12754 generateREXprefix(false, dstReg, srcIndex, null);
12755 // single byte opcode
12756 setMachineCodes(mi++, (byte) 0x2A);
12757 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12758 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12759 }
12760
12761 /**
12762 * Generate a register--register-offset SUB. That is,
12763 * <PRE>
12764 * dstReg -= (byte) [srcDisp]
12765 * </PRE>
12766 *
12767 * @param dstReg the destination register
12768 * @param srcDisp the source displacement
12769 */
12770 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12771 public final void emitSUB_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
12772 int miStart = mi;
12773 // no group 1 to 4 prefix byte
12774 generateREXprefix(false, dstReg, null, null);
12775 // single byte opcode
12776 setMachineCodes(mi++, (byte) 0x2A);
12777 emitAbsRegOperands(srcDisp, dstReg);
12778 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12779 }
12780
12781 /**
12782 * Generate a register--register-offset SUB. That is,
12783 * <PRE>
12784 * dstReg -= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
12785 * </PRE>
12786 *
12787 * @param dstReg the destination register
12788 * @param srcBase the source base register
12789 * @param srcIndex the source index register
12790 * @param srcScale the source shift amount
12791 * @param srcDisp the source displacement
12792 */
12793 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12794 public final void emitSUB_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12795 int miStart = mi;
12796 // no group 1 to 4 prefix byte
12797 generateREXprefix(false, dstReg, srcIndex, srcBase);
12798 // single byte opcode
12799 setMachineCodes(mi++, (byte) 0x2A);
12800 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12801 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12802 }
12803
12804 /**
12805 * Generate a register--register(indirect) SUB. That is,
12806 * <PRE>
12807 * dstReg -= (byte) [srcBase]
12808 * </PRE>
12809 *
12810 * @param dstReg the destination register
12811 * @param srcBase the source base register
12812 */
12813 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12814 public final void emitSUB_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
12815 int miStart = mi;
12816 // no group 1 to 4 prefix byte
12817 generateREXprefix(false, dstReg, null, srcBase);
12818 // single byte opcode
12819 setMachineCodes(mi++, (byte) 0x2A);
12820 emitRegIndirectRegOperands(srcBase, dstReg);
12821 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12822 }
12823
12824 /**
12825 * Generate a register--immediate SUB. That is,
12826 * <PRE>
12827 * dstReg -= imm
12828 * </PRE>
12829 *
12830 * @param dstReg the destination register
12831 * @param imm immediate
12832 */
12833 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12834 public final void emitSUB_Reg_Imm(GPR dstReg, int imm) {
12835 int miStart = mi;
12836 // no group 1 to 4 prefix byte
12837 generateREXprefix(false, null, null, dstReg);
12838 // single byte opcode
12839 if (fits(imm,8)) {
12840 setMachineCodes(mi++, (byte) 0x83);
12841 // "register 0x5" is really part of the opcode
12842 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
12843 emitImm8((byte)imm);
12844 } else if (dstReg == EAX) {
12845 setMachineCodes(mi++, (byte) 0x2D);
12846 emitImm32(imm);
12847 } else {
12848 setMachineCodes(mi++, (byte) 0x81);
12849 // "register 0x5" is really part of the opcode
12850 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
12851 emitImm32(imm);
12852 }
12853 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
12854 }
12855
12856 /**
12857 * Generate a register-displacement--immediate SUB. That is,
12858 * <PRE>
12859 * [dstBase + dstDisp] -= imm
12860 * </PRE>
12861 *
12862 * @param dstBase the destination register
12863 * @param dstDisp the destination displacement
12864 * @param imm immediate
12865 */
12866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12867 public final void emitSUB_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
12868 int miStart = mi;
12869 // no group 1 to 4 prefix byte
12870 generateREXprefix(false, null, null, dstBase);
12871 // single byte opcode
12872 if (fits(imm,8)) {
12873 setMachineCodes(mi++, (byte) 0x83);
12874 // "register 0x5" is really part of the opcode
12875 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
12876 emitImm8((byte)imm);
12877 } else {
12878 setMachineCodes(mi++, (byte) 0x81);
12879 // "register 0x5" is really part of the opcode
12880 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
12881 emitImm32(imm);
12882 }
12883 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
12884 }
12885
12886 /**
12887 * Generate a register-offset--immediate SUB. That is,
12888 * <PRE>
12889 * [dstIndex<<dstScale + dstDisp] -= imm
12890 * </PRE>
12891 *
12892 * @param dstIndex the destination index register
12893 * @param dstScale the destination shift amount
12894 * @param dstDisp the destination displacement
12895 * @param imm immediate
12896 */
12897 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12898 public final void emitSUB_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
12899 int miStart = mi;
12900 // no group 1 to 4 prefix byte
12901 generateREXprefix(false, null, dstIndex, null);
12902 // single byte opcode
12903 if (fits(imm,8)) {
12904 setMachineCodes(mi++, (byte) 0x83);
12905 // "register 0x5" is really part of the opcode
12906 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12907 emitImm8((byte)imm);
12908 } else {
12909 setMachineCodes(mi++, (byte) 0x81);
12910 // "register 0x5" is really part of the opcode
12911 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12912 emitImm32(imm);
12913 }
12914 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
12915 }
12916
12917 /**
12918 * Generate a absolute--immediate SUB. That is,
12919 * <PRE>
12920 * [dstDisp] -= imm
12921 * </PRE>
12922 *
12923 * @param dstDisp the destination displacement
12924 * @param imm immediate
12925 */
12926 public final void emitSUB_Abs_Imm(Address dstDisp, int imm) {
12927 int miStart = mi;
12928 // no group 1 to 4 prefix byte
12929 generateREXprefix(false, null, null, null);
12930 // single byte opcode
12931 if (fits(imm,8)) {
12932 setMachineCodes(mi++, (byte) 0x83);
12933 // "register 0x5" is really part of the opcode
12934 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
12935 emitImm8((byte)imm);
12936 } else {
12937 setMachineCodes(mi++, (byte) 0x81);
12938 // "register 0x5" is really part of the opcode
12939 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
12940 emitImm32(imm);
12941 }
12942 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
12943 }
12944
12945 /**
12946 * Generate a register-index--immediate SUB. That is,
12947 * <PRE>
12948 * [dstBase + dstIndex<<dstScale + dstDisp] -= imm
12949 * </PRE>
12950 *
12951 * @param dstBase the destination base register
12952 * @param dstIndex the destination index register
12953 * @param dstScale the destination shift amount
12954 * @param dstDisp the destination displacement
12955 * @param imm immediate
12956 */
12957 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12958 public final void emitSUB_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
12959 int miStart = mi;
12960 // no group 1 to 4 prefix byte
12961 generateREXprefix(false, null, dstIndex, dstBase);
12962 // single byte opcode
12963 if (fits(imm,8)) {
12964 setMachineCodes(mi++, (byte) 0x83);
12965 // "register 0x5" is really part of the opcode
12966 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12967 emitImm8((byte)imm);
12968 } else {
12969 setMachineCodes(mi++, (byte) 0x81);
12970 // "register 0x5" is really part of the opcode
12971 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12972 emitImm32(imm);
12973 }
12974 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
12975 }
12976
12977 /**
12978 * Generate a register(indirect)--immediate SUB. That is,
12979 * <PRE>
12980 * [dstBase] -= imm
12981 * </PRE>
12982 *
12983 * @param dstBase the destination base register
12984 * @param imm immediate
12985 */
12986 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12987 public final void emitSUB_RegInd_Imm(GPR dstBase, int imm) {
12988 int miStart = mi;
12989 // no group 1 to 4 prefix byte
12990 generateREXprefix(false, null, null, dstBase);
12991 // single byte opcode
12992 if (fits(imm,8)) {
12993 setMachineCodes(mi++, (byte) 0x83);
12994 // "register 0x5" is really part of the opcode
12995 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
12996 emitImm8((byte)imm);
12997 } else {
12998 setMachineCodes(mi++, (byte) 0x81);
12999 // "register 0x5" is really part of the opcode
13000 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13001 emitImm32(imm);
13002 }
13003 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13004 }
13005
13006 /**
13007 * Generate a register--immediate SUB. That is,
13008 * <PRE>
13009 * dstReg -= (word) imm
13010 * </PRE>
13011 *
13012 * @param dstReg the destination register
13013 * @param imm immediate
13014 */
13015 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13016 public final void emitSUB_Reg_Imm_Word(GPR dstReg, int imm) {
13017 int miStart = mi;
13018 setMachineCodes(mi++, (byte) 0x66);
13019 generateREXprefix(false, null, null, dstReg);
13020 // single byte opcode
13021 if (fits(imm,8)) {
13022 setMachineCodes(mi++, (byte) 0x83);
13023 // "register 0x5" is really part of the opcode
13024 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13025 emitImm8((byte)imm);
13026 } else if (dstReg == EAX) {
13027 setMachineCodes(mi++, (byte) 0x2D);
13028 emitImm16(imm);
13029 } else {
13030 setMachineCodes(mi++, (byte) 0x81);
13031 // "register 0x5" is really part of the opcode
13032 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13033 emitImm16(imm);
13034 }
13035 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13036 }
13037
13038 /**
13039 * Generate a register-displacement--immediate SUB. That is,
13040 * <PRE>
13041 * [dstBase + dstDisp] -= (word) imm
13042 * </PRE>
13043 *
13044 * @param dstBase the destination register
13045 * @param dstDisp the destination displacement
13046 * @param imm immediate
13047 */
13048 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13049 public final void emitSUB_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
13050 int miStart = mi;
13051 setMachineCodes(mi++, (byte) 0x66);
13052 generateREXprefix(false, null, null, dstBase);
13053 // single byte opcode
13054 if (fits(imm,8)) {
13055 setMachineCodes(mi++, (byte) 0x83);
13056 // "register 0x5" is really part of the opcode
13057 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13058 emitImm8((byte)imm);
13059 } else {
13060 setMachineCodes(mi++, (byte) 0x81);
13061 // "register 0x5" is really part of the opcode
13062 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13063 emitImm16(imm);
13064 }
13065 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13066 }
13067
13068 /**
13069 * Generate a register-offset--immediate SUB. That is,
13070 * <PRE>
13071 * [dstIndex<<dstScale + dstDisp] -= (word) imm
13072 * </PRE>
13073 *
13074 * @param dstIndex the destination index register
13075 * @param dstScale the destination shift amount
13076 * @param dstDisp the destination displacement
13077 * @param imm immediate
13078 */
13079 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13080 public final void emitSUB_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13081 int miStart = mi;
13082 setMachineCodes(mi++, (byte) 0x66);
13083 generateREXprefix(false, null, dstIndex, null);
13084 // single byte opcode
13085 if (fits(imm,8)) {
13086 setMachineCodes(mi++, (byte) 0x83);
13087 // "register 0x5" is really part of the opcode
13088 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13089 emitImm8((byte)imm);
13090 } else {
13091 setMachineCodes(mi++, (byte) 0x81);
13092 // "register 0x5" is really part of the opcode
13093 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13094 emitImm16(imm);
13095 }
13096 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13097 }
13098
13099 /**
13100 * Generate a absolute--immediate SUB. That is,
13101 * <PRE>
13102 * [dstDisp] -= (word) imm
13103 * </PRE>
13104 *
13105 * @param dstDisp the destination displacement
13106 * @param imm immediate
13107 */
13108 public final void emitSUB_Abs_Imm_Word(Address dstDisp, int imm) {
13109 int miStart = mi;
13110 setMachineCodes(mi++, (byte) 0x66);
13111 generateREXprefix(false, null, null, null);
13112 // single byte opcode
13113 if (fits(imm,8)) {
13114 setMachineCodes(mi++, (byte) 0x83);
13115 // "register 0x5" is really part of the opcode
13116 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13117 emitImm8((byte)imm);
13118 } else {
13119 setMachineCodes(mi++, (byte) 0x81);
13120 // "register 0x5" is really part of the opcode
13121 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13122 emitImm16(imm);
13123 }
13124 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13125 }
13126
13127 /**
13128 * Generate a register-index--immediate SUB. That is,
13129 * <PRE>
13130 * [dstBase + dstIndex<<dstScale + dstDisp] -= (word) imm
13131 * </PRE>
13132 *
13133 * @param dstBase the destination base register
13134 * @param dstIndex the destination index register
13135 * @param dstScale the destination shift amount
13136 * @param dstDisp the destination displacement
13137 * @param imm immediate
13138 */
13139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13140 public final void emitSUB_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13141 int miStart = mi;
13142 setMachineCodes(mi++, (byte) 0x66);
13143 generateREXprefix(false, null, dstIndex, dstBase);
13144 // single byte opcode
13145 if (fits(imm,8)) {
13146 setMachineCodes(mi++, (byte) 0x83);
13147 // "register 0x5" is really part of the opcode
13148 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13149 emitImm8((byte)imm);
13150 } else {
13151 setMachineCodes(mi++, (byte) 0x81);
13152 // "register 0x5" is really part of the opcode
13153 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13154 emitImm16(imm);
13155 }
13156 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13157 }
13158
13159 /**
13160 * Generate a register(indirect)--immediate SUB. That is,
13161 * <PRE>
13162 * [dstBase] -= (word) imm
13163 * </PRE>
13164 *
13165 * @param dstBase the destination base register
13166 * @param imm immediate
13167 */
13168 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13169 public final void emitSUB_RegInd_Imm_Word(GPR dstBase, int imm) {
13170 int miStart = mi;
13171 setMachineCodes(mi++, (byte) 0x66);
13172 generateREXprefix(false, null, null, dstBase);
13173 // single byte opcode
13174 if (fits(imm,8)) {
13175 setMachineCodes(mi++, (byte) 0x83);
13176 // "register 0x5" is really part of the opcode
13177 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13178 emitImm8((byte)imm);
13179 } else {
13180 setMachineCodes(mi++, (byte) 0x81);
13181 // "register 0x5" is really part of the opcode
13182 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13183 emitImm16(imm);
13184 }
13185 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13186 }
13187
13188 /**
13189 * Generate a register--immediate SUB. That is,
13190 * <PRE>
13191 * dstReg -= (quad) imm
13192 * </PRE>
13193 *
13194 * @param dstReg the destination register
13195 * @param imm immediate
13196 */
13197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13198 public final void emitSUB_Reg_Imm_Quad(GPR dstReg, int imm) {
13199 int miStart = mi;
13200 // no group 1 to 4 prefix byte
13201 generateREXprefix(true, null, null, dstReg);
13202 // single byte opcode
13203 if (fits(imm,8)) {
13204 setMachineCodes(mi++, (byte) 0x83);
13205 // "register 0x5" is really part of the opcode
13206 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13207 emitImm8((byte)imm);
13208 } else if (dstReg == EAX) {
13209 setMachineCodes(mi++, (byte) 0x2D);
13210 emitImm32(imm);
13211 } else {
13212 setMachineCodes(mi++, (byte) 0x81);
13213 // "register 0x5" is really part of the opcode
13214 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13215 emitImm32(imm);
13216 }
13217 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13218 }
13219
13220 /**
13221 * Generate a register-displacement--immediate SUB. That is,
13222 * <PRE>
13223 * [dstBase + dstDisp] -= (quad) imm
13224 * </PRE>
13225 *
13226 * @param dstBase the destination register
13227 * @param dstDisp the destination displacement
13228 * @param imm immediate
13229 */
13230 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13231 public final void emitSUB_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
13232 int miStart = mi;
13233 // no group 1 to 4 prefix byte
13234 generateREXprefix(true, null, null, dstBase);
13235 // single byte opcode
13236 if (fits(imm,8)) {
13237 setMachineCodes(mi++, (byte) 0x83);
13238 // "register 0x5" is really part of the opcode
13239 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13240 emitImm8((byte)imm);
13241 } else {
13242 setMachineCodes(mi++, (byte) 0x81);
13243 // "register 0x5" is really part of the opcode
13244 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13245 emitImm32(imm);
13246 }
13247 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13248 }
13249
13250 /**
13251 * Generate a register-offset--immediate SUB. That is,
13252 * <PRE>
13253 * [dstIndex<<dstScale + dstDisp] -= (quad) imm
13254 * </PRE>
13255 *
13256 * @param dstIndex the destination index register
13257 * @param dstScale the destination shift amount
13258 * @param dstDisp the destination displacement
13259 * @param imm immediate
13260 */
13261 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13262 public final void emitSUB_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13263 int miStart = mi;
13264 // no group 1 to 4 prefix byte
13265 generateREXprefix(true, null, dstIndex, null);
13266 // single byte opcode
13267 if (fits(imm,8)) {
13268 setMachineCodes(mi++, (byte) 0x83);
13269 // "register 0x5" is really part of the opcode
13270 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13271 emitImm8((byte)imm);
13272 } else {
13273 setMachineCodes(mi++, (byte) 0x81);
13274 // "register 0x5" is really part of the opcode
13275 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13276 emitImm32(imm);
13277 }
13278 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13279 }
13280
13281 /**
13282 * Generate a absolute--immediate SUB. That is,
13283 * <PRE>
13284 * [dstDisp] -= (quad) imm
13285 * </PRE>
13286 *
13287 * @param dstDisp the destination displacement
13288 * @param imm immediate
13289 */
13290 public final void emitSUB_Abs_Imm_Quad(Address dstDisp, int imm) {
13291 int miStart = mi;
13292 // no group 1 to 4 prefix byte
13293 generateREXprefix(true, null, null, null);
13294 // single byte opcode
13295 if (fits(imm,8)) {
13296 setMachineCodes(mi++, (byte) 0x83);
13297 // "register 0x5" is really part of the opcode
13298 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13299 emitImm8((byte)imm);
13300 } else {
13301 setMachineCodes(mi++, (byte) 0x81);
13302 // "register 0x5" is really part of the opcode
13303 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13304 emitImm32(imm);
13305 }
13306 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13307 }
13308
13309 /**
13310 * Generate a register-index--immediate SUB. That is,
13311 * <PRE>
13312 * [dstBase + dstIndex<<dstScale + dstDisp] -= (quad) imm
13313 * </PRE>
13314 *
13315 * @param dstBase the destination base register
13316 * @param dstIndex the destination index register
13317 * @param dstScale the destination shift amount
13318 * @param dstDisp the destination displacement
13319 * @param imm immediate
13320 */
13321 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13322 public final void emitSUB_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13323 int miStart = mi;
13324 // no group 1 to 4 prefix byte
13325 generateREXprefix(true, null, dstIndex, dstBase);
13326 // single byte opcode
13327 if (fits(imm,8)) {
13328 setMachineCodes(mi++, (byte) 0x83);
13329 // "register 0x5" is really part of the opcode
13330 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13331 emitImm8((byte)imm);
13332 } else {
13333 setMachineCodes(mi++, (byte) 0x81);
13334 // "register 0x5" is really part of the opcode
13335 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13336 emitImm32(imm);
13337 }
13338 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13339 }
13340
13341 /**
13342 * Generate a register(indirect)--immediate SUB. That is,
13343 * <PRE>
13344 * [dstBase] -= (quad) imm
13345 * </PRE>
13346 *
13347 * @param dstBase the destination base register
13348 * @param imm immediate
13349 */
13350 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13351 public final void emitSUB_RegInd_Imm_Quad(GPR dstBase, int imm) {
13352 int miStart = mi;
13353 // no group 1 to 4 prefix byte
13354 generateREXprefix(true, null, null, dstBase);
13355 // single byte opcode
13356 if (fits(imm,8)) {
13357 setMachineCodes(mi++, (byte) 0x83);
13358 // "register 0x5" is really part of the opcode
13359 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13360 emitImm8((byte)imm);
13361 } else {
13362 setMachineCodes(mi++, (byte) 0x81);
13363 // "register 0x5" is really part of the opcode
13364 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13365 emitImm32(imm);
13366 }
13367 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13368 }
13369
13370 /**
13371 * Generate a register--immediate SUB. That is,
13372 * <PRE>
13373 * dstReg -= (byte) imm
13374 * </PRE>
13375 *
13376 * @param dstReg the destination register
13377 * @param imm immediate
13378 */
13379 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13380 public final void emitSUB_Reg_Imm_Byte(GPR dstReg, int imm) {
13381 int miStart = mi;
13382 if (dstReg == EAX) {
13383 setMachineCodes(mi++, (byte) 0x2C);
13384 emitImm8(imm);
13385 } else {
13386 generateREXprefix(false, null, null, dstReg);
13387 setMachineCodes(mi++, (byte) 0x80);
13388 // "register 0x5" is really part of the opcode
13389 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13390 emitImm8(imm);
13391 }
13392 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13393 }
13394
13395 /**
13396 * Generate a register-displacement--immediate SUB. That is,
13397 * <PRE>
13398 * [dstBase + dstDisp] -= (byte) imm
13399 * </PRE>
13400 *
13401 * @param dstBase the destination register
13402 * @param dstDisp the destination displacement
13403 * @param imm immediate
13404 */
13405 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13406 public final void emitSUB_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
13407 int miStart = mi;
13408 generateREXprefix(false, null, null, dstBase);
13409 setMachineCodes(mi++, (byte) 0x80);
13410 // "register 0x5" is really part of the opcode
13411 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13412 emitImm8(imm);
13413 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13414 }
13415
13416 /**
13417 * Generate a register-index--immediate SUB. That is,
13418 * <PRE>
13419 * [dstBase + dstIndex<<scale + dstDisp] -= (byte) imm
13420 * </PRE>
13421 *
13422 * @param dstBase the destination base register
13423 * @param dstIndex the destination index register
13424 * @param dstScale the destination shift amount
13425 * @param dstDisp the destination displacement
13426 * @param imm immediate
13427 */
13428 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13429 public final void emitSUB_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13430 int miStart = mi;
13431 generateREXprefix(false, null, dstIndex, dstBase);
13432 setMachineCodes(mi++, (byte) 0x80);
13433 // "register 0x5" is really part of the opcode
13434 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13435 emitImm8(imm);
13436 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13437 }
13438
13439 /**
13440 * Generate a register-offset--immediate SUB. That is,
13441 * <PRE>
13442 * [dstIndex<<dstScale + dstDisp] -= (byte) imm
13443 * </PRE>
13444 *
13445 * @param dstIndex the destination index register
13446 * @param dstScale the destination shift amount
13447 * @param dstDisp the destination displacement
13448 * @param imm immediate
13449 */
13450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13451 public final void emitSUB_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13452 int miStart = mi;
13453 generateREXprefix(false, null, dstIndex, null);
13454 setMachineCodes(mi++, (byte) 0x80);
13455 // "register 0x5" is really part of the opcode
13456 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13457 emitImm8(imm);
13458 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13459 }
13460
13461 /**
13462 * Generate a absolute--immediate SUB. That is,
13463 * <PRE>
13464 * [dstDisp] -= (byte) imm
13465 * </PRE>
13466 *
13467 * @param dstDisp the destination displacement
13468 * @param imm immediate
13469 */
13470 public final void emitSUB_Abs_Imm_Byte(Address dstDisp, int imm) {
13471 int miStart = mi;
13472 generateREXprefix(false, null, null, null);
13473 setMachineCodes(mi++, (byte) 0x80);
13474 // "register 0x5" is really part of the opcode
13475 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13476 emitImm8(imm);
13477 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13478 }
13479
13480 /**
13481 * Generate a register(indirect)--immediate SUB. That is,
13482 * <PRE>
13483 * [dstBase] -= (byte) imm
13484 * </PRE>
13485 *
13486 * @param dstBase the destination base register
13487 * @param imm immediate
13488 */
13489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13490 public final void emitSUB_RegInd_Imm_Byte(GPR dstBase, int imm) {
13491 int miStart = mi;
13492 generateREXprefix(false, null, null, dstBase);
13493 setMachineCodes(mi++, (byte) 0x80);
13494 // "register 0x5" is really part of the opcode
13495 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13496 emitImm8(imm);
13497 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13498 }
13499
13500 /**
13501 * Generate a register(indirect)--register TEST. That is,
13502 * <PRE>
13503 * [dstBase] &= srcReg
13504 * </PRE>
13505 *
13506 * @param dstBase the destination base
13507 * @param srcReg the source register
13508 */
13509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13510 public final void emitTEST_RegInd_Reg(GPR dstBase, GPR srcReg) {
13511 int miStart = mi;
13512 // no group 1 to 4 prefix byte
13513 generateREXprefix(false, srcReg, null, dstBase);
13514 // single byte opcode
13515 setMachineCodes(mi++, (byte) 0x85);
13516 emitRegIndirectRegOperands(dstBase, srcReg);
13517 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13518 }
13519
13520 /**
13521 * Generate a register-offset--register TEST. That is,
13522 * <PRE>
13523 * [dstReg<<dstScale + dstDisp] &= srcReg
13524 * </PRE>
13525 *
13526 * @param dstIndex the destination index register
13527 * @param dstScale the destination shift amount
13528 * @param dstDisp the destination displacement
13529 * @param srcReg the source register
13530 */
13531 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13532 public final void emitTEST_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13533 int miStart = mi;
13534 // no group 1 to 4 prefix byte
13535 generateREXprefix(false, srcReg, dstIndex, null);
13536 // single byte opcode
13537 setMachineCodes(mi++, (byte) 0x85);
13538 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13539 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13540 }
13541
13542 /**
13543 * Generate a absolute--register TEST. That is,
13544 * <PRE>
13545 * [dstDisp] &= srcReg
13546 * </PRE>
13547 *
13548 * @param dstDisp the destination address
13549 * @param srcReg the source register
13550 */
13551 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13552 public final void emitTEST_Abs_Reg(Address dstDisp, GPR srcReg) {
13553 int miStart = mi;
13554 // no group 1 to 4 prefix byte
13555 generateREXprefix(false, srcReg, null, null);
13556 // single byte opcode
13557 setMachineCodes(mi++, (byte) 0x85);
13558 emitAbsRegOperands(dstDisp, srcReg);
13559 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13560 }
13561
13562 /**
13563 * Generate a register-index--register TEST. That is,
13564 * <PRE>
13565 * [dstBase + dstIndex<<dstScale + dstDisp] &= srcReg
13566 * </PRE>
13567 *
13568 * @param dstBase the base register
13569 * @param dstIndex the destination index register
13570 * @param dstScale the destination shift amount
13571 * @param dstDisp the destination displacement
13572 * @param srcReg the source register
13573 */
13574 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13575 public final void emitTEST_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13576 int miStart = mi;
13577 // no group 1 to 4 prefix byte
13578 generateREXprefix(false, srcReg, dstIndex, dstBase);
13579 // single byte opcode
13580 setMachineCodes(mi++, (byte) 0x85);
13581 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13582 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13583 }
13584
13585 /**
13586 * Generate a register-displacement--register TEST. That is,
13587 * <PRE>
13588 * [dstBase + dstDisp] &= srcReg
13589 * </PRE>
13590 *
13591 * @param dstBase the base register
13592 * @param dstDisp the destination displacement
13593 * @param srcReg the source register
13594 */
13595 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13596 public final void emitTEST_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
13597 int miStart = mi;
13598 // no group 1 to 4 prefix byte
13599 generateREXprefix(false, srcReg, null, dstBase);
13600 // single byte opcode
13601 setMachineCodes(mi++, (byte) 0x85);
13602 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13603 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13604 }
13605
13606 /**
13607 * Generate a register--register TEST. That is,
13608 * <PRE>
13609 * dstReg &= srcReg
13610 * </PRE>
13611 *
13612 * @param dstReg the destination register
13613 * @param srcReg the source register
13614 */
13615 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13616 public final void emitTEST_Reg_Reg(GPR dstReg, GPR srcReg) {
13617 int miStart = mi;
13618 // no group 1 to 4 prefix byte
13619 generateREXprefix(false, srcReg, null, dstReg);
13620 // single byte opcode
13621 setMachineCodes(mi++, (byte) 0x85);
13622 emitRegRegOperands(dstReg, srcReg);
13623 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13624 }
13625
13626 /**
13627 * Generate a register(indirect)--register TEST. That is,
13628 * <PRE>
13629 * [dstBase] &= (word) srcReg
13630 * </PRE>
13631 *
13632 * @param dstBase the destination base
13633 * @param srcReg the source register
13634 */
13635 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13636 public final void emitTEST_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
13637 int miStart = mi;
13638 setMachineCodes(mi++, (byte) 0x66);
13639 generateREXprefix(false, srcReg, null, dstBase);
13640 // single byte opcode
13641 setMachineCodes(mi++, (byte) 0x85);
13642 emitRegIndirectRegOperands(dstBase, srcReg);
13643 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13644 }
13645
13646 /**
13647 * Generate a register-offset--register TEST. That is,
13648 * <PRE>
13649 * [dstReg<<dstScale + dstDisp] &= (word) srcReg
13650 * </PRE>
13651 *
13652 * @param dstIndex the destination index register
13653 * @param dstScale the destination shift amount
13654 * @param dstDisp the destination displacement
13655 * @param srcReg the source register
13656 */
13657 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13658 public final void emitTEST_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13659 int miStart = mi;
13660 setMachineCodes(mi++, (byte) 0x66);
13661 generateREXprefix(false, srcReg, dstIndex, null);
13662 // single byte opcode
13663 setMachineCodes(mi++, (byte) 0x85);
13664 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13665 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13666 }
13667
13668 /**
13669 * Generate a absolute--register TEST. That is,
13670 * <PRE>
13671 * [dstDisp] &= (word) srcReg
13672 * </PRE>
13673 *
13674 * @param dstDisp the destination address
13675 * @param srcReg the source register
13676 */
13677 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13678 public final void emitTEST_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
13679 int miStart = mi;
13680 setMachineCodes(mi++, (byte) 0x66);
13681 generateREXprefix(false, srcReg, null, null);
13682 // single byte opcode
13683 setMachineCodes(mi++, (byte) 0x85);
13684 emitAbsRegOperands(dstDisp, srcReg);
13685 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13686 }
13687
13688 /**
13689 * Generate a register-index--register TEST. That is,
13690 * <PRE>
13691 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) srcReg
13692 * </PRE>
13693 *
13694 * @param dstBase the base register
13695 * @param dstIndex the destination index register
13696 * @param dstScale the destination shift amount
13697 * @param dstDisp the destination displacement
13698 * @param srcReg the source register
13699 */
13700 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13701 public final void emitTEST_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13702 int miStart = mi;
13703 setMachineCodes(mi++, (byte) 0x66);
13704 generateREXprefix(false, srcReg, dstIndex, dstBase);
13705 // single byte opcode
13706 setMachineCodes(mi++, (byte) 0x85);
13707 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13708 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13709 }
13710
13711 /**
13712 * Generate a register-displacement--register TEST. That is,
13713 * <PRE>
13714 * [dstBase + dstDisp] &= (word) srcReg
13715 * </PRE>
13716 *
13717 * @param dstBase the base register
13718 * @param dstDisp the destination displacement
13719 * @param srcReg the source register
13720 */
13721 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13722 public final void emitTEST_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
13723 int miStart = mi;
13724 setMachineCodes(mi++, (byte) 0x66);
13725 generateREXprefix(false, srcReg, null, dstBase);
13726 // single byte opcode
13727 setMachineCodes(mi++, (byte) 0x85);
13728 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13729 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13730 }
13731
13732 /**
13733 * Generate a register--register TEST. That is,
13734 * <PRE>
13735 * dstReg &= (word) srcReg
13736 * </PRE>
13737 *
13738 * @param dstReg the destination register
13739 * @param srcReg the source register
13740 */
13741 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13742 public final void emitTEST_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
13743 int miStart = mi;
13744 setMachineCodes(mi++, (byte) 0x66);
13745 generateREXprefix(false, srcReg, null, dstReg);
13746 // single byte opcode
13747 setMachineCodes(mi++, (byte) 0x85);
13748 emitRegRegOperands(dstReg, srcReg);
13749 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13750 }
13751
13752 /**
13753 * Generate a register(indirect)--register TEST. That is,
13754 * <PRE>
13755 * [dstBase] &= (quad) srcReg
13756 * </PRE>
13757 *
13758 * @param dstBase the destination base
13759 * @param srcReg the source register
13760 */
13761 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13762 public final void emitTEST_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
13763 int miStart = mi;
13764 // no group 1 to 4 prefix byte
13765 generateREXprefix(true, srcReg, null, dstBase);
13766 // single byte opcode
13767 setMachineCodes(mi++, (byte) 0x85);
13768 emitRegIndirectRegOperands(dstBase, srcReg);
13769 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13770 }
13771
13772 /**
13773 * Generate a register-offset--register TEST. That is,
13774 * <PRE>
13775 * [dstReg<<dstScale + dstDisp] &= (quad) srcReg
13776 * </PRE>
13777 *
13778 * @param dstIndex the destination index register
13779 * @param dstScale the destination shift amount
13780 * @param dstDisp the destination displacement
13781 * @param srcReg the source register
13782 */
13783 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13784 public final void emitTEST_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13785 int miStart = mi;
13786 // no group 1 to 4 prefix byte
13787 generateREXprefix(true, srcReg, dstIndex, null);
13788 // single byte opcode
13789 setMachineCodes(mi++, (byte) 0x85);
13790 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13791 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13792 }
13793
13794 /**
13795 * Generate a absolute--register TEST. That is,
13796 * <PRE>
13797 * [dstDisp] &= (quad) srcReg
13798 * </PRE>
13799 *
13800 * @param dstDisp the destination address
13801 * @param srcReg the source register
13802 */
13803 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13804 public final void emitTEST_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
13805 int miStart = mi;
13806 // no group 1 to 4 prefix byte
13807 generateREXprefix(true, srcReg, null, null);
13808 // single byte opcode
13809 setMachineCodes(mi++, (byte) 0x85);
13810 emitAbsRegOperands(dstDisp, srcReg);
13811 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13812 }
13813
13814 /**
13815 * Generate a register-index--register TEST. That is,
13816 * <PRE>
13817 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) srcReg
13818 * </PRE>
13819 *
13820 * @param dstBase the base register
13821 * @param dstIndex the destination index register
13822 * @param dstScale the destination shift amount
13823 * @param dstDisp the destination displacement
13824 * @param srcReg the source register
13825 */
13826 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13827 public final void emitTEST_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13828 int miStart = mi;
13829 // no group 1 to 4 prefix byte
13830 generateREXprefix(true, srcReg, dstIndex, dstBase);
13831 // single byte opcode
13832 setMachineCodes(mi++, (byte) 0x85);
13833 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13834 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13835 }
13836
13837 /**
13838 * Generate a register-displacement--register TEST. That is,
13839 * <PRE>
13840 * [dstBase + dstDisp] &= (quad) srcReg
13841 * </PRE>
13842 *
13843 * @param dstBase the base register
13844 * @param dstDisp the destination displacement
13845 * @param srcReg the source register
13846 */
13847 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13848 public final void emitTEST_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
13849 int miStart = mi;
13850 // no group 1 to 4 prefix byte
13851 generateREXprefix(true, srcReg, null, dstBase);
13852 // single byte opcode
13853 setMachineCodes(mi++, (byte) 0x85);
13854 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13855 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13856 }
13857
13858 /**
13859 * Generate a register--register TEST. That is,
13860 * <PRE>
13861 * dstReg &= (quad) srcReg
13862 * </PRE>
13863 *
13864 * @param dstReg the destination register
13865 * @param srcReg the source register
13866 */
13867 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13868 public final void emitTEST_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
13869 int miStart = mi;
13870 // no group 1 to 4 prefix byte
13871 generateREXprefix(true, srcReg, null, dstReg);
13872 // single byte opcode
13873 setMachineCodes(mi++, (byte) 0x85);
13874 emitRegRegOperands(dstReg, srcReg);
13875 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13876 }
13877
13878 /**
13879 * Generate a register(indirect)--register TEST. That is,
13880 * <PRE>
13881 * [dstBase] &= (byte) srcReg
13882 * </PRE>
13883 *
13884 * @param dstBase the destination base
13885 * @param srcReg the source register
13886 */
13887 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13888 public final void emitTEST_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
13889 int miStart = mi;
13890 // no group 1 to 4 prefix byte
13891 generateREXprefix(false, srcReg, null, dstBase);
13892 // single byte opcode
13893 setMachineCodes(mi++, (byte) 0x84);
13894 emitRegIndirectRegOperands(dstBase, srcReg);
13895 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13896 }
13897
13898 /**
13899 * Generate a register-offset--register TEST. That is,
13900 * <PRE>
13901 * [dstReg<<dstScale + dstDisp] &= (byte) srcReg
13902 * </PRE>
13903 *
13904 * @param dstIndex the destination index register
13905 * @param dstScale the destination shift amount
13906 * @param dstDisp the destination displacement
13907 * @param srcReg the source register
13908 */
13909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13910 public final void emitTEST_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13911 int miStart = mi;
13912 // no group 1 to 4 prefix byte
13913 generateREXprefix(false, srcReg, dstIndex, null);
13914 // single byte opcode
13915 setMachineCodes(mi++, (byte) 0x84);
13916 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13917 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13918 }
13919
13920 /**
13921 * Generate a absolute--register TEST. That is,
13922 * <PRE>
13923 * [dstDisp] &= (byte) srcReg
13924 * </PRE>
13925 *
13926 * @param dstDisp the destination address
13927 * @param srcReg the source register
13928 */
13929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13930 public final void emitTEST_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
13931 int miStart = mi;
13932 // no group 1 to 4 prefix byte
13933 generateREXprefix(false, srcReg, null, null);
13934 // single byte opcode
13935 setMachineCodes(mi++, (byte) 0x84);
13936 emitAbsRegOperands(dstDisp, srcReg);
13937 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13938 }
13939
13940 /**
13941 * Generate a register-index--register TEST. That is,
13942 * <PRE>
13943 * [dstBase + dstIndex<<dstScale + dstDisp] &= (byte) srcReg
13944 * </PRE>
13945 *
13946 * @param dstBase the base register
13947 * @param dstIndex the destination index register
13948 * @param dstScale the destination shift amount
13949 * @param dstDisp the destination displacement
13950 * @param srcReg the source register
13951 */
13952 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13953 public final void emitTEST_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13954 int miStart = mi;
13955 // no group 1 to 4 prefix byte
13956 generateREXprefix(false, srcReg, dstIndex, dstBase);
13957 // single byte opcode
13958 setMachineCodes(mi++, (byte) 0x84);
13959 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13960 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13961 }
13962
13963 /**
13964 * Generate a register-displacement--register TEST. That is,
13965 * <PRE>
13966 * [dstBase + dstDisp] &= (byte) srcReg
13967 * </PRE>
13968 *
13969 * @param dstBase the base register
13970 * @param dstDisp the destination displacement
13971 * @param srcReg the source register
13972 */
13973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13974 public final void emitTEST_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
13975 int miStart = mi;
13976 // no group 1 to 4 prefix byte
13977 generateREXprefix(false, srcReg, null, dstBase);
13978 // single byte opcode
13979 setMachineCodes(mi++, (byte) 0x84);
13980 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13981 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13982 }
13983
13984 /**
13985 * Generate a register--register TEST. That is,
13986 * <PRE>
13987 * dstReg &= (byte) srcReg
13988 * </PRE>
13989 *
13990 * @param dstReg the destination register
13991 * @param srcReg the source register
13992 */
13993 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13994 public final void emitTEST_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
13995 int miStart = mi;
13996 // no group 1 to 4 prefix byte
13997 generateREXprefix(false, srcReg, null, dstReg);
13998 // single byte opcode
13999 setMachineCodes(mi++, (byte) 0x84);
14000 emitRegRegOperands(dstReg, srcReg);
14001 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
14002 }
14003
14004 /**
14005 * Generate a register--immediate TEST. That is,
14006 * <PRE>
14007 * dstReg &= imm
14008 * </PRE>
14009 *
14010 * @param dstReg the destination register
14011 * @param imm immediate
14012 */
14013 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14014 public final void emitTEST_Reg_Imm(GPR dstReg, int imm) {
14015 int miStart = mi;
14016 // no group 1 to 4 prefix byte
14017 generateREXprefix(false, null, null, dstReg);
14018 // single byte opcode
14019 if (false) {
14020 } else if (dstReg == EAX) {
14021 setMachineCodes(mi++, (byte) 0xA9);
14022 emitImm32(imm);
14023 } else {
14024 setMachineCodes(mi++, (byte) 0xF7);
14025 // "register 0x0" is really part of the opcode
14026 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14027 emitImm32(imm);
14028 }
14029 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14030 }
14031
14032 /**
14033 * Generate a register-displacement--immediate TEST. That is,
14034 * <PRE>
14035 * [dstBase + dstDisp] &= imm
14036 * </PRE>
14037 *
14038 * @param dstBase the destination register
14039 * @param dstDisp the destination displacement
14040 * @param imm immediate
14041 */
14042 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14043 public final void emitTEST_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
14044 int miStart = mi;
14045 // no group 1 to 4 prefix byte
14046 generateREXprefix(false, null, null, dstBase);
14047 // single byte opcode
14048 if (false) {
14049 } else {
14050 setMachineCodes(mi++, (byte) 0xF7);
14051 // "register 0x0" is really part of the opcode
14052 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14053 emitImm32(imm);
14054 }
14055 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14056 }
14057
14058 /**
14059 * Generate a register-offset--immediate TEST. That is,
14060 * <PRE>
14061 * [dstIndex<<dstScale + dstDisp] &= imm
14062 * </PRE>
14063 *
14064 * @param dstIndex the destination index register
14065 * @param dstScale the destination shift amount
14066 * @param dstDisp the destination displacement
14067 * @param imm immediate
14068 */
14069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14070 public final void emitTEST_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14071 int miStart = mi;
14072 // no group 1 to 4 prefix byte
14073 generateREXprefix(false, null, dstIndex, null);
14074 // single byte opcode
14075 if (false) {
14076 } else {
14077 setMachineCodes(mi++, (byte) 0xF7);
14078 // "register 0x0" is really part of the opcode
14079 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14080 emitImm32(imm);
14081 }
14082 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14083 }
14084
14085 /**
14086 * Generate a absolute--immediate TEST. That is,
14087 * <PRE>
14088 * [dstDisp] &= imm
14089 * </PRE>
14090 *
14091 * @param dstDisp the destination displacement
14092 * @param imm immediate
14093 */
14094 public final void emitTEST_Abs_Imm(Address dstDisp, int imm) {
14095 int miStart = mi;
14096 // no group 1 to 4 prefix byte
14097 generateREXprefix(false, null, null, null);
14098 // single byte opcode
14099 if (false) {
14100 } else {
14101 setMachineCodes(mi++, (byte) 0xF7);
14102 // "register 0x0" is really part of the opcode
14103 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14104 emitImm32(imm);
14105 }
14106 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14107 }
14108
14109 /**
14110 * Generate a register-index--immediate TEST. That is,
14111 * <PRE>
14112 * [dstBase + dstIndex<<dstScale + dstDisp] &= imm
14113 * </PRE>
14114 *
14115 * @param dstBase the destination base register
14116 * @param dstIndex the destination index register
14117 * @param dstScale the destination shift amount
14118 * @param dstDisp the destination displacement
14119 * @param imm immediate
14120 */
14121 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14122 public final void emitTEST_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14123 int miStart = mi;
14124 // no group 1 to 4 prefix byte
14125 generateREXprefix(false, null, dstIndex, dstBase);
14126 // single byte opcode
14127 if (false) {
14128 } else {
14129 setMachineCodes(mi++, (byte) 0xF7);
14130 // "register 0x0" is really part of the opcode
14131 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14132 emitImm32(imm);
14133 }
14134 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14135 }
14136
14137 /**
14138 * Generate a register(indirect)--immediate TEST. That is,
14139 * <PRE>
14140 * [dstBase] &= imm
14141 * </PRE>
14142 *
14143 * @param dstBase the destination base register
14144 * @param imm immediate
14145 */
14146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14147 public final void emitTEST_RegInd_Imm(GPR dstBase, int imm) {
14148 int miStart = mi;
14149 // no group 1 to 4 prefix byte
14150 generateREXprefix(false, null, null, dstBase);
14151 // single byte opcode
14152 if (false) {
14153 } else {
14154 setMachineCodes(mi++, (byte) 0xF7);
14155 // "register 0x0" is really part of the opcode
14156 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14157 emitImm32(imm);
14158 }
14159 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14160 }
14161
14162 /**
14163 * Generate a register--immediate TEST. That is,
14164 * <PRE>
14165 * dstReg &= (word) imm
14166 * </PRE>
14167 *
14168 * @param dstReg the destination register
14169 * @param imm immediate
14170 */
14171 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14172 public final void emitTEST_Reg_Imm_Word(GPR dstReg, int imm) {
14173 int miStart = mi;
14174 setMachineCodes(mi++, (byte) 0x66);
14175 generateREXprefix(false, null, null, dstReg);
14176 // single byte opcode
14177 if (false) {
14178 } else if (dstReg == EAX) {
14179 setMachineCodes(mi++, (byte) 0xA9);
14180 emitImm16(imm);
14181 } else {
14182 setMachineCodes(mi++, (byte) 0xF7);
14183 // "register 0x0" is really part of the opcode
14184 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14185 emitImm16(imm);
14186 }
14187 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14188 }
14189
14190 /**
14191 * Generate a register-displacement--immediate TEST. That is,
14192 * <PRE>
14193 * [dstBase + dstDisp] &= (word) imm
14194 * </PRE>
14195 *
14196 * @param dstBase the destination register
14197 * @param dstDisp the destination displacement
14198 * @param imm immediate
14199 */
14200 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14201 public final void emitTEST_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
14202 int miStart = mi;
14203 setMachineCodes(mi++, (byte) 0x66);
14204 generateREXprefix(false, null, null, dstBase);
14205 // single byte opcode
14206 if (false) {
14207 } else {
14208 setMachineCodes(mi++, (byte) 0xF7);
14209 // "register 0x0" is really part of the opcode
14210 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14211 emitImm16(imm);
14212 }
14213 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14214 }
14215
14216 /**
14217 * Generate a register-offset--immediate TEST. That is,
14218 * <PRE>
14219 * [dstIndex<<dstScale + dstDisp] &= (word) imm
14220 * </PRE>
14221 *
14222 * @param dstIndex the destination index register
14223 * @param dstScale the destination shift amount
14224 * @param dstDisp the destination displacement
14225 * @param imm immediate
14226 */
14227 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14228 public final void emitTEST_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14229 int miStart = mi;
14230 setMachineCodes(mi++, (byte) 0x66);
14231 generateREXprefix(false, null, dstIndex, null);
14232 // single byte opcode
14233 if (false) {
14234 } else {
14235 setMachineCodes(mi++, (byte) 0xF7);
14236 // "register 0x0" is really part of the opcode
14237 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14238 emitImm16(imm);
14239 }
14240 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14241 }
14242
14243 /**
14244 * Generate a absolute--immediate TEST. That is,
14245 * <PRE>
14246 * [dstDisp] &= (word) imm
14247 * </PRE>
14248 *
14249 * @param dstDisp the destination displacement
14250 * @param imm immediate
14251 */
14252 public final void emitTEST_Abs_Imm_Word(Address dstDisp, int imm) {
14253 int miStart = mi;
14254 setMachineCodes(mi++, (byte) 0x66);
14255 generateREXprefix(false, null, null, null);
14256 // single byte opcode
14257 if (false) {
14258 } else {
14259 setMachineCodes(mi++, (byte) 0xF7);
14260 // "register 0x0" is really part of the opcode
14261 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14262 emitImm16(imm);
14263 }
14264 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14265 }
14266
14267 /**
14268 * Generate a register-index--immediate TEST. That is,
14269 * <PRE>
14270 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) imm
14271 * </PRE>
14272 *
14273 * @param dstBase the destination base register
14274 * @param dstIndex the destination index register
14275 * @param dstScale the destination shift amount
14276 * @param dstDisp the destination displacement
14277 * @param imm immediate
14278 */
14279 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14280 public final void emitTEST_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14281 int miStart = mi;
14282 setMachineCodes(mi++, (byte) 0x66);
14283 generateREXprefix(false, null, dstIndex, dstBase);
14284 // single byte opcode
14285 if (false) {
14286 } else {
14287 setMachineCodes(mi++, (byte) 0xF7);
14288 // "register 0x0" is really part of the opcode
14289 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14290 emitImm16(imm);
14291 }
14292 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14293 }
14294
14295 /**
14296 * Generate a register(indirect)--immediate TEST. That is,
14297 * <PRE>
14298 * [dstBase] &= (word) imm
14299 * </PRE>
14300 *
14301 * @param dstBase the destination base register
14302 * @param imm immediate
14303 */
14304 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14305 public final void emitTEST_RegInd_Imm_Word(GPR dstBase, int imm) {
14306 int miStart = mi;
14307 setMachineCodes(mi++, (byte) 0x66);
14308 generateREXprefix(false, null, null, dstBase);
14309 // single byte opcode
14310 if (false) {
14311 } else {
14312 setMachineCodes(mi++, (byte) 0xF7);
14313 // "register 0x0" is really part of the opcode
14314 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14315 emitImm16(imm);
14316 }
14317 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14318 }
14319
14320 /**
14321 * Generate a register--immediate TEST. That is,
14322 * <PRE>
14323 * dstReg &= (quad) imm
14324 * </PRE>
14325 *
14326 * @param dstReg the destination register
14327 * @param imm immediate
14328 */
14329 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14330 public final void emitTEST_Reg_Imm_Quad(GPR dstReg, int imm) {
14331 int miStart = mi;
14332 // no group 1 to 4 prefix byte
14333 generateREXprefix(true, null, null, dstReg);
14334 // single byte opcode
14335 if (false) {
14336 } else if (dstReg == EAX) {
14337 setMachineCodes(mi++, (byte) 0xA9);
14338 emitImm32(imm);
14339 } else {
14340 setMachineCodes(mi++, (byte) 0xF7);
14341 // "register 0x0" is really part of the opcode
14342 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14343 emitImm32(imm);
14344 }
14345 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14346 }
14347
14348 /**
14349 * Generate a register-displacement--immediate TEST. That is,
14350 * <PRE>
14351 * [dstBase + dstDisp] &= (quad) imm
14352 * </PRE>
14353 *
14354 * @param dstBase the destination register
14355 * @param dstDisp the destination displacement
14356 * @param imm immediate
14357 */
14358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14359 public final void emitTEST_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
14360 int miStart = mi;
14361 // no group 1 to 4 prefix byte
14362 generateREXprefix(true, null, null, dstBase);
14363 // single byte opcode
14364 if (false) {
14365 } else {
14366 setMachineCodes(mi++, (byte) 0xF7);
14367 // "register 0x0" is really part of the opcode
14368 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14369 emitImm32(imm);
14370 }
14371 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14372 }
14373
14374 /**
14375 * Generate a register-offset--immediate TEST. That is,
14376 * <PRE>
14377 * [dstIndex<<dstScale + dstDisp] &= (quad) imm
14378 * </PRE>
14379 *
14380 * @param dstIndex the destination index register
14381 * @param dstScale the destination shift amount
14382 * @param dstDisp the destination displacement
14383 * @param imm immediate
14384 */
14385 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14386 public final void emitTEST_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14387 int miStart = mi;
14388 // no group 1 to 4 prefix byte
14389 generateREXprefix(true, null, dstIndex, null);
14390 // single byte opcode
14391 if (false) {
14392 } else {
14393 setMachineCodes(mi++, (byte) 0xF7);
14394 // "register 0x0" is really part of the opcode
14395 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14396 emitImm32(imm);
14397 }
14398 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14399 }
14400
14401 /**
14402 * Generate a absolute--immediate TEST. That is,
14403 * <PRE>
14404 * [dstDisp] &= (quad) imm
14405 * </PRE>
14406 *
14407 * @param dstDisp the destination displacement
14408 * @param imm immediate
14409 */
14410 public final void emitTEST_Abs_Imm_Quad(Address dstDisp, int imm) {
14411 int miStart = mi;
14412 // no group 1 to 4 prefix byte
14413 generateREXprefix(true, null, null, null);
14414 // single byte opcode
14415 if (false) {
14416 } else {
14417 setMachineCodes(mi++, (byte) 0xF7);
14418 // "register 0x0" is really part of the opcode
14419 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14420 emitImm32(imm);
14421 }
14422 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14423 }
14424
14425 /**
14426 * Generate a register-index--immediate TEST. That is,
14427 * <PRE>
14428 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) imm
14429 * </PRE>
14430 *
14431 * @param dstBase the destination base register
14432 * @param dstIndex the destination index register
14433 * @param dstScale the destination shift amount
14434 * @param dstDisp the destination displacement
14435 * @param imm immediate
14436 */
14437 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14438 public final void emitTEST_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14439 int miStart = mi;
14440 // no group 1 to 4 prefix byte
14441 generateREXprefix(true, null, dstIndex, dstBase);
14442 // single byte opcode
14443 if (false) {
14444 } else {
14445 setMachineCodes(mi++, (byte) 0xF7);
14446 // "register 0x0" is really part of the opcode
14447 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14448 emitImm32(imm);
14449 }
14450 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14451 }
14452
14453 /**
14454 * Generate a register(indirect)--immediate TEST. That is,
14455 * <PRE>
14456 * [dstBase] &= (quad) imm
14457 * </PRE>
14458 *
14459 * @param dstBase the destination base register
14460 * @param imm immediate
14461 */
14462 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14463 public final void emitTEST_RegInd_Imm_Quad(GPR dstBase, int imm) {
14464 int miStart = mi;
14465 // no group 1 to 4 prefix byte
14466 generateREXprefix(true, null, null, dstBase);
14467 // single byte opcode
14468 if (false) {
14469 } else {
14470 setMachineCodes(mi++, (byte) 0xF7);
14471 // "register 0x0" is really part of the opcode
14472 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14473 emitImm32(imm);
14474 }
14475 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14476 }
14477
14478 /**
14479 * Generate a register--immediate TEST. That is,
14480 * <PRE>
14481 * dstReg &= (byte) imm
14482 * </PRE>
14483 *
14484 * @param dstReg the destination register
14485 * @param imm immediate
14486 */
14487 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14488 public final void emitTEST_Reg_Imm_Byte(GPR dstReg, int imm) {
14489 int miStart = mi;
14490 if (dstReg == EAX) {
14491 setMachineCodes(mi++, (byte) 0xA8);
14492 emitImm8(imm);
14493 } else {
14494 generateREXprefix(false, null, null, dstReg);
14495 setMachineCodes(mi++, (byte) 0xF6);
14496 // "register 0x0" is really part of the opcode
14497 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14498 emitImm8(imm);
14499 }
14500 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14501 }
14502
14503 /**
14504 * Generate a register-displacement--immediate TEST. That is,
14505 * <PRE>
14506 * [dstBase + dstDisp] &= (byte) imm
14507 * </PRE>
14508 *
14509 * @param dstBase the destination register
14510 * @param dstDisp the destination displacement
14511 * @param imm immediate
14512 */
14513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14514 public final void emitTEST_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
14515 int miStart = mi;
14516 generateREXprefix(false, null, null, dstBase);
14517 setMachineCodes(mi++, (byte) 0xF6);
14518 // "register 0x0" is really part of the opcode
14519 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14520 emitImm8(imm);
14521 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14522 }
14523
14524 /**
14525 * Generate a register-index--immediate TEST. That is,
14526 * <PRE>
14527 * [dstBase + dstIndex<<scale + dstDisp] &= (byte) imm
14528 * </PRE>
14529 *
14530 * @param dstBase the destination base register
14531 * @param dstIndex the destination index register
14532 * @param dstScale the destination shift amount
14533 * @param dstDisp the destination displacement
14534 * @param imm immediate
14535 */
14536 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14537 public final void emitTEST_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14538 int miStart = mi;
14539 generateREXprefix(false, null, dstIndex, dstBase);
14540 setMachineCodes(mi++, (byte) 0xF6);
14541 // "register 0x0" is really part of the opcode
14542 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14543 emitImm8(imm);
14544 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14545 }
14546
14547 /**
14548 * Generate a register-offset--immediate TEST. That is,
14549 * <PRE>
14550 * [dstIndex<<dstScale + dstDisp] &= (byte) imm
14551 * </PRE>
14552 *
14553 * @param dstIndex the destination index register
14554 * @param dstScale the destination shift amount
14555 * @param dstDisp the destination displacement
14556 * @param imm immediate
14557 */
14558 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14559 public final void emitTEST_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14560 int miStart = mi;
14561 generateREXprefix(false, null, dstIndex, null);
14562 setMachineCodes(mi++, (byte) 0xF6);
14563 // "register 0x0" is really part of the opcode
14564 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14565 emitImm8(imm);
14566 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14567 }
14568
14569 /**
14570 * Generate a absolute--immediate TEST. That is,
14571 * <PRE>
14572 * [dstDisp] &= (byte) imm
14573 * </PRE>
14574 *
14575 * @param dstDisp the destination displacement
14576 * @param imm immediate
14577 */
14578 public final void emitTEST_Abs_Imm_Byte(Address dstDisp, int imm) {
14579 int miStart = mi;
14580 generateREXprefix(false, null, null, null);
14581 setMachineCodes(mi++, (byte) 0xF6);
14582 // "register 0x0" is really part of the opcode
14583 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14584 emitImm8(imm);
14585 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14586 }
14587
14588 /**
14589 * Generate a register(indirect)--immediate TEST. That is,
14590 * <PRE>
14591 * [dstBase] &= (byte) imm
14592 * </PRE>
14593 *
14594 * @param dstBase the destination base register
14595 * @param imm immediate
14596 */
14597 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14598 public final void emitTEST_RegInd_Imm_Byte(GPR dstBase, int imm) {
14599 int miStart = mi;
14600 generateREXprefix(false, null, null, dstBase);
14601 setMachineCodes(mi++, (byte) 0xF6);
14602 // "register 0x0" is really part of the opcode
14603 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14604 emitImm8(imm);
14605 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14606 }
14607
14608 /**
14609 * Generate a register(indirect)--register XOR. That is,
14610 * <PRE>
14611 * [dstBase] ~= srcReg
14612 * </PRE>
14613 *
14614 * @param dstBase the destination base
14615 * @param srcReg the source register
14616 */
14617 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14618 public final void emitXOR_RegInd_Reg(GPR dstBase, GPR srcReg) {
14619 int miStart = mi;
14620 // no group 1 to 4 prefix byte
14621 generateREXprefix(false, srcReg, null, dstBase);
14622 // single byte opcode
14623 setMachineCodes(mi++, (byte) 0x31);
14624 emitRegIndirectRegOperands(dstBase, srcReg);
14625 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
14626 }
14627
14628 /**
14629 * Generate a register-offset--register XOR. That is,
14630 * <PRE>
14631 * [dstReg<<dstScale + dstDisp] ~= srcReg
14632 * </PRE>
14633 *
14634 * @param dstIndex the destination index register
14635 * @param dstScale the destination shift amount
14636 * @param dstDisp the destination displacement
14637 * @param srcReg the source register
14638 */
14639 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
14640 public final void emitXOR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14641 int miStart = mi;
14642 // no group 1 to 4 prefix byte
14643 generateREXprefix(false, srcReg, dstIndex, null);
14644 // single byte opcode
14645 setMachineCodes(mi++, (byte) 0x31);
14646 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
14647 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
14648 }
14649
14650 /**
14651 * Generate a absolute--register XOR. That is,
14652 * <PRE>
14653 * [dstDisp] ~= srcReg
14654 * </PRE>
14655 *
14656 * @param dstDisp the destination address
14657 * @param srcReg the source register
14658 */
14659 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
14660 public final void emitXOR_Abs_Reg(Address dstDisp, GPR srcReg) {
14661 int miStart = mi;
14662 // no group 1 to 4 prefix byte
14663 generateREXprefix(false, srcReg, null, null);
14664 // single byte opcode
14665 setMachineCodes(mi++, (byte) 0x31);
14666 emitAbsRegOperands(dstDisp, srcReg);
14667 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
14668 }
14669
14670 /**
14671 * Generate a register-index--register XOR. That is,
14672 * <PRE>
14673 * [dstBase + dstIndex<<dstScale + dstDisp] ~= srcReg
14674 * </PRE>
14675 *
14676 * @param dstBase the base register
14677 * @param dstIndex the destination index register
14678 * @param dstScale the destination shift amount
14679 * @param dstDisp the destination displacement
14680 * @param srcReg the source register
14681 */
14682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
14683 public final void emitXOR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14684 int miStart = mi;
14685 // no group 1 to 4 prefix byte
14686 generateREXprefix(false, srcReg, dstIndex, dstBase);
14687 // single byte opcode
14688 setMachineCodes(mi++, (byte) 0x31);
14689 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
14690 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
14691 }
14692
14693 /**
14694 * Generate a register-displacement--register XOR. That is,
14695 * <PRE>
14696 * [dstBase + dstDisp] ~= srcReg
14697 * </PRE>
14698 *
14699 * @param dstBase the base register
14700 * @param dstDisp the destination displacement
14701 * @param srcReg the source register
14702 */
14703 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
14704 public final void emitXOR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
14705 int miStart = mi;
14706 // no group 1 to 4 prefix byte
14707 generateREXprefix(false, srcReg, null, dstBase);
14708 // single byte opcode
14709 setMachineCodes(mi++, (byte) 0x31);
14710 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
14711 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
14712 }
14713
14714 /**
14715 * Generate a register--register XOR. That is,
14716 * <PRE>
14717 * dstReg ~= srcReg
14718 * </PRE>
14719 *
14720 * @param dstReg the destination register
14721 * @param srcReg the source register
14722 */
14723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14724 public final void emitXOR_Reg_Reg(GPR dstReg, GPR srcReg) {
14725 int miStart = mi;
14726 // no group 1 to 4 prefix byte
14727 generateREXprefix(false, srcReg, null, dstReg);
14728 // single byte opcode
14729 setMachineCodes(mi++, (byte) 0x31);
14730 emitRegRegOperands(dstReg, srcReg);
14731 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
14732 }
14733
14734 /**
14735 * Generate a register--register-displacement XOR. That is,
14736 * <PRE>
14737 * dstReg ~= [srcReg + srcDisp]
14738 * </PRE>
14739 *
14740 * @param dstReg the destination register
14741 * @param srcBase the source register
14742 * @param srcDisp the source displacement
14743 */
14744 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14745 public final void emitXOR_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
14746 int miStart = mi;
14747 // no group 1 to 4 prefix byte
14748 generateREXprefix(false, dstReg, null, srcBase);
14749 // single byte opcode
14750 setMachineCodes(mi++, (byte) 0x33);
14751 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
14752 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
14753 }
14754
14755 /**
14756 * Generate a register--register-offset XOR. That is,
14757 * <PRE>
14758 * dstReg ~= [srcIndex<<srcScale + srcDisp]
14759 * </PRE>
14760 *
14761 * @param dstReg the destination register
14762 * @param srcIndex the source index register
14763 * @param srcScale the source shift amount
14764 * @param srcDisp the source displacement
14765 */
14766 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14767 public final void emitXOR_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
14768 int miStart = mi;
14769 // no group 1 to 4 prefix byte
14770 generateREXprefix(false, dstReg, srcIndex, null);
14771 // single byte opcode
14772 setMachineCodes(mi++, (byte) 0x33);
14773 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
14774 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
14775 }
14776
14777 /**
14778 * Generate a register--register-offset XOR. That is,
14779 * <PRE>
14780 * dstReg ~= [srcDisp]
14781 * </PRE>
14782 *
14783 * @param dstReg the destination register
14784 * @param srcDisp the source displacement
14785 */
14786 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14787 public final void emitXOR_Reg_Abs(GPR dstReg, Address srcDisp) {
14788 int miStart = mi;
14789 // no group 1 to 4 prefix byte
14790 generateREXprefix(false, dstReg, null, null);
14791 // single byte opcode
14792 setMachineCodes(mi++, (byte) 0x33);
14793 emitAbsRegOperands(srcDisp, dstReg);
14794 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
14795 }
14796
14797 /**
14798 * Generate a register--register-offset XOR. That is,
14799 * <PRE>
14800 * dstReg ~= [srcBase + srcIndex<<srcScale + srcDisp]
14801 * </PRE>
14802 *
14803 * @param dstReg the destination register
14804 * @param srcBase the source base register
14805 * @param srcIndex the source index register
14806 * @param srcScale the source shift amount
14807 * @param srcDisp the source displacement
14808 */
14809 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
14810 public final void emitXOR_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
14811 int miStart = mi;
14812 // no group 1 to 4 prefix byte
14813 generateREXprefix(false, dstReg, srcIndex, srcBase);
14814 // single byte opcode
14815 setMachineCodes(mi++, (byte) 0x33);
14816 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
14817 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
14818 }
14819
14820 /**
14821 * Generate a register--register(indirect) XOR. That is,
14822 * <PRE>
14823 * dstReg ~= [srcBase]
14824 * </PRE>
14825 *
14826 * @param dstReg the destination register
14827 * @param srcBase the source base register
14828 */
14829 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14830 public final void emitXOR_Reg_RegInd(GPR dstReg, GPR srcBase) {
14831 int miStart = mi;
14832 // no group 1 to 4 prefix byte
14833 generateREXprefix(false, dstReg, null, srcBase);
14834 // single byte opcode
14835 setMachineCodes(mi++, (byte) 0x33);
14836 emitRegIndirectRegOperands(srcBase, dstReg);
14837 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
14838 }
14839
14840 /**
14841 * Generate a register(indirect)--register XOR. That is,
14842 * <PRE>
14843 * [dstBase] ~= (word) srcReg
14844 * </PRE>
14845 *
14846 * @param dstBase the destination base
14847 * @param srcReg the source register
14848 */
14849 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14850 public final void emitXOR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
14851 int miStart = mi;
14852 setMachineCodes(mi++, (byte) 0x66);
14853 generateREXprefix(false, srcReg, null, dstBase);
14854 // single byte opcode
14855 setMachineCodes(mi++, (byte) 0x31);
14856 emitRegIndirectRegOperands(dstBase, srcReg);
14857 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
14858 }
14859
14860 /**
14861 * Generate a register-offset--register XOR. That is,
14862 * <PRE>
14863 * [dstReg<<dstScale + dstDisp] ~= (word) srcReg
14864 * </PRE>
14865 *
14866 * @param dstIndex the destination index register
14867 * @param dstScale the destination shift amount
14868 * @param dstDisp the destination displacement
14869 * @param srcReg the source register
14870 */
14871 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
14872 public final void emitXOR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14873 int miStart = mi;
14874 setMachineCodes(mi++, (byte) 0x66);
14875 generateREXprefix(false, srcReg, dstIndex, null);
14876 // single byte opcode
14877 setMachineCodes(mi++, (byte) 0x31);
14878 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
14879 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
14880 }
14881
14882 /**
14883 * Generate a absolute--register XOR. That is,
14884 * <PRE>
14885 * [dstDisp] ~= (word) srcReg
14886 * </PRE>
14887 *
14888 * @param dstDisp the destination address
14889 * @param srcReg the source register
14890 */
14891 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
14892 public final void emitXOR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
14893 int miStart = mi;
14894 setMachineCodes(mi++, (byte) 0x66);
14895 generateREXprefix(false, srcReg, null, null);
14896 // single byte opcode
14897 setMachineCodes(mi++, (byte) 0x31);
14898 emitAbsRegOperands(dstDisp, srcReg);
14899 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
14900 }
14901
14902 /**
14903 * Generate a register-index--register XOR. That is,
14904 * <PRE>
14905 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (word) srcReg
14906 * </PRE>
14907 *
14908 * @param dstBase the base register
14909 * @param dstIndex the destination index register
14910 * @param dstScale the destination shift amount
14911 * @param dstDisp the destination displacement
14912 * @param srcReg the source register
14913 */
14914 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
14915 public final void emitXOR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14916 int miStart = mi;
14917 setMachineCodes(mi++, (byte) 0x66);
14918 generateREXprefix(false, srcReg, dstIndex, dstBase);
14919 // single byte opcode
14920 setMachineCodes(mi++, (byte) 0x31);
14921 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
14922 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
14923 }
14924
14925 /**
14926 * Generate a register-displacement--register XOR. That is,
14927 * <PRE>
14928 * [dstBase + dstDisp] ~= (word) srcReg
14929 * </PRE>
14930 *
14931 * @param dstBase the base register
14932 * @param dstDisp the destination displacement
14933 * @param srcReg the source register
14934 */
14935 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
14936 public final void emitXOR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
14937 int miStart = mi;
14938 setMachineCodes(mi++, (byte) 0x66);
14939 generateREXprefix(false, srcReg, null, dstBase);
14940 // single byte opcode
14941 setMachineCodes(mi++, (byte) 0x31);
14942 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
14943 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
14944 }
14945
14946 /**
14947 * Generate a register--register XOR. That is,
14948 * <PRE>
14949 * dstReg ~= (word) srcReg
14950 * </PRE>
14951 *
14952 * @param dstReg the destination register
14953 * @param srcReg the source register
14954 */
14955 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14956 public final void emitXOR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
14957 int miStart = mi;
14958 setMachineCodes(mi++, (byte) 0x66);
14959 generateREXprefix(false, srcReg, null, dstReg);
14960 // single byte opcode
14961 setMachineCodes(mi++, (byte) 0x31);
14962 emitRegRegOperands(dstReg, srcReg);
14963 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
14964 }
14965
14966 /**
14967 * Generate a register--register-displacement XOR. That is,
14968 * <PRE>
14969 * dstReg ~= (word) [srcReg + srcDisp]
14970 * </PRE>
14971 *
14972 * @param dstReg the destination register
14973 * @param srcBase the source register
14974 * @param srcDisp the source displacement
14975 */
14976 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14977 public final void emitXOR_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
14978 int miStart = mi;
14979 setMachineCodes(mi++, (byte) 0x66);
14980 generateREXprefix(false, dstReg, null, srcBase);
14981 // single byte opcode
14982 setMachineCodes(mi++, (byte) 0x33);
14983 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
14984 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
14985 }
14986
14987 /**
14988 * Generate a register--register-offset XOR. That is,
14989 * <PRE>
14990 * dstReg ~= (word) [srcIndex<<srcScale + srcDisp]
14991 * </PRE>
14992 *
14993 * @param dstReg the destination register
14994 * @param srcIndex the source index register
14995 * @param srcScale the source shift amount
14996 * @param srcDisp the source displacement
14997 */
14998 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14999 public final void emitXOR_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15000 int miStart = mi;
15001 setMachineCodes(mi++, (byte) 0x66);
15002 generateREXprefix(false, dstReg, srcIndex, null);
15003 // single byte opcode
15004 setMachineCodes(mi++, (byte) 0x33);
15005 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15006 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15007 }
15008
15009 /**
15010 * Generate a register--register-offset XOR. That is,
15011 * <PRE>
15012 * dstReg ~= (word) [srcDisp]
15013 * </PRE>
15014 *
15015 * @param dstReg the destination register
15016 * @param srcDisp the source displacement
15017 */
15018 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15019 public final void emitXOR_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
15020 int miStart = mi;
15021 setMachineCodes(mi++, (byte) 0x66);
15022 generateREXprefix(false, dstReg, null, null);
15023 // single byte opcode
15024 setMachineCodes(mi++, (byte) 0x33);
15025 emitAbsRegOperands(srcDisp, dstReg);
15026 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15027 }
15028
15029 /**
15030 * Generate a register--register-offset XOR. That is,
15031 * <PRE>
15032 * dstReg ~= (word) [srcBase + srcIndex<<srcScale + srcDisp]
15033 * </PRE>
15034 *
15035 * @param dstReg the destination register
15036 * @param srcBase the source base register
15037 * @param srcIndex the source index register
15038 * @param srcScale the source shift amount
15039 * @param srcDisp the source displacement
15040 */
15041 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15042 public final void emitXOR_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15043 int miStart = mi;
15044 setMachineCodes(mi++, (byte) 0x66);
15045 generateREXprefix(false, dstReg, srcIndex, srcBase);
15046 // single byte opcode
15047 setMachineCodes(mi++, (byte) 0x33);
15048 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15049 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15050 }
15051
15052 /**
15053 * Generate a register--register(indirect) XOR. That is,
15054 * <PRE>
15055 * dstReg ~= (word) [srcBase]
15056 * </PRE>
15057 *
15058 * @param dstReg the destination register
15059 * @param srcBase the source base register
15060 */
15061 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15062 public final void emitXOR_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
15063 int miStart = mi;
15064 setMachineCodes(mi++, (byte) 0x66);
15065 generateREXprefix(false, dstReg, null, srcBase);
15066 // single byte opcode
15067 setMachineCodes(mi++, (byte) 0x33);
15068 emitRegIndirectRegOperands(srcBase, dstReg);
15069 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15070 }
15071
15072 /**
15073 * Generate a register(indirect)--register XOR. That is,
15074 * <PRE>
15075 * [dstBase] ~= (quad) srcReg
15076 * </PRE>
15077 *
15078 * @param dstBase the destination base
15079 * @param srcReg the source register
15080 */
15081 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15082 public final void emitXOR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
15083 int miStart = mi;
15084 // no group 1 to 4 prefix byte
15085 generateREXprefix(true, srcReg, null, dstBase);
15086 // single byte opcode
15087 setMachineCodes(mi++, (byte) 0x31);
15088 emitRegIndirectRegOperands(dstBase, srcReg);
15089 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
15090 }
15091
15092 /**
15093 * Generate a register-offset--register XOR. That is,
15094 * <PRE>
15095 * [dstReg<<dstScale + dstDisp] ~= (quad) srcReg
15096 * </PRE>
15097 *
15098 * @param dstIndex the destination index register
15099 * @param dstScale the destination shift amount
15100 * @param dstDisp the destination displacement
15101 * @param srcReg the source register
15102 */
15103 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
15104 public final void emitXOR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15105 int miStart = mi;
15106 // no group 1 to 4 prefix byte
15107 generateREXprefix(true, srcReg, dstIndex, null);
15108 // single byte opcode
15109 setMachineCodes(mi++, (byte) 0x31);
15110 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
15111 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
15112 }
15113
15114 /**
15115 * Generate a absolute--register XOR. That is,
15116 * <PRE>
15117 * [dstDisp] ~= (quad) srcReg
15118 * </PRE>
15119 *
15120 * @param dstDisp the destination address
15121 * @param srcReg the source register
15122 */
15123 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
15124 public final void emitXOR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
15125 int miStart = mi;
15126 // no group 1 to 4 prefix byte
15127 generateREXprefix(true, srcReg, null, null);
15128 // single byte opcode
15129 setMachineCodes(mi++, (byte) 0x31);
15130 emitAbsRegOperands(dstDisp, srcReg);
15131 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
15132 }
15133
15134 /**
15135 * Generate a register-index--register XOR. That is,
15136 * <PRE>
15137 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (quad) srcReg
15138 * </PRE>
15139 *
15140 * @param dstBase the base register
15141 * @param dstIndex the destination index register
15142 * @param dstScale the destination shift amount
15143 * @param dstDisp the destination displacement
15144 * @param srcReg the source register
15145 */
15146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
15147 public final void emitXOR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15148 int miStart = mi;
15149 // no group 1 to 4 prefix byte
15150 generateREXprefix(true, srcReg, dstIndex, dstBase);
15151 // single byte opcode
15152 setMachineCodes(mi++, (byte) 0x31);
15153 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
15154 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
15155 }
15156
15157 /**
15158 * Generate a register-displacement--register XOR. That is,
15159 * <PRE>
15160 * [dstBase + dstDisp] ~= (quad) srcReg
15161 * </PRE>
15162 *
15163 * @param dstBase the base register
15164 * @param dstDisp the destination displacement
15165 * @param srcReg the source register
15166 */
15167 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
15168 public final void emitXOR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
15169 int miStart = mi;
15170 // no group 1 to 4 prefix byte
15171 generateREXprefix(true, srcReg, null, dstBase);
15172 // single byte opcode
15173 setMachineCodes(mi++, (byte) 0x31);
15174 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
15175 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
15176 }
15177
15178 /**
15179 * Generate a register--register XOR. That is,
15180 * <PRE>
15181 * dstReg ~= (quad) srcReg
15182 * </PRE>
15183 *
15184 * @param dstReg the destination register
15185 * @param srcReg the source register
15186 */
15187 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15188 public final void emitXOR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
15189 int miStart = mi;
15190 // no group 1 to 4 prefix byte
15191 generateREXprefix(true, srcReg, null, dstReg);
15192 // single byte opcode
15193 setMachineCodes(mi++, (byte) 0x31);
15194 emitRegRegOperands(dstReg, srcReg);
15195 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
15196 }
15197
15198 /**
15199 * Generate a register--register-displacement XOR. That is,
15200 * <PRE>
15201 * dstReg ~= (quad) [srcReg + srcDisp]
15202 * </PRE>
15203 *
15204 * @param dstReg the destination register
15205 * @param srcBase the source register
15206 * @param srcDisp the source displacement
15207 */
15208 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15209 public final void emitXOR_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
15210 int miStart = mi;
15211 // no group 1 to 4 prefix byte
15212 generateREXprefix(true, dstReg, null, srcBase);
15213 // single byte opcode
15214 setMachineCodes(mi++, (byte) 0x33);
15215 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
15216 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
15217 }
15218
15219 /**
15220 * Generate a register--register-offset XOR. That is,
15221 * <PRE>
15222 * dstReg ~= (quad) [srcIndex<<srcScale + srcDisp]
15223 * </PRE>
15224 *
15225 * @param dstReg the destination register
15226 * @param srcIndex the source index register
15227 * @param srcScale the source shift amount
15228 * @param srcDisp the source displacement
15229 */
15230 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15231 public final void emitXOR_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15232 int miStart = mi;
15233 // no group 1 to 4 prefix byte
15234 generateREXprefix(true, dstReg, srcIndex, null);
15235 // single byte opcode
15236 setMachineCodes(mi++, (byte) 0x33);
15237 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15238 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15239 }
15240
15241 /**
15242 * Generate a register--register-offset XOR. That is,
15243 * <PRE>
15244 * dstReg ~= (quad) [srcDisp]
15245 * </PRE>
15246 *
15247 * @param dstReg the destination register
15248 * @param srcDisp the source displacement
15249 */
15250 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15251 public final void emitXOR_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
15252 int miStart = mi;
15253 // no group 1 to 4 prefix byte
15254 generateREXprefix(true, dstReg, null, null);
15255 // single byte opcode
15256 setMachineCodes(mi++, (byte) 0x33);
15257 emitAbsRegOperands(srcDisp, dstReg);
15258 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15259 }
15260
15261 /**
15262 * Generate a register--register-offset XOR. That is,
15263 * <PRE>
15264 * dstReg ~= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
15265 * </PRE>
15266 *
15267 * @param dstReg the destination register
15268 * @param srcBase the source base register
15269 * @param srcIndex the source index register
15270 * @param srcScale the source shift amount
15271 * @param srcDisp the source displacement
15272 */
15273 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15274 public final void emitXOR_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15275 int miStart = mi;
15276 // no group 1 to 4 prefix byte
15277 generateREXprefix(true, dstReg, srcIndex, srcBase);
15278 // single byte opcode
15279 setMachineCodes(mi++, (byte) 0x33);
15280 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15281 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15282 }
15283
15284 /**
15285 * Generate a register--register(indirect) XOR. That is,
15286 * <PRE>
15287 * dstReg ~= (quad) [srcBase]
15288 * </PRE>
15289 *
15290 * @param dstReg the destination register
15291 * @param srcBase the source base register
15292 */
15293 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15294 public final void emitXOR_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
15295 int miStart = mi;
15296 // no group 1 to 4 prefix byte
15297 generateREXprefix(true, dstReg, null, srcBase);
15298 // single byte opcode
15299 setMachineCodes(mi++, (byte) 0x33);
15300 emitRegIndirectRegOperands(srcBase, dstReg);
15301 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15302 }
15303
15304 /**
15305 * Generate a register(indirect)--register XOR. That is,
15306 * <PRE>
15307 * [dstBase] ~= (byte) srcReg
15308 * </PRE>
15309 *
15310 * @param dstBase the destination base
15311 * @param srcReg the source register
15312 */
15313 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15314 public final void emitXOR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
15315 int miStart = mi;
15316 // no group 1 to 4 prefix byte
15317 generateREXprefix(false, srcReg, null, dstBase);
15318 // single byte opcode
15319 setMachineCodes(mi++, (byte) 0x30);
15320 emitRegIndirectRegOperands(dstBase, srcReg);
15321 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
15322 }
15323
15324 /**
15325 * Generate a register-offset--register XOR. That is,
15326 * <PRE>
15327 * [dstReg<<dstScale + dstDisp] ~= (byte) srcReg
15328 * </PRE>
15329 *
15330 * @param dstIndex the destination index register
15331 * @param dstScale the destination shift amount
15332 * @param dstDisp the destination displacement
15333 * @param srcReg the source register
15334 */
15335 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
15336 public final void emitXOR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15337 int miStart = mi;
15338 // no group 1 to 4 prefix byte
15339 generateREXprefix(false, srcReg, dstIndex, null);
15340 // single byte opcode
15341 setMachineCodes(mi++, (byte) 0x30);
15342 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
15343 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
15344 }
15345
15346 /**
15347 * Generate a absolute--register XOR. That is,
15348 * <PRE>
15349 * [dstDisp] ~= (byte) srcReg
15350 * </PRE>
15351 *
15352 * @param dstDisp the destination address
15353 * @param srcReg the source register
15354 */
15355 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
15356 public final void emitXOR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
15357 int miStart = mi;
15358 // no group 1 to 4 prefix byte
15359 generateREXprefix(false, srcReg, null, null);
15360 // single byte opcode
15361 setMachineCodes(mi++, (byte) 0x30);
15362 emitAbsRegOperands(dstDisp, srcReg);
15363 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
15364 }
15365
15366 /**
15367 * Generate a register-index--register XOR. That is,
15368 * <PRE>
15369 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (byte) srcReg
15370 * </PRE>
15371 *
15372 * @param dstBase the base register
15373 * @param dstIndex the destination index register
15374 * @param dstScale the destination shift amount
15375 * @param dstDisp the destination displacement
15376 * @param srcReg the source register
15377 */
15378 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
15379 public final void emitXOR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15380 int miStart = mi;
15381 // no group 1 to 4 prefix byte
15382 generateREXprefix(false, srcReg, dstIndex, dstBase);
15383 // single byte opcode
15384 setMachineCodes(mi++, (byte) 0x30);
15385 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
15386 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
15387 }
15388
15389 /**
15390 * Generate a register-displacement--register XOR. That is,
15391 * <PRE>
15392 * [dstBase + dstDisp] ~= (byte) srcReg
15393 * </PRE>
15394 *
15395 * @param dstBase the base register
15396 * @param dstDisp the destination displacement
15397 * @param srcReg the source register
15398 */
15399 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
15400 public final void emitXOR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
15401 int miStart = mi;
15402 // no group 1 to 4 prefix byte
15403 generateREXprefix(false, srcReg, null, dstBase);
15404 // single byte opcode
15405 setMachineCodes(mi++, (byte) 0x30);
15406 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
15407 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
15408 }
15409
15410 /**
15411 * Generate a register--register XOR. That is,
15412 * <PRE>
15413 * dstReg ~= (byte) srcReg
15414 * </PRE>
15415 *
15416 * @param dstReg the destination register
15417 * @param srcReg the source register
15418 */
15419 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15420 public final void emitXOR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
15421 int miStart = mi;
15422 // no group 1 to 4 prefix byte
15423 generateREXprefix(false, srcReg, null, dstReg);
15424 // single byte opcode
15425 setMachineCodes(mi++, (byte) 0x30);
15426 emitRegRegOperands(dstReg, srcReg);
15427 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
15428 }
15429
15430 /**
15431 * Generate a register--register-displacement XOR. That is,
15432 * <PRE>
15433 * dstReg ~= (byte) [srcReg + srcDisp]
15434 * </PRE>
15435 *
15436 * @param dstReg the destination register
15437 * @param srcBase the source register
15438 * @param srcDisp the source displacement
15439 */
15440 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15441 public final void emitXOR_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
15442 int miStart = mi;
15443 // no group 1 to 4 prefix byte
15444 generateREXprefix(false, dstReg, null, srcBase);
15445 // single byte opcode
15446 setMachineCodes(mi++, (byte) 0x32);
15447 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
15448 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
15449 }
15450
15451 /**
15452 * Generate a register--register-offset XOR. That is,
15453 * <PRE>
15454 * dstReg ~= (byte) [srcIndex<<srcScale + srcDisp]
15455 * </PRE>
15456 *
15457 * @param dstReg the destination register
15458 * @param srcIndex the source index register
15459 * @param srcScale the source shift amount
15460 * @param srcDisp the source displacement
15461 */
15462 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15463 public final void emitXOR_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15464 int miStart = mi;
15465 // no group 1 to 4 prefix byte
15466 generateREXprefix(false, dstReg, srcIndex, null);
15467 // single byte opcode
15468 setMachineCodes(mi++, (byte) 0x32);
15469 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15470 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15471 }
15472
15473 /**
15474 * Generate a register--register-offset XOR. That is,
15475 * <PRE>
15476 * dstReg ~= (byte) [srcDisp]
15477 * </PRE>
15478 *
15479 * @param dstReg the destination register
15480 * @param srcDisp the source displacement
15481 */
15482 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15483 public final void emitXOR_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
15484 int miStart = mi;
15485 // no group 1 to 4 prefix byte
15486 generateREXprefix(false, dstReg, null, null);
15487 // single byte opcode
15488 setMachineCodes(mi++, (byte) 0x32);
15489 emitAbsRegOperands(srcDisp, dstReg);
15490 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15491 }
15492
15493 /**
15494 * Generate a register--register-offset XOR. That is,
15495 * <PRE>
15496 * dstReg ~= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
15497 * </PRE>
15498 *
15499 * @param dstReg the destination register
15500 * @param srcBase the source base register
15501 * @param srcIndex the source index register
15502 * @param srcScale the source shift amount
15503 * @param srcDisp the source displacement
15504 */
15505 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15506 public final void emitXOR_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15507 int miStart = mi;
15508 // no group 1 to 4 prefix byte
15509 generateREXprefix(false, dstReg, srcIndex, srcBase);
15510 // single byte opcode
15511 setMachineCodes(mi++, (byte) 0x32);
15512 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15513 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15514 }
15515
15516 /**
15517 * Generate a register--register(indirect) XOR. That is,
15518 * <PRE>
15519 * dstReg ~= (byte) [srcBase]
15520 * </PRE>
15521 *
15522 * @param dstReg the destination register
15523 * @param srcBase the source base register
15524 */
15525 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15526 public final void emitXOR_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
15527 int miStart = mi;
15528 // no group 1 to 4 prefix byte
15529 generateREXprefix(false, dstReg, null, srcBase);
15530 // single byte opcode
15531 setMachineCodes(mi++, (byte) 0x32);
15532 emitRegIndirectRegOperands(srcBase, dstReg);
15533 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15534 }
15535
15536 /**
15537 * Generate a register--immediate XOR. That is,
15538 * <PRE>
15539 * dstReg ~= imm
15540 * </PRE>
15541 *
15542 * @param dstReg the destination register
15543 * @param imm immediate
15544 */
15545 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15546 public final void emitXOR_Reg_Imm(GPR dstReg, int imm) {
15547 int miStart = mi;
15548 // no group 1 to 4 prefix byte
15549 generateREXprefix(false, null, null, dstReg);
15550 // single byte opcode
15551 if (fits(imm,8)) {
15552 setMachineCodes(mi++, (byte) 0x83);
15553 // "register 0x6" is really part of the opcode
15554 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15555 emitImm8((byte)imm);
15556 } else if (dstReg == EAX) {
15557 setMachineCodes(mi++, (byte) 0x35);
15558 emitImm32(imm);
15559 } else {
15560 setMachineCodes(mi++, (byte) 0x81);
15561 // "register 0x6" is really part of the opcode
15562 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15563 emitImm32(imm);
15564 }
15565 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15566 }
15567
15568 /**
15569 * Generate a register-displacement--immediate XOR. That is,
15570 * <PRE>
15571 * [dstBase + dstDisp] ~= imm
15572 * </PRE>
15573 *
15574 * @param dstBase the destination register
15575 * @param dstDisp the destination displacement
15576 * @param imm immediate
15577 */
15578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15579 public final void emitXOR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
15580 int miStart = mi;
15581 // no group 1 to 4 prefix byte
15582 generateREXprefix(false, null, null, dstBase);
15583 // single byte opcode
15584 if (fits(imm,8)) {
15585 setMachineCodes(mi++, (byte) 0x83);
15586 // "register 0x6" is really part of the opcode
15587 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15588 emitImm8((byte)imm);
15589 } else {
15590 setMachineCodes(mi++, (byte) 0x81);
15591 // "register 0x6" is really part of the opcode
15592 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15593 emitImm32(imm);
15594 }
15595 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15596 }
15597
15598 /**
15599 * Generate a register-offset--immediate XOR. That is,
15600 * <PRE>
15601 * [dstIndex<<dstScale + dstDisp] ~= imm
15602 * </PRE>
15603 *
15604 * @param dstIndex the destination index register
15605 * @param dstScale the destination shift amount
15606 * @param dstDisp the destination displacement
15607 * @param imm immediate
15608 */
15609 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15610 public final void emitXOR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15611 int miStart = mi;
15612 // no group 1 to 4 prefix byte
15613 generateREXprefix(false, null, dstIndex, null);
15614 // single byte opcode
15615 if (fits(imm,8)) {
15616 setMachineCodes(mi++, (byte) 0x83);
15617 // "register 0x6" is really part of the opcode
15618 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15619 emitImm8((byte)imm);
15620 } else {
15621 setMachineCodes(mi++, (byte) 0x81);
15622 // "register 0x6" is really part of the opcode
15623 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15624 emitImm32(imm);
15625 }
15626 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
15627 }
15628
15629 /**
15630 * Generate a absolute--immediate XOR. That is,
15631 * <PRE>
15632 * [dstDisp] ~= imm
15633 * </PRE>
15634 *
15635 * @param dstDisp the destination displacement
15636 * @param imm immediate
15637 */
15638 public final void emitXOR_Abs_Imm(Address dstDisp, int imm) {
15639 int miStart = mi;
15640 // no group 1 to 4 prefix byte
15641 generateREXprefix(false, null, null, null);
15642 // single byte opcode
15643 if (fits(imm,8)) {
15644 setMachineCodes(mi++, (byte) 0x83);
15645 // "register 0x6" is really part of the opcode
15646 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15647 emitImm8((byte)imm);
15648 } else {
15649 setMachineCodes(mi++, (byte) 0x81);
15650 // "register 0x6" is really part of the opcode
15651 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15652 emitImm32(imm);
15653 }
15654 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
15655 }
15656
15657 /**
15658 * Generate a register-index--immediate XOR. That is,
15659 * <PRE>
15660 * [dstBase + dstIndex<<dstScale + dstDisp] ~= imm
15661 * </PRE>
15662 *
15663 * @param dstBase the destination base register
15664 * @param dstIndex the destination index register
15665 * @param dstScale the destination shift amount
15666 * @param dstDisp the destination displacement
15667 * @param imm immediate
15668 */
15669 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15670 public final void emitXOR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15671 int miStart = mi;
15672 // no group 1 to 4 prefix byte
15673 generateREXprefix(false, null, dstIndex, dstBase);
15674 // single byte opcode
15675 if (fits(imm,8)) {
15676 setMachineCodes(mi++, (byte) 0x83);
15677 // "register 0x6" is really part of the opcode
15678 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15679 emitImm8((byte)imm);
15680 } else {
15681 setMachineCodes(mi++, (byte) 0x81);
15682 // "register 0x6" is really part of the opcode
15683 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15684 emitImm32(imm);
15685 }
15686 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
15687 }
15688
15689 /**
15690 * Generate a register(indirect)--immediate XOR. That is,
15691 * <PRE>
15692 * [dstBase] ~= imm
15693 * </PRE>
15694 *
15695 * @param dstBase the destination base register
15696 * @param imm immediate
15697 */
15698 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15699 public final void emitXOR_RegInd_Imm(GPR dstBase, int imm) {
15700 int miStart = mi;
15701 // no group 1 to 4 prefix byte
15702 generateREXprefix(false, null, null, dstBase);
15703 // single byte opcode
15704 if (fits(imm,8)) {
15705 setMachineCodes(mi++, (byte) 0x83);
15706 // "register 0x6" is really part of the opcode
15707 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15708 emitImm8((byte)imm);
15709 } else {
15710 setMachineCodes(mi++, (byte) 0x81);
15711 // "register 0x6" is really part of the opcode
15712 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15713 emitImm32(imm);
15714 }
15715 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
15716 }
15717
15718 /**
15719 * Generate a register--immediate XOR. That is,
15720 * <PRE>
15721 * dstReg ~= (word) imm
15722 * </PRE>
15723 *
15724 * @param dstReg the destination register
15725 * @param imm immediate
15726 */
15727 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15728 public final void emitXOR_Reg_Imm_Word(GPR dstReg, int imm) {
15729 int miStart = mi;
15730 setMachineCodes(mi++, (byte) 0x66);
15731 generateREXprefix(false, null, null, dstReg);
15732 // single byte opcode
15733 if (fits(imm,8)) {
15734 setMachineCodes(mi++, (byte) 0x83);
15735 // "register 0x6" is really part of the opcode
15736 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15737 emitImm8((byte)imm);
15738 } else if (dstReg == EAX) {
15739 setMachineCodes(mi++, (byte) 0x35);
15740 emitImm16(imm);
15741 } else {
15742 setMachineCodes(mi++, (byte) 0x81);
15743 // "register 0x6" is really part of the opcode
15744 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15745 emitImm16(imm);
15746 }
15747 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15748 }
15749
15750 /**
15751 * Generate a register-displacement--immediate XOR. That is,
15752 * <PRE>
15753 * [dstBase + dstDisp] ~= (word) imm
15754 * </PRE>
15755 *
15756 * @param dstBase the destination register
15757 * @param dstDisp the destination displacement
15758 * @param imm immediate
15759 */
15760 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15761 public final void emitXOR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
15762 int miStart = mi;
15763 setMachineCodes(mi++, (byte) 0x66);
15764 generateREXprefix(false, null, null, dstBase);
15765 // single byte opcode
15766 if (fits(imm,8)) {
15767 setMachineCodes(mi++, (byte) 0x83);
15768 // "register 0x6" is really part of the opcode
15769 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15770 emitImm8((byte)imm);
15771 } else {
15772 setMachineCodes(mi++, (byte) 0x81);
15773 // "register 0x6" is really part of the opcode
15774 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15775 emitImm16(imm);
15776 }
15777 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15778 }
15779
15780 /**
15781 * Generate a register-offset--immediate XOR. That is,
15782 * <PRE>
15783 * [dstIndex<<dstScale + dstDisp] ~= (word) imm
15784 * </PRE>
15785 *
15786 * @param dstIndex the destination index register
15787 * @param dstScale the destination shift amount
15788 * @param dstDisp the destination displacement
15789 * @param imm immediate
15790 */
15791 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15792 public final void emitXOR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15793 int miStart = mi;
15794 setMachineCodes(mi++, (byte) 0x66);
15795 generateREXprefix(false, null, dstIndex, null);
15796 // single byte opcode
15797 if (fits(imm,8)) {
15798 setMachineCodes(mi++, (byte) 0x83);
15799 // "register 0x6" is really part of the opcode
15800 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15801 emitImm8((byte)imm);
15802 } else {
15803 setMachineCodes(mi++, (byte) 0x81);
15804 // "register 0x6" is really part of the opcode
15805 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15806 emitImm16(imm);
15807 }
15808 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
15809 }
15810
15811 /**
15812 * Generate a absolute--immediate XOR. That is,
15813 * <PRE>
15814 * [dstDisp] ~= (word) imm
15815 * </PRE>
15816 *
15817 * @param dstDisp the destination displacement
15818 * @param imm immediate
15819 */
15820 public final void emitXOR_Abs_Imm_Word(Address dstDisp, int imm) {
15821 int miStart = mi;
15822 setMachineCodes(mi++, (byte) 0x66);
15823 generateREXprefix(false, null, null, null);
15824 // single byte opcode
15825 if (fits(imm,8)) {
15826 setMachineCodes(mi++, (byte) 0x83);
15827 // "register 0x6" is really part of the opcode
15828 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15829 emitImm8((byte)imm);
15830 } else {
15831 setMachineCodes(mi++, (byte) 0x81);
15832 // "register 0x6" is really part of the opcode
15833 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15834 emitImm16(imm);
15835 }
15836 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
15837 }
15838
15839 /**
15840 * Generate a register-index--immediate XOR. That is,
15841 * <PRE>
15842 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (word) imm
15843 * </PRE>
15844 *
15845 * @param dstBase the destination base register
15846 * @param dstIndex the destination index register
15847 * @param dstScale the destination shift amount
15848 * @param dstDisp the destination displacement
15849 * @param imm immediate
15850 */
15851 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15852 public final void emitXOR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15853 int miStart = mi;
15854 setMachineCodes(mi++, (byte) 0x66);
15855 generateREXprefix(false, null, dstIndex, dstBase);
15856 // single byte opcode
15857 if (fits(imm,8)) {
15858 setMachineCodes(mi++, (byte) 0x83);
15859 // "register 0x6" is really part of the opcode
15860 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15861 emitImm8((byte)imm);
15862 } else {
15863 setMachineCodes(mi++, (byte) 0x81);
15864 // "register 0x6" is really part of the opcode
15865 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15866 emitImm16(imm);
15867 }
15868 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
15869 }
15870
15871 /**
15872 * Generate a register(indirect)--immediate XOR. That is,
15873 * <PRE>
15874 * [dstBase] ~= (word) imm
15875 * </PRE>
15876 *
15877 * @param dstBase the destination base register
15878 * @param imm immediate
15879 */
15880 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15881 public final void emitXOR_RegInd_Imm_Word(GPR dstBase, int imm) {
15882 int miStart = mi;
15883 setMachineCodes(mi++, (byte) 0x66);
15884 generateREXprefix(false, null, null, dstBase);
15885 // single byte opcode
15886 if (fits(imm,8)) {
15887 setMachineCodes(mi++, (byte) 0x83);
15888 // "register 0x6" is really part of the opcode
15889 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15890 emitImm8((byte)imm);
15891 } else {
15892 setMachineCodes(mi++, (byte) 0x81);
15893 // "register 0x6" is really part of the opcode
15894 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15895 emitImm16(imm);
15896 }
15897 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
15898 }
15899
15900 /**
15901 * Generate a register--immediate XOR. That is,
15902 * <PRE>
15903 * dstReg ~= (quad) imm
15904 * </PRE>
15905 *
15906 * @param dstReg the destination register
15907 * @param imm immediate
15908 */
15909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15910 public final void emitXOR_Reg_Imm_Quad(GPR dstReg, int imm) {
15911 int miStart = mi;
15912 // no group 1 to 4 prefix byte
15913 generateREXprefix(true, null, null, dstReg);
15914 // single byte opcode
15915 if (fits(imm,8)) {
15916 setMachineCodes(mi++, (byte) 0x83);
15917 // "register 0x6" is really part of the opcode
15918 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15919 emitImm8((byte)imm);
15920 } else if (dstReg == EAX) {
15921 setMachineCodes(mi++, (byte) 0x35);
15922 emitImm32(imm);
15923 } else {
15924 setMachineCodes(mi++, (byte) 0x81);
15925 // "register 0x6" is really part of the opcode
15926 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15927 emitImm32(imm);
15928 }
15929 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15930 }
15931
15932 /**
15933 * Generate a register-displacement--immediate XOR. That is,
15934 * <PRE>
15935 * [dstBase + dstDisp] ~= (quad) imm
15936 * </PRE>
15937 *
15938 * @param dstBase the destination register
15939 * @param dstDisp the destination displacement
15940 * @param imm immediate
15941 */
15942 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15943 public final void emitXOR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
15944 int miStart = mi;
15945 // no group 1 to 4 prefix byte
15946 generateREXprefix(true, null, null, dstBase);
15947 // single byte opcode
15948 if (fits(imm,8)) {
15949 setMachineCodes(mi++, (byte) 0x83);
15950 // "register 0x6" is really part of the opcode
15951 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15952 emitImm8((byte)imm);
15953 } else {
15954 setMachineCodes(mi++, (byte) 0x81);
15955 // "register 0x6" is really part of the opcode
15956 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15957 emitImm32(imm);
15958 }
15959 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15960 }
15961
15962 /**
15963 * Generate a register-offset--immediate XOR. That is,
15964 * <PRE>
15965 * [dstIndex<<dstScale + dstDisp] ~= (quad) imm
15966 * </PRE>
15967 *
15968 * @param dstIndex the destination index register
15969 * @param dstScale the destination shift amount
15970 * @param dstDisp the destination displacement
15971 * @param imm immediate
15972 */
15973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15974 public final void emitXOR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15975 int miStart = mi;
15976 // no group 1 to 4 prefix byte
15977 generateREXprefix(true, null, dstIndex, null);
15978 // single byte opcode
15979 if (fits(imm,8)) {
15980 setMachineCodes(mi++, (byte) 0x83);
15981 // "register 0x6" is really part of the opcode
15982 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15983 emitImm8((byte)imm);
15984 } else {
15985 setMachineCodes(mi++, (byte) 0x81);
15986 // "register 0x6" is really part of the opcode
15987 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15988 emitImm32(imm);
15989 }
15990 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
15991 }
15992
15993 /**
15994 * Generate a absolute--immediate XOR. That is,
15995 * <PRE>
15996 * [dstDisp] ~= (quad) imm
15997 * </PRE>
15998 *
15999 * @param dstDisp the destination displacement
16000 * @param imm immediate
16001 */
16002 public final void emitXOR_Abs_Imm_Quad(Address dstDisp, int imm) {
16003 int miStart = mi;
16004 // no group 1 to 4 prefix byte
16005 generateREXprefix(true, null, null, null);
16006 // single byte opcode
16007 if (fits(imm,8)) {
16008 setMachineCodes(mi++, (byte) 0x83);
16009 // "register 0x6" is really part of the opcode
16010 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16011 emitImm8((byte)imm);
16012 } else {
16013 setMachineCodes(mi++, (byte) 0x81);
16014 // "register 0x6" is really part of the opcode
16015 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16016 emitImm32(imm);
16017 }
16018 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
16019 }
16020
16021 /**
16022 * Generate a register-index--immediate XOR. That is,
16023 * <PRE>
16024 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (quad) imm
16025 * </PRE>
16026 *
16027 * @param dstBase the destination base register
16028 * @param dstIndex the destination index register
16029 * @param dstScale the destination shift amount
16030 * @param dstDisp the destination displacement
16031 * @param imm immediate
16032 */
16033 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16034 public final void emitXOR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16035 int miStart = mi;
16036 // no group 1 to 4 prefix byte
16037 generateREXprefix(true, null, dstIndex, dstBase);
16038 // single byte opcode
16039 if (fits(imm,8)) {
16040 setMachineCodes(mi++, (byte) 0x83);
16041 // "register 0x6" is really part of the opcode
16042 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16043 emitImm8((byte)imm);
16044 } else {
16045 setMachineCodes(mi++, (byte) 0x81);
16046 // "register 0x6" is really part of the opcode
16047 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16048 emitImm32(imm);
16049 }
16050 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
16051 }
16052
16053 /**
16054 * Generate a register(indirect)--immediate XOR. That is,
16055 * <PRE>
16056 * [dstBase] ~= (quad) imm
16057 * </PRE>
16058 *
16059 * @param dstBase the destination base register
16060 * @param imm immediate
16061 */
16062 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16063 public final void emitXOR_RegInd_Imm_Quad(GPR dstBase, int imm) {
16064 int miStart = mi;
16065 // no group 1 to 4 prefix byte
16066 generateREXprefix(true, null, null, dstBase);
16067 // single byte opcode
16068 if (fits(imm,8)) {
16069 setMachineCodes(mi++, (byte) 0x83);
16070 // "register 0x6" is really part of the opcode
16071 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16072 emitImm8((byte)imm);
16073 } else {
16074 setMachineCodes(mi++, (byte) 0x81);
16075 // "register 0x6" is really part of the opcode
16076 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16077 emitImm32(imm);
16078 }
16079 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
16080 }
16081
16082 /**
16083 * Generate a register--immediate XOR. That is,
16084 * <PRE>
16085 * dstReg ~= (byte) imm
16086 * </PRE>
16087 *
16088 * @param dstReg the destination register
16089 * @param imm immediate
16090 */
16091 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16092 public final void emitXOR_Reg_Imm_Byte(GPR dstReg, int imm) {
16093 int miStart = mi;
16094 if (dstReg == EAX) {
16095 setMachineCodes(mi++, (byte) 0x34);
16096 emitImm8(imm);
16097 } else {
16098 generateREXprefix(false, null, null, dstReg);
16099 setMachineCodes(mi++, (byte) 0x80);
16100 // "register 0x6" is really part of the opcode
16101 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
16102 emitImm8(imm);
16103 }
16104 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
16105 }
16106
16107 /**
16108 * Generate a register-displacement--immediate XOR. That is,
16109 * <PRE>
16110 * [dstBase + dstDisp] ~= (byte) imm
16111 * </PRE>
16112 *
16113 * @param dstBase the destination register
16114 * @param dstDisp the destination displacement
16115 * @param imm immediate
16116 */
16117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16118 public final void emitXOR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
16119 int miStart = mi;
16120 generateREXprefix(false, null, null, dstBase);
16121 setMachineCodes(mi++, (byte) 0x80);
16122 // "register 0x6" is really part of the opcode
16123 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
16124 emitImm8(imm);
16125 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
16126 }
16127
16128 /**
16129 * Generate a register-index--immediate XOR. That is,
16130 * <PRE>
16131 * [dstBase + dstIndex<<scale + dstDisp] ~= (byte) imm
16132 * </PRE>
16133 *
16134 * @param dstBase the destination base register
16135 * @param dstIndex the destination index register
16136 * @param dstScale the destination shift amount
16137 * @param dstDisp the destination displacement
16138 * @param imm immediate
16139 */
16140 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16141 public final void emitXOR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16142 int miStart = mi;
16143 generateREXprefix(false, null, dstIndex, dstBase);
16144 setMachineCodes(mi++, (byte) 0x80);
16145 // "register 0x6" is really part of the opcode
16146 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16147 emitImm8(imm);
16148 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
16149 }
16150
16151 /**
16152 * Generate a register-offset--immediate XOR. That is,
16153 * <PRE>
16154 * [dstIndex<<dstScale + dstDisp] ~= (byte) imm
16155 * </PRE>
16156 *
16157 * @param dstIndex the destination index register
16158 * @param dstScale the destination shift amount
16159 * @param dstDisp the destination displacement
16160 * @param imm immediate
16161 */
16162 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16163 public final void emitXOR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16164 int miStart = mi;
16165 generateREXprefix(false, null, dstIndex, null);
16166 setMachineCodes(mi++, (byte) 0x80);
16167 // "register 0x6" is really part of the opcode
16168 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16169 emitImm8(imm);
16170 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
16171 }
16172
16173 /**
16174 * Generate a absolute--immediate XOR. That is,
16175 * <PRE>
16176 * [dstDisp] ~= (byte) imm
16177 * </PRE>
16178 *
16179 * @param dstDisp the destination displacement
16180 * @param imm immediate
16181 */
16182 public final void emitXOR_Abs_Imm_Byte(Address dstDisp, int imm) {
16183 int miStart = mi;
16184 generateREXprefix(false, null, null, null);
16185 setMachineCodes(mi++, (byte) 0x80);
16186 // "register 0x6" is really part of the opcode
16187 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16188 emitImm8(imm);
16189 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
16190 }
16191
16192 /**
16193 * Generate a register(indirect)--immediate XOR. That is,
16194 * <PRE>
16195 * [dstBase] ~= (byte) imm
16196 * </PRE>
16197 *
16198 * @param dstBase the destination base register
16199 * @param imm immediate
16200 */
16201 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16202 public final void emitXOR_RegInd_Imm_Byte(GPR dstBase, int imm) {
16203 int miStart = mi;
16204 generateREXprefix(false, null, null, dstBase);
16205 setMachineCodes(mi++, (byte) 0x80);
16206 // "register 0x6" is really part of the opcode
16207 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16208 emitImm8(imm);
16209 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
16210 }
16211
16212 /**
16213 * Generate a register(indirect)--register BT. That is,
16214 * <PRE>
16215 * [dstBase] BT= srcReg
16216 * </PRE>
16217 *
16218 * @param dstBase the destination base
16219 * @param srcReg the source register
16220 */
16221 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16222 public final void emitBT_RegInd_Reg(GPR dstBase, GPR srcReg) {
16223 int miStart = mi;
16224 // no group 1 to 4 prefix byte
16225 generateREXprefix(false, srcReg, null, dstBase);
16226 setMachineCodes(mi++, (byte) 0x0F);
16227 setMachineCodes(mi++, (byte) 0xA3);
16228 emitRegIndirectRegOperands(dstBase, srcReg);
16229 if (lister != null) lister.RNR(miStart, "BT", dstBase, srcReg);
16230 }
16231
16232 /**
16233 * Generate a register-offset--register BT. That is,
16234 * <PRE>
16235 * [dstReg<<dstScale + dstDisp] BT= srcReg
16236 * </PRE>
16237 *
16238 * @param dstIndex the destination index register
16239 * @param dstScale the destination shift amount
16240 * @param dstDisp the destination displacement
16241 * @param srcReg the source register
16242 */
16243 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16244 public final void emitBT_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16245 int miStart = mi;
16246 // no group 1 to 4 prefix byte
16247 generateREXprefix(false, srcReg, dstIndex, null);
16248 setMachineCodes(mi++, (byte) 0x0F);
16249 setMachineCodes(mi++, (byte) 0xA3);
16250 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16251 if (lister != null) lister.RFDR(miStart, "BT", dstIndex, dstScale, dstDisp, srcReg);
16252 }
16253
16254 /**
16255 * Generate a absolute--register BT. That is,
16256 * <PRE>
16257 * [dstDisp] BT= srcReg
16258 * </PRE>
16259 *
16260 * @param dstDisp the destination address
16261 * @param srcReg the source register
16262 */
16263 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16264 public final void emitBT_Abs_Reg(Address dstDisp, GPR srcReg) {
16265 int miStart = mi;
16266 // no group 1 to 4 prefix byte
16267 generateREXprefix(false, srcReg, null, null);
16268 setMachineCodes(mi++, (byte) 0x0F);
16269 setMachineCodes(mi++, (byte) 0xA3);
16270 emitAbsRegOperands(dstDisp, srcReg);
16271 if (lister != null) lister.RAR(miStart, "BT", dstDisp, srcReg);
16272 }
16273
16274 /**
16275 * Generate a register-index--register BT. That is,
16276 * <PRE>
16277 * [dstBase + dstIndex<<dstScale + dstDisp] BT= srcReg
16278 * </PRE>
16279 *
16280 * @param dstBase the base register
16281 * @param dstIndex the destination index register
16282 * @param dstScale the destination shift amount
16283 * @param dstDisp the destination displacement
16284 * @param srcReg the source register
16285 */
16286 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16287 public final void emitBT_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16288 int miStart = mi;
16289 // no group 1 to 4 prefix byte
16290 generateREXprefix(false, srcReg, dstIndex, dstBase);
16291 setMachineCodes(mi++, (byte) 0x0F);
16292 setMachineCodes(mi++, (byte) 0xA3);
16293 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16294 if (lister != null) lister.RXDR(miStart, "BT", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16295 }
16296
16297 /**
16298 * Generate a register-displacement--register BT. That is,
16299 * <PRE>
16300 * [dstBase + dstDisp] BT= srcReg
16301 * </PRE>
16302 *
16303 * @param dstBase the base register
16304 * @param dstDisp the destination displacement
16305 * @param srcReg the source register
16306 */
16307 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16308 public final void emitBT_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16309 int miStart = mi;
16310 // no group 1 to 4 prefix byte
16311 generateREXprefix(false, srcReg, null, dstBase);
16312 setMachineCodes(mi++, (byte) 0x0F);
16313 setMachineCodes(mi++, (byte) 0xA3);
16314 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16315 if (lister != null) lister.RDR(miStart, "BT", dstBase, dstDisp, srcReg);
16316 }
16317
16318 /**
16319 * Generate a register--register BT. That is,
16320 * <PRE>
16321 * dstReg BT= srcReg
16322 * </PRE>
16323 *
16324 * @param dstReg the destination register
16325 * @param srcReg the source register
16326 */
16327 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16328 public final void emitBT_Reg_Reg(GPR dstReg, GPR srcReg) {
16329 int miStart = mi;
16330 // no group 1 to 4 prefix byte
16331 generateREXprefix(false, srcReg, null, dstReg);
16332 setMachineCodes(mi++, (byte) 0x0F);
16333 setMachineCodes(mi++, (byte) 0xA3);
16334 emitRegRegOperands(dstReg, srcReg);
16335 if (lister != null) lister.RR(miStart, "BT", dstReg, srcReg);
16336 }
16337
16338 /**
16339 * Generate a register--immediate BT. That is,
16340 * <PRE>
16341 * dstReg BT= imm
16342 * </PRE>
16343 *
16344 * @param dstReg the destination register
16345 * @param imm immediate
16346 */
16347 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16348 public final void emitBT_Reg_Imm(GPR dstReg, int imm) {
16349 int miStart = mi;
16350 // no group 1 to 4 prefix byte
16351 generateREXprefix(false, null, null, dstReg);
16352 setMachineCodes(mi++, (byte) 0x0F);
16353 if (fits(imm,8)) {
16354 setMachineCodes(mi++, (byte) 0xBA);
16355 // "register 0x4" is really part of the opcode
16356 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
16357 emitImm8((byte)imm);
16358 } else {
16359 throw new InternalError("Data too large for BT instruction");
16360 }
16361 if (lister != null) lister.RI(miStart, "BT", dstReg, imm);
16362 }
16363
16364 /**
16365 * Generate a register-displacement--immediate BT. That is,
16366 * <PRE>
16367 * [dstBase + dstDisp] BT= imm
16368 * </PRE>
16369 *
16370 * @param dstBase the destination register
16371 * @param dstDisp the destination displacement
16372 * @param imm immediate
16373 */
16374 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16375 public final void emitBT_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16376 int miStart = mi;
16377 // no group 1 to 4 prefix byte
16378 generateREXprefix(false, null, null, dstBase);
16379 setMachineCodes(mi++, (byte) 0x0F);
16380 if (fits(imm,8)) {
16381 setMachineCodes(mi++, (byte) 0xBA);
16382 // "register 0x4" is really part of the opcode
16383 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
16384 emitImm8((byte)imm);
16385 } else {
16386 throw new InternalError("Data too large for BT instruction");
16387 }
16388 if (lister != null) lister.RDI(miStart, "BT", dstBase, dstDisp, imm);
16389 }
16390
16391 /**
16392 * Generate a register-offset--immediate BT. That is,
16393 * <PRE>
16394 * [dstIndex<<dstScale + dstDisp] BT= imm
16395 * </PRE>
16396 *
16397 * @param dstIndex the destination index register
16398 * @param dstScale the destination shift amount
16399 * @param dstDisp the destination displacement
16400 * @param imm immediate
16401 */
16402 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16403 public final void emitBT_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16404 int miStart = mi;
16405 // no group 1 to 4 prefix byte
16406 generateREXprefix(false, null, dstIndex, null);
16407 setMachineCodes(mi++, (byte) 0x0F);
16408 if (fits(imm,8)) {
16409 setMachineCodes(mi++, (byte) 0xBA);
16410 // "register 0x4" is really part of the opcode
16411 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
16412 emitImm8((byte)imm);
16413 } else {
16414 throw new InternalError("Data too large for BT instruction");
16415 }
16416 if (lister != null) lister.RFDI(miStart, "BT", dstIndex, dstScale, dstDisp, imm);
16417 }
16418
16419 /**
16420 * Generate a absolute--immediate BT. That is,
16421 * <PRE>
16422 * [dstDisp] BT= imm
16423 * </PRE>
16424 *
16425 * @param dstDisp the destination displacement
16426 * @param imm immediate
16427 */
16428 public final void emitBT_Abs_Imm(Address dstDisp, int imm) {
16429 int miStart = mi;
16430 // no group 1 to 4 prefix byte
16431 generateREXprefix(false, null, null, null);
16432 setMachineCodes(mi++, (byte) 0x0F);
16433 if (fits(imm,8)) {
16434 setMachineCodes(mi++, (byte) 0xBA);
16435 // "register 0x4" is really part of the opcode
16436 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
16437 emitImm8((byte)imm);
16438 } else {
16439 throw new InternalError("Data too large for BT instruction");
16440 }
16441 if (lister != null) lister.RAI(miStart, "BT", dstDisp, imm);
16442 }
16443
16444 /**
16445 * Generate a register-index--immediate BT. That is,
16446 * <PRE>
16447 * [dstBase + dstIndex<<dstScale + dstDisp] BT= imm
16448 * </PRE>
16449 *
16450 * @param dstBase the destination base register
16451 * @param dstIndex the destination index register
16452 * @param dstScale the destination shift amount
16453 * @param dstDisp the destination displacement
16454 * @param imm immediate
16455 */
16456 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16457 public final void emitBT_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16458 int miStart = mi;
16459 // no group 1 to 4 prefix byte
16460 generateREXprefix(false, null, dstIndex, dstBase);
16461 setMachineCodes(mi++, (byte) 0x0F);
16462 if (fits(imm,8)) {
16463 setMachineCodes(mi++, (byte) 0xBA);
16464 // "register 0x4" is really part of the opcode
16465 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
16466 emitImm8((byte)imm);
16467 } else {
16468 throw new InternalError("Data too large for BT instruction");
16469 }
16470 if (lister != null) lister.RXDI(miStart, "BT", dstBase, dstIndex, dstScale, dstDisp, imm);
16471 }
16472
16473 /**
16474 * Generate a register(indirect)--immediate BT. That is,
16475 * <PRE>
16476 * [dstBase] BT= imm
16477 * </PRE>
16478 *
16479 * @param dstBase the destination base register
16480 * @param imm immediate
16481 */
16482 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16483 public final void emitBT_RegInd_Imm(GPR dstBase, int imm) {
16484 int miStart = mi;
16485 // no group 1 to 4 prefix byte
16486 generateREXprefix(false, null, null, dstBase);
16487 setMachineCodes(mi++, (byte) 0x0F);
16488 if (fits(imm,8)) {
16489 setMachineCodes(mi++, (byte) 0xBA);
16490 // "register 0x4" is really part of the opcode
16491 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
16492 emitImm8((byte)imm);
16493 } else {
16494 throw new InternalError("Data too large for BT instruction");
16495 }
16496 if (lister != null) lister.RNI(miStart, "BT", dstBase, imm);
16497 }
16498
16499 /**
16500 * Generate a register(indirect)--register BTC. That is,
16501 * <PRE>
16502 * [dstBase] BTC= srcReg
16503 * </PRE>
16504 *
16505 * @param dstBase the destination base
16506 * @param srcReg the source register
16507 */
16508 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16509 public final void emitBTC_RegInd_Reg(GPR dstBase, GPR srcReg) {
16510 int miStart = mi;
16511 // no group 1 to 4 prefix byte
16512 generateREXprefix(false, srcReg, null, dstBase);
16513 setMachineCodes(mi++, (byte) 0x0F);
16514 setMachineCodes(mi++, (byte) 0xBB);
16515 emitRegIndirectRegOperands(dstBase, srcReg);
16516 if (lister != null) lister.RNR(miStart, "BTC", dstBase, srcReg);
16517 }
16518
16519 /**
16520 * Generate a register-offset--register BTC. That is,
16521 * <PRE>
16522 * [dstReg<<dstScale + dstDisp] BTC= srcReg
16523 * </PRE>
16524 *
16525 * @param dstIndex the destination index register
16526 * @param dstScale the destination shift amount
16527 * @param dstDisp the destination displacement
16528 * @param srcReg the source register
16529 */
16530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16531 public final void emitBTC_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16532 int miStart = mi;
16533 // no group 1 to 4 prefix byte
16534 generateREXprefix(false, srcReg, dstIndex, null);
16535 setMachineCodes(mi++, (byte) 0x0F);
16536 setMachineCodes(mi++, (byte) 0xBB);
16537 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16538 if (lister != null) lister.RFDR(miStart, "BTC", dstIndex, dstScale, dstDisp, srcReg);
16539 }
16540
16541 /**
16542 * Generate a absolute--register BTC. That is,
16543 * <PRE>
16544 * [dstDisp] BTC= srcReg
16545 * </PRE>
16546 *
16547 * @param dstDisp the destination address
16548 * @param srcReg the source register
16549 */
16550 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16551 public final void emitBTC_Abs_Reg(Address dstDisp, GPR srcReg) {
16552 int miStart = mi;
16553 // no group 1 to 4 prefix byte
16554 generateREXprefix(false, srcReg, null, null);
16555 setMachineCodes(mi++, (byte) 0x0F);
16556 setMachineCodes(mi++, (byte) 0xBB);
16557 emitAbsRegOperands(dstDisp, srcReg);
16558 if (lister != null) lister.RAR(miStart, "BTC", dstDisp, srcReg);
16559 }
16560
16561 /**
16562 * Generate a register-index--register BTC. That is,
16563 * <PRE>
16564 * [dstBase + dstIndex<<dstScale + dstDisp] BTC= srcReg
16565 * </PRE>
16566 *
16567 * @param dstBase the base register
16568 * @param dstIndex the destination index register
16569 * @param dstScale the destination shift amount
16570 * @param dstDisp the destination displacement
16571 * @param srcReg the source register
16572 */
16573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16574 public final void emitBTC_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16575 int miStart = mi;
16576 // no group 1 to 4 prefix byte
16577 generateREXprefix(false, srcReg, dstIndex, dstBase);
16578 setMachineCodes(mi++, (byte) 0x0F);
16579 setMachineCodes(mi++, (byte) 0xBB);
16580 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16581 if (lister != null) lister.RXDR(miStart, "BTC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16582 }
16583
16584 /**
16585 * Generate a register-displacement--register BTC. That is,
16586 * <PRE>
16587 * [dstBase + dstDisp] BTC= srcReg
16588 * </PRE>
16589 *
16590 * @param dstBase the base register
16591 * @param dstDisp the destination displacement
16592 * @param srcReg the source register
16593 */
16594 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16595 public final void emitBTC_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16596 int miStart = mi;
16597 // no group 1 to 4 prefix byte
16598 generateREXprefix(false, srcReg, null, dstBase);
16599 setMachineCodes(mi++, (byte) 0x0F);
16600 setMachineCodes(mi++, (byte) 0xBB);
16601 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16602 if (lister != null) lister.RDR(miStart, "BTC", dstBase, dstDisp, srcReg);
16603 }
16604
16605 /**
16606 * Generate a register--register BTC. That is,
16607 * <PRE>
16608 * dstReg BTC= srcReg
16609 * </PRE>
16610 *
16611 * @param dstReg the destination register
16612 * @param srcReg the source register
16613 */
16614 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16615 public final void emitBTC_Reg_Reg(GPR dstReg, GPR srcReg) {
16616 int miStart = mi;
16617 // no group 1 to 4 prefix byte
16618 generateREXprefix(false, srcReg, null, dstReg);
16619 setMachineCodes(mi++, (byte) 0x0F);
16620 setMachineCodes(mi++, (byte) 0xBB);
16621 emitRegRegOperands(dstReg, srcReg);
16622 if (lister != null) lister.RR(miStart, "BTC", dstReg, srcReg);
16623 }
16624
16625 /**
16626 * Generate a register--immediate BTC. That is,
16627 * <PRE>
16628 * dstReg BTC= imm
16629 * </PRE>
16630 *
16631 * @param dstReg the destination register
16632 * @param imm immediate
16633 */
16634 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16635 public final void emitBTC_Reg_Imm(GPR dstReg, int imm) {
16636 int miStart = mi;
16637 // no group 1 to 4 prefix byte
16638 generateREXprefix(false, null, null, dstReg);
16639 setMachineCodes(mi++, (byte) 0x0F);
16640 if (fits(imm,8)) {
16641 setMachineCodes(mi++, (byte) 0xBA);
16642 // "register 0x7" is really part of the opcode
16643 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
16644 emitImm8((byte)imm);
16645 } else {
16646 throw new InternalError("Data too large for BTC instruction");
16647 }
16648 if (lister != null) lister.RI(miStart, "BTC", dstReg, imm);
16649 }
16650
16651 /**
16652 * Generate a register-displacement--immediate BTC. That is,
16653 * <PRE>
16654 * [dstBase + dstDisp] BTC= imm
16655 * </PRE>
16656 *
16657 * @param dstBase the destination register
16658 * @param dstDisp the destination displacement
16659 * @param imm immediate
16660 */
16661 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16662 public final void emitBTC_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16663 int miStart = mi;
16664 // no group 1 to 4 prefix byte
16665 generateREXprefix(false, null, null, dstBase);
16666 setMachineCodes(mi++, (byte) 0x0F);
16667 if (fits(imm,8)) {
16668 setMachineCodes(mi++, (byte) 0xBA);
16669 // "register 0x7" is really part of the opcode
16670 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
16671 emitImm8((byte)imm);
16672 } else {
16673 throw new InternalError("Data too large for BTC instruction");
16674 }
16675 if (lister != null) lister.RDI(miStart, "BTC", dstBase, dstDisp, imm);
16676 }
16677
16678 /**
16679 * Generate a register-offset--immediate BTC. That is,
16680 * <PRE>
16681 * [dstIndex<<dstScale + dstDisp] BTC= imm
16682 * </PRE>
16683 *
16684 * @param dstIndex the destination index register
16685 * @param dstScale the destination shift amount
16686 * @param dstDisp the destination displacement
16687 * @param imm immediate
16688 */
16689 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16690 public final void emitBTC_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16691 int miStart = mi;
16692 // no group 1 to 4 prefix byte
16693 generateREXprefix(false, null, dstIndex, null);
16694 setMachineCodes(mi++, (byte) 0x0F);
16695 if (fits(imm,8)) {
16696 setMachineCodes(mi++, (byte) 0xBA);
16697 // "register 0x7" is really part of the opcode
16698 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
16699 emitImm8((byte)imm);
16700 } else {
16701 throw new InternalError("Data too large for BTC instruction");
16702 }
16703 if (lister != null) lister.RFDI(miStart, "BTC", dstIndex, dstScale, dstDisp, imm);
16704 }
16705
16706 /**
16707 * Generate a absolute--immediate BTC. That is,
16708 * <PRE>
16709 * [dstDisp] BTC= imm
16710 * </PRE>
16711 *
16712 * @param dstDisp the destination displacement
16713 * @param imm immediate
16714 */
16715 public final void emitBTC_Abs_Imm(Address dstDisp, int imm) {
16716 int miStart = mi;
16717 // no group 1 to 4 prefix byte
16718 generateREXprefix(false, null, null, null);
16719 setMachineCodes(mi++, (byte) 0x0F);
16720 if (fits(imm,8)) {
16721 setMachineCodes(mi++, (byte) 0xBA);
16722 // "register 0x7" is really part of the opcode
16723 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
16724 emitImm8((byte)imm);
16725 } else {
16726 throw new InternalError("Data too large for BTC instruction");
16727 }
16728 if (lister != null) lister.RAI(miStart, "BTC", dstDisp, imm);
16729 }
16730
16731 /**
16732 * Generate a register-index--immediate BTC. That is,
16733 * <PRE>
16734 * [dstBase + dstIndex<<dstScale + dstDisp] BTC= imm
16735 * </PRE>
16736 *
16737 * @param dstBase the destination base register
16738 * @param dstIndex the destination index register
16739 * @param dstScale the destination shift amount
16740 * @param dstDisp the destination displacement
16741 * @param imm immediate
16742 */
16743 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16744 public final void emitBTC_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16745 int miStart = mi;
16746 // no group 1 to 4 prefix byte
16747 generateREXprefix(false, null, dstIndex, dstBase);
16748 setMachineCodes(mi++, (byte) 0x0F);
16749 if (fits(imm,8)) {
16750 setMachineCodes(mi++, (byte) 0xBA);
16751 // "register 0x7" is really part of the opcode
16752 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
16753 emitImm8((byte)imm);
16754 } else {
16755 throw new InternalError("Data too large for BTC instruction");
16756 }
16757 if (lister != null) lister.RXDI(miStart, "BTC", dstBase, dstIndex, dstScale, dstDisp, imm);
16758 }
16759
16760 /**
16761 * Generate a register(indirect)--immediate BTC. That is,
16762 * <PRE>
16763 * [dstBase] BTC= imm
16764 * </PRE>
16765 *
16766 * @param dstBase the destination base register
16767 * @param imm immediate
16768 */
16769 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16770 public final void emitBTC_RegInd_Imm(GPR dstBase, int imm) {
16771 int miStart = mi;
16772 // no group 1 to 4 prefix byte
16773 generateREXprefix(false, null, null, dstBase);
16774 setMachineCodes(mi++, (byte) 0x0F);
16775 if (fits(imm,8)) {
16776 setMachineCodes(mi++, (byte) 0xBA);
16777 // "register 0x7" is really part of the opcode
16778 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
16779 emitImm8((byte)imm);
16780 } else {
16781 throw new InternalError("Data too large for BTC instruction");
16782 }
16783 if (lister != null) lister.RNI(miStart, "BTC", dstBase, imm);
16784 }
16785
16786 /**
16787 * Generate a register(indirect)--register BTR. That is,
16788 * <PRE>
16789 * [dstBase] BTR= srcReg
16790 * </PRE>
16791 *
16792 * @param dstBase the destination base
16793 * @param srcReg the source register
16794 */
16795 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16796 public final void emitBTR_RegInd_Reg(GPR dstBase, GPR srcReg) {
16797 int miStart = mi;
16798 // no group 1 to 4 prefix byte
16799 generateREXprefix(false, srcReg, null, dstBase);
16800 setMachineCodes(mi++, (byte) 0x0F);
16801 setMachineCodes(mi++, (byte) 0xB3);
16802 emitRegIndirectRegOperands(dstBase, srcReg);
16803 if (lister != null) lister.RNR(miStart, "BTR", dstBase, srcReg);
16804 }
16805
16806 /**
16807 * Generate a register-offset--register BTR. That is,
16808 * <PRE>
16809 * [dstReg<<dstScale + dstDisp] BTR= srcReg
16810 * </PRE>
16811 *
16812 * @param dstIndex the destination index register
16813 * @param dstScale the destination shift amount
16814 * @param dstDisp the destination displacement
16815 * @param srcReg the source register
16816 */
16817 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16818 public final void emitBTR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16819 int miStart = mi;
16820 // no group 1 to 4 prefix byte
16821 generateREXprefix(false, srcReg, dstIndex, null);
16822 setMachineCodes(mi++, (byte) 0x0F);
16823 setMachineCodes(mi++, (byte) 0xB3);
16824 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16825 if (lister != null) lister.RFDR(miStart, "BTR", dstIndex, dstScale, dstDisp, srcReg);
16826 }
16827
16828 /**
16829 * Generate a absolute--register BTR. That is,
16830 * <PRE>
16831 * [dstDisp] BTR= srcReg
16832 * </PRE>
16833 *
16834 * @param dstDisp the destination address
16835 * @param srcReg the source register
16836 */
16837 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16838 public final void emitBTR_Abs_Reg(Address dstDisp, GPR srcReg) {
16839 int miStart = mi;
16840 // no group 1 to 4 prefix byte
16841 generateREXprefix(false, srcReg, null, null);
16842 setMachineCodes(mi++, (byte) 0x0F);
16843 setMachineCodes(mi++, (byte) 0xB3);
16844 emitAbsRegOperands(dstDisp, srcReg);
16845 if (lister != null) lister.RAR(miStart, "BTR", dstDisp, srcReg);
16846 }
16847
16848 /**
16849 * Generate a register-index--register BTR. That is,
16850 * <PRE>
16851 * [dstBase + dstIndex<<dstScale + dstDisp] BTR= srcReg
16852 * </PRE>
16853 *
16854 * @param dstBase the base register
16855 * @param dstIndex the destination index register
16856 * @param dstScale the destination shift amount
16857 * @param dstDisp the destination displacement
16858 * @param srcReg the source register
16859 */
16860 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16861 public final void emitBTR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16862 int miStart = mi;
16863 // no group 1 to 4 prefix byte
16864 generateREXprefix(false, srcReg, dstIndex, dstBase);
16865 setMachineCodes(mi++, (byte) 0x0F);
16866 setMachineCodes(mi++, (byte) 0xB3);
16867 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16868 if (lister != null) lister.RXDR(miStart, "BTR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16869 }
16870
16871 /**
16872 * Generate a register-displacement--register BTR. That is,
16873 * <PRE>
16874 * [dstBase + dstDisp] BTR= srcReg
16875 * </PRE>
16876 *
16877 * @param dstBase the base register
16878 * @param dstDisp the destination displacement
16879 * @param srcReg the source register
16880 */
16881 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16882 public final void emitBTR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16883 int miStart = mi;
16884 // no group 1 to 4 prefix byte
16885 generateREXprefix(false, srcReg, null, dstBase);
16886 setMachineCodes(mi++, (byte) 0x0F);
16887 setMachineCodes(mi++, (byte) 0xB3);
16888 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16889 if (lister != null) lister.RDR(miStart, "BTR", dstBase, dstDisp, srcReg);
16890 }
16891
16892 /**
16893 * Generate a register--register BTR. That is,
16894 * <PRE>
16895 * dstReg BTR= srcReg
16896 * </PRE>
16897 *
16898 * @param dstReg the destination register
16899 * @param srcReg the source register
16900 */
16901 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16902 public final void emitBTR_Reg_Reg(GPR dstReg, GPR srcReg) {
16903 int miStart = mi;
16904 // no group 1 to 4 prefix byte
16905 generateREXprefix(false, srcReg, null, dstReg);
16906 setMachineCodes(mi++, (byte) 0x0F);
16907 setMachineCodes(mi++, (byte) 0xB3);
16908 emitRegRegOperands(dstReg, srcReg);
16909 if (lister != null) lister.RR(miStart, "BTR", dstReg, srcReg);
16910 }
16911
16912 /**
16913 * Generate a register--immediate BTR. That is,
16914 * <PRE>
16915 * dstReg BTR= imm
16916 * </PRE>
16917 *
16918 * @param dstReg the destination register
16919 * @param imm immediate
16920 */
16921 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16922 public final void emitBTR_Reg_Imm(GPR dstReg, int imm) {
16923 int miStart = mi;
16924 // no group 1 to 4 prefix byte
16925 generateREXprefix(false, null, null, dstReg);
16926 setMachineCodes(mi++, (byte) 0x0F);
16927 if (fits(imm,8)) {
16928 setMachineCodes(mi++, (byte) 0xBA);
16929 // "register 0x6" is really part of the opcode
16930 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
16931 emitImm8((byte)imm);
16932 } else {
16933 throw new InternalError("Data too large for BTR instruction");
16934 }
16935 if (lister != null) lister.RI(miStart, "BTR", dstReg, imm);
16936 }
16937
16938 /**
16939 * Generate a register-displacement--immediate BTR. That is,
16940 * <PRE>
16941 * [dstBase + dstDisp] BTR= imm
16942 * </PRE>
16943 *
16944 * @param dstBase the destination register
16945 * @param dstDisp the destination displacement
16946 * @param imm immediate
16947 */
16948 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16949 public final void emitBTR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16950 int miStart = mi;
16951 // no group 1 to 4 prefix byte
16952 generateREXprefix(false, null, null, dstBase);
16953 setMachineCodes(mi++, (byte) 0x0F);
16954 if (fits(imm,8)) {
16955 setMachineCodes(mi++, (byte) 0xBA);
16956 // "register 0x6" is really part of the opcode
16957 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
16958 emitImm8((byte)imm);
16959 } else {
16960 throw new InternalError("Data too large for BTR instruction");
16961 }
16962 if (lister != null) lister.RDI(miStart, "BTR", dstBase, dstDisp, imm);
16963 }
16964
16965 /**
16966 * Generate a register-offset--immediate BTR. That is,
16967 * <PRE>
16968 * [dstIndex<<dstScale + dstDisp] BTR= imm
16969 * </PRE>
16970 *
16971 * @param dstIndex the destination index register
16972 * @param dstScale the destination shift amount
16973 * @param dstDisp the destination displacement
16974 * @param imm immediate
16975 */
16976 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16977 public final void emitBTR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16978 int miStart = mi;
16979 // no group 1 to 4 prefix byte
16980 generateREXprefix(false, null, dstIndex, null);
16981 setMachineCodes(mi++, (byte) 0x0F);
16982 if (fits(imm,8)) {
16983 setMachineCodes(mi++, (byte) 0xBA);
16984 // "register 0x6" is really part of the opcode
16985 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16986 emitImm8((byte)imm);
16987 } else {
16988 throw new InternalError("Data too large for BTR instruction");
16989 }
16990 if (lister != null) lister.RFDI(miStart, "BTR", dstIndex, dstScale, dstDisp, imm);
16991 }
16992
16993 /**
16994 * Generate a absolute--immediate BTR. That is,
16995 * <PRE>
16996 * [dstDisp] BTR= imm
16997 * </PRE>
16998 *
16999 * @param dstDisp the destination displacement
17000 * @param imm immediate
17001 */
17002 public final void emitBTR_Abs_Imm(Address dstDisp, int imm) {
17003 int miStart = mi;
17004 // no group 1 to 4 prefix byte
17005 generateREXprefix(false, null, null, null);
17006 setMachineCodes(mi++, (byte) 0x0F);
17007 if (fits(imm,8)) {
17008 setMachineCodes(mi++, (byte) 0xBA);
17009 // "register 0x6" is really part of the opcode
17010 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
17011 emitImm8((byte)imm);
17012 } else {
17013 throw new InternalError("Data too large for BTR instruction");
17014 }
17015 if (lister != null) lister.RAI(miStart, "BTR", dstDisp, imm);
17016 }
17017
17018 /**
17019 * Generate a register-index--immediate BTR. That is,
17020 * <PRE>
17021 * [dstBase + dstIndex<<dstScale + dstDisp] BTR= imm
17022 * </PRE>
17023 *
17024 * @param dstBase the destination base register
17025 * @param dstIndex the destination index register
17026 * @param dstScale the destination shift amount
17027 * @param dstDisp the destination displacement
17028 * @param imm immediate
17029 */
17030 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17031 public final void emitBTR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17032 int miStart = mi;
17033 // no group 1 to 4 prefix byte
17034 generateREXprefix(false, null, dstIndex, dstBase);
17035 setMachineCodes(mi++, (byte) 0x0F);
17036 if (fits(imm,8)) {
17037 setMachineCodes(mi++, (byte) 0xBA);
17038 // "register 0x6" is really part of the opcode
17039 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
17040 emitImm8((byte)imm);
17041 } else {
17042 throw new InternalError("Data too large for BTR instruction");
17043 }
17044 if (lister != null) lister.RXDI(miStart, "BTR", dstBase, dstIndex, dstScale, dstDisp, imm);
17045 }
17046
17047 /**
17048 * Generate a register(indirect)--immediate BTR. That is,
17049 * <PRE>
17050 * [dstBase] BTR= imm
17051 * </PRE>
17052 *
17053 * @param dstBase the destination base register
17054 * @param imm immediate
17055 */
17056 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17057 public final void emitBTR_RegInd_Imm(GPR dstBase, int imm) {
17058 int miStart = mi;
17059 // no group 1 to 4 prefix byte
17060 generateREXprefix(false, null, null, dstBase);
17061 setMachineCodes(mi++, (byte) 0x0F);
17062 if (fits(imm,8)) {
17063 setMachineCodes(mi++, (byte) 0xBA);
17064 // "register 0x6" is really part of the opcode
17065 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
17066 emitImm8((byte)imm);
17067 } else {
17068 throw new InternalError("Data too large for BTR instruction");
17069 }
17070 if (lister != null) lister.RNI(miStart, "BTR", dstBase, imm);
17071 }
17072
17073 /**
17074 * Generate a register(indirect)--register BTS. That is,
17075 * <PRE>
17076 * [dstBase] BTS= srcReg
17077 * </PRE>
17078 *
17079 * @param dstBase the destination base
17080 * @param srcReg the source register
17081 */
17082 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17083 public final void emitBTS_RegInd_Reg(GPR dstBase, GPR srcReg) {
17084 int miStart = mi;
17085 // no group 1 to 4 prefix byte
17086 generateREXprefix(false, srcReg, null, dstBase);
17087 setMachineCodes(mi++, (byte) 0x0F);
17088 setMachineCodes(mi++, (byte) 0xAB);
17089 emitRegIndirectRegOperands(dstBase, srcReg);
17090 if (lister != null) lister.RNR(miStart, "BTS", dstBase, srcReg);
17091 }
17092
17093 /**
17094 * Generate a register-offset--register BTS. That is,
17095 * <PRE>
17096 * [dstReg<<dstScale + dstDisp] BTS= srcReg
17097 * </PRE>
17098 *
17099 * @param dstIndex the destination index register
17100 * @param dstScale the destination shift amount
17101 * @param dstDisp the destination displacement
17102 * @param srcReg the source register
17103 */
17104 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
17105 public final void emitBTS_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
17106 int miStart = mi;
17107 // no group 1 to 4 prefix byte
17108 generateREXprefix(false, srcReg, dstIndex, null);
17109 setMachineCodes(mi++, (byte) 0x0F);
17110 setMachineCodes(mi++, (byte) 0xAB);
17111 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
17112 if (lister != null) lister.RFDR(miStart, "BTS", dstIndex, dstScale, dstDisp, srcReg);
17113 }
17114
17115 /**
17116 * Generate a absolute--register BTS. That is,
17117 * <PRE>
17118 * [dstDisp] BTS= srcReg
17119 * </PRE>
17120 *
17121 * @param dstDisp the destination address
17122 * @param srcReg the source register
17123 */
17124 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
17125 public final void emitBTS_Abs_Reg(Address dstDisp, GPR srcReg) {
17126 int miStart = mi;
17127 // no group 1 to 4 prefix byte
17128 generateREXprefix(false, srcReg, null, null);
17129 setMachineCodes(mi++, (byte) 0x0F);
17130 setMachineCodes(mi++, (byte) 0xAB);
17131 emitAbsRegOperands(dstDisp, srcReg);
17132 if (lister != null) lister.RAR(miStart, "BTS", dstDisp, srcReg);
17133 }
17134
17135 /**
17136 * Generate a register-index--register BTS. That is,
17137 * <PRE>
17138 * [dstBase + dstIndex<<dstScale + dstDisp] BTS= srcReg
17139 * </PRE>
17140 *
17141 * @param dstBase the base register
17142 * @param dstIndex the destination index register
17143 * @param dstScale the destination shift amount
17144 * @param dstDisp the destination displacement
17145 * @param srcReg the source register
17146 */
17147 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
17148 public final void emitBTS_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
17149 int miStart = mi;
17150 // no group 1 to 4 prefix byte
17151 generateREXprefix(false, srcReg, dstIndex, dstBase);
17152 setMachineCodes(mi++, (byte) 0x0F);
17153 setMachineCodes(mi++, (byte) 0xAB);
17154 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
17155 if (lister != null) lister.RXDR(miStart, "BTS", dstBase, dstIndex, dstScale, dstDisp, srcReg);
17156 }
17157
17158 /**
17159 * Generate a register-displacement--register BTS. That is,
17160 * <PRE>
17161 * [dstBase + dstDisp] BTS= srcReg
17162 * </PRE>
17163 *
17164 * @param dstBase the base register
17165 * @param dstDisp the destination displacement
17166 * @param srcReg the source register
17167 */
17168 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
17169 public final void emitBTS_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
17170 int miStart = mi;
17171 // no group 1 to 4 prefix byte
17172 generateREXprefix(false, srcReg, null, dstBase);
17173 setMachineCodes(mi++, (byte) 0x0F);
17174 setMachineCodes(mi++, (byte) 0xAB);
17175 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
17176 if (lister != null) lister.RDR(miStart, "BTS", dstBase, dstDisp, srcReg);
17177 }
17178
17179 /**
17180 * Generate a register--register BTS. That is,
17181 * <PRE>
17182 * dstReg BTS= srcReg
17183 * </PRE>
17184 *
17185 * @param dstReg the destination register
17186 * @param srcReg the source register
17187 */
17188 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17189 public final void emitBTS_Reg_Reg(GPR dstReg, GPR srcReg) {
17190 int miStart = mi;
17191 // no group 1 to 4 prefix byte
17192 generateREXprefix(false, srcReg, null, dstReg);
17193 setMachineCodes(mi++, (byte) 0x0F);
17194 setMachineCodes(mi++, (byte) 0xAB);
17195 emitRegRegOperands(dstReg, srcReg);
17196 if (lister != null) lister.RR(miStart, "BTS", dstReg, srcReg);
17197 }
17198
17199 /**
17200 * Generate a register--immediate BTS. That is,
17201 * <PRE>
17202 * dstReg BTS= imm
17203 * </PRE>
17204 *
17205 * @param dstReg the destination register
17206 * @param imm immediate
17207 */
17208 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17209 public final void emitBTS_Reg_Imm(GPR dstReg, int imm) {
17210 int miStart = mi;
17211 // no group 1 to 4 prefix byte
17212 generateREXprefix(false, null, null, dstReg);
17213 setMachineCodes(mi++, (byte) 0x0F);
17214 if (fits(imm,8)) {
17215 setMachineCodes(mi++, (byte) 0xBA);
17216 // "register 0x5" is really part of the opcode
17217 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
17218 emitImm8((byte)imm);
17219 } else {
17220 throw new InternalError("Data too large for BTS instruction");
17221 }
17222 if (lister != null) lister.RI(miStart, "BTS", dstReg, imm);
17223 }
17224
17225 /**
17226 * Generate a register-displacement--immediate BTS. That is,
17227 * <PRE>
17228 * [dstBase + dstDisp] BTS= imm
17229 * </PRE>
17230 *
17231 * @param dstBase the destination register
17232 * @param dstDisp the destination displacement
17233 * @param imm immediate
17234 */
17235 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17236 public final void emitBTS_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
17237 int miStart = mi;
17238 // no group 1 to 4 prefix byte
17239 generateREXprefix(false, null, null, dstBase);
17240 setMachineCodes(mi++, (byte) 0x0F);
17241 if (fits(imm,8)) {
17242 setMachineCodes(mi++, (byte) 0xBA);
17243 // "register 0x5" is really part of the opcode
17244 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
17245 emitImm8((byte)imm);
17246 } else {
17247 throw new InternalError("Data too large for BTS instruction");
17248 }
17249 if (lister != null) lister.RDI(miStart, "BTS", dstBase, dstDisp, imm);
17250 }
17251
17252 /**
17253 * Generate a register-offset--immediate BTS. That is,
17254 * <PRE>
17255 * [dstIndex<<dstScale + dstDisp] BTS= imm
17256 * </PRE>
17257 *
17258 * @param dstIndex the destination index register
17259 * @param dstScale the destination shift amount
17260 * @param dstDisp the destination displacement
17261 * @param imm immediate
17262 */
17263 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17264 public final void emitBTS_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17265 int miStart = mi;
17266 // no group 1 to 4 prefix byte
17267 generateREXprefix(false, null, dstIndex, null);
17268 setMachineCodes(mi++, (byte) 0x0F);
17269 if (fits(imm,8)) {
17270 setMachineCodes(mi++, (byte) 0xBA);
17271 // "register 0x5" is really part of the opcode
17272 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
17273 emitImm8((byte)imm);
17274 } else {
17275 throw new InternalError("Data too large for BTS instruction");
17276 }
17277 if (lister != null) lister.RFDI(miStart, "BTS", dstIndex, dstScale, dstDisp, imm);
17278 }
17279
17280 /**
17281 * Generate a absolute--immediate BTS. That is,
17282 * <PRE>
17283 * [dstDisp] BTS= imm
17284 * </PRE>
17285 *
17286 * @param dstDisp the destination displacement
17287 * @param imm immediate
17288 */
17289 public final void emitBTS_Abs_Imm(Address dstDisp, int imm) {
17290 int miStart = mi;
17291 // no group 1 to 4 prefix byte
17292 generateREXprefix(false, null, null, null);
17293 setMachineCodes(mi++, (byte) 0x0F);
17294 if (fits(imm,8)) {
17295 setMachineCodes(mi++, (byte) 0xBA);
17296 // "register 0x5" is really part of the opcode
17297 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
17298 emitImm8((byte)imm);
17299 } else {
17300 throw new InternalError("Data too large for BTS instruction");
17301 }
17302 if (lister != null) lister.RAI(miStart, "BTS", dstDisp, imm);
17303 }
17304
17305 /**
17306 * Generate a register-index--immediate BTS. That is,
17307 * <PRE>
17308 * [dstBase + dstIndex<<dstScale + dstDisp] BTS= imm
17309 * </PRE>
17310 *
17311 * @param dstBase the destination base register
17312 * @param dstIndex the destination index register
17313 * @param dstScale the destination shift amount
17314 * @param dstDisp the destination displacement
17315 * @param imm immediate
17316 */
17317 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17318 public final void emitBTS_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17319 int miStart = mi;
17320 // no group 1 to 4 prefix byte
17321 generateREXprefix(false, null, dstIndex, dstBase);
17322 setMachineCodes(mi++, (byte) 0x0F);
17323 if (fits(imm,8)) {
17324 setMachineCodes(mi++, (byte) 0xBA);
17325 // "register 0x5" is really part of the opcode
17326 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
17327 emitImm8((byte)imm);
17328 } else {
17329 throw new InternalError("Data too large for BTS instruction");
17330 }
17331 if (lister != null) lister.RXDI(miStart, "BTS", dstBase, dstIndex, dstScale, dstDisp, imm);
17332 }
17333
17334 /**
17335 * Generate a register(indirect)--immediate BTS. That is,
17336 * <PRE>
17337 * [dstBase] BTS= imm
17338 * </PRE>
17339 *
17340 * @param dstBase the destination base register
17341 * @param imm immediate
17342 */
17343 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17344 public final void emitBTS_RegInd_Imm(GPR dstBase, int imm) {
17345 int miStart = mi;
17346 // no group 1 to 4 prefix byte
17347 generateREXprefix(false, null, null, dstBase);
17348 setMachineCodes(mi++, (byte) 0x0F);
17349 if (fits(imm,8)) {
17350 setMachineCodes(mi++, (byte) 0xBA);
17351 // "register 0x5" is really part of the opcode
17352 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
17353 emitImm8((byte)imm);
17354 } else {
17355 throw new InternalError("Data too large for BTS instruction");
17356 }
17357 if (lister != null) lister.RNI(miStart, "BTS", dstBase, imm);
17358 }
17359
17360 /**
17361 * Generate a CALL to a label or immediate. That is,
17362 * <PRE>
17363 * pc = {future address from label | imm}
17364 * </PRE>
17365 *
17366 * @param imm offset to immediate CALL to. 0 means use
17367 * label. Immediate is assumed to be within current instructions.
17368 * @param label label to branch to (used when imm == 0)
17369 */
17370 public final void emitCALL_ImmOrLabel(int imm, int label) {
17371 if (imm == 0)
17372 emitCALL_Label(label);
17373 else
17374 emitCALL_Imm(imm);
17375 }
17376
17377 /**
17378 * Branch to the given target with a CALL instruction
17379 * <PRE>
17380 * IP = (instruction @ label)
17381 * </PRE>
17382 *
17383 * This emit method is expecting only a forward branch (that is
17384 * what the Label operand means); it creates a ForwardReference
17385 * to the given label, and puts it into the assembler's list of
17386 * references to resolve. This emitter knows the branch is
17387 * unconditional, so it uses
17388 * {@link org.jikesrvm.compilers.common.assembler.ForwardReference.UnconditionalBranch}
17389 * as the forward reference type to create.
17390 *
17391 * All forward branches have a label as the branch target; clients
17392 * can arbirarily associate labels and instructions, but must be
17393 * consistent in giving the chosen label as the target of branches
17394 * to an instruction and calling resolveForwardBranches with the
17395 * given label immediately before emitting the target instruction.
17396 * See the header comments of ForwardReference for more details.
17397 *
17398 * @param label the label associated with the branch target instrucion
17399 */
17400 public final void emitCALL_Label(int label) {
17401 int miStart = mi;
17402 ForwardReference r =
17403 new ForwardReference.UnconditionalBranch(mi, label);
17404 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
17405 setMachineCodes(mi++, (byte) 0xE8);
17406 mi += 4; // leave space for displacement
17407 if (lister != null) lister.I(miStart, "CALL", label);
17408 }
17409
17410 /**
17411 * Generate a CALL to immediate. That is,
17412 * <PRE>
17413 * pc = imm
17414 * </PRE>
17415 *
17416 * @param imm offset to immediate CALL to (within current instructions)
17417 */
17418 public final void emitCALL_Imm(int imm) {
17419 int miStart = mi;
17420 setMachineCodes(mi++, (byte) 0xE8);
17421 // offset of next instruction (this instruction is 5 bytes,
17422 // but we just accounted for one of them in the mi++ above)
17423 emitImm32(imm - (mi + 4));
17424 if (lister != null) lister.I(miStart, "CALL", imm);
17425 }
17426
17427 /**
17428 * Generate a CALL to register. That is,
17429 * <PRE>
17430 * pc = dstReg
17431 * </PRE>
17432 *
17433 * @param dstReg register containing destination address
17434 */
17435 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17436 public final void emitCALL_Reg(GPR dstReg) {
17437 int miStart = mi;
17438 generateREXprefix(false, null, null, dstReg);
17439 setMachineCodes(mi++, (byte) 0xFF);
17440 // "register 0x2" is really part of the CALL opcode
17441 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
17442 if (lister != null) lister.R(miStart, "CALL", dstReg);
17443 }
17444
17445 /**
17446 * Generate a CALL to register and displacement. That is,
17447 * <PRE>
17448 * pc = [dstBase + dstDisp]
17449 * </PRE>
17450 *
17451 * @param dstBase the destination base address register
17452 * @param dstDisp the destination displacement
17453 */
17454 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17455 public final void emitCALL_RegDisp(GPR dstBase, Offset dstDisp) {
17456 int miStart = mi;
17457 generateREXprefix(false, null, null, dstBase);
17458 setMachineCodes(mi++, (byte) 0xFF);
17459 // "register 0x2" is really part of the CALL opcode
17460 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
17461 if (lister != null) lister.RD(miStart, "CALL", dstBase, dstDisp);
17462 }
17463
17464 /**
17465 * Generate a CALL to register indirect. That is,
17466 * <PRE>
17467 * pc = [dstBase]
17468 * </PRE>
17469 *
17470 * @param dstBase the destination base address register
17471 */
17472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17473 public final void emitCALL_RegInd(GPR dstBase) {
17474 int miStart = mi;
17475 generateREXprefix(false, null, null, dstBase);
17476 setMachineCodes(mi++, (byte) 0xFF);
17477 // "register 0x2" is really part of the CALL opcode
17478 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
17479 if (lister != null) lister.RN(miStart, "CALL", dstBase);
17480 }
17481
17482 /**
17483 * Generate a CALL to register offset. That is,
17484 * <PRE>
17485 * pc = [dstIndex<<dstScale + dstDisp]
17486 * </PRE>
17487 *
17488 * @param dstIndex the destination index register
17489 * @param dstScale the destination shift amount
17490 * @param dstDisp the destination displacement
17491 */
17492 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17493 public final void emitCALL_RegOff(GPR dstIndex, short dstScale, Offset dstDisp) {
17494 int miStart = mi;
17495 generateREXprefix(false, null, dstIndex, null);
17496 setMachineCodes(mi++, (byte) 0xFF);
17497 // "register 0x2" is really part of the CALL opcode
17498 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
17499 if (lister != null) lister.RFD(miStart, "CALL", dstIndex, dstScale, dstDisp);
17500 }
17501
17502 /**
17503 * Generate a CALL to absolute address. That is,
17504 * <PRE>
17505 * pc = [dstDisp]
17506 * </PRE>
17507 *
17508 * @param dstDisp the destination displacement
17509 */
17510 public final void emitCALL_Abs(Address dstDisp) {
17511 int miStart = mi;
17512 setMachineCodes(mi++, (byte) 0xFF);
17513 // "register 0x2" is really part of the CALL opcode
17514 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
17515 if (lister != null) lister.RA(miStart, "CALL", dstDisp);
17516 }
17517
17518 /**
17519 * Generate a CALL to register offset. That is,
17520 * <PRE>
17521 * pc = [dstBase + dstIndex<<dstScale + dstDisp]
17522 * </PRE>
17523 *
17524 * @param dstBase the destination base register
17525 * @param dstIndex the destination index register
17526 * @param dstScale the destination shift amount
17527 * @param dstDisp the destination displacement
17528 */
17529 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17530 public final void emitCALL_RegIdx(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp) {
17531 int miStart = mi;
17532 generateREXprefix(false, null, dstIndex, dstBase);
17533 setMachineCodes(mi++, (byte) 0xFF);
17534 // "register 0x2" is really part of the CALL opcode
17535 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
17536 if (lister != null) lister.RXD(miStart, "CALL", dstBase, dstIndex, dstScale, dstDisp);
17537 }
17538
17539 /**
17540 * Generate a JMP to a label or immediate. That is,
17541 * <PRE>
17542 * pc = {future address from label | imm}
17543 * </PRE>
17544 *
17545 * @param imm offset to immediate JMP to. 0 means use
17546 * label. Immediate is assumed to be within current instructions.
17547 * @param label label to branch to (used when imm == 0)
17548 */
17549 public final void emitJMP_ImmOrLabel(int imm, int label) {
17550 if (imm == 0)
17551 emitJMP_Label(label);
17552 else
17553 emitJMP_Imm(imm);
17554 }
17555
17556 /**
17557 * Branch to the given target with a JMP instruction
17558 * <PRE>
17559 * IP = (instruction @ label)
17560 * </PRE>
17561 *
17562 * This emit method is expecting only a forward branch (that is
17563 * what the Label operand means); it creates a ForwardReference
17564 * to the given label, and puts it into the assembler's list of
17565 * references to resolve. This emitter knows the branch is
17566 * unconditional, so it uses
17567 * {@link org.jikesrvm.compilers.common.assembler.ForwardReference.UnconditionalBranch}
17568 * as the forward reference type to create.
17569 *
17570 * All forward branches have a label as the branch target; clients
17571 * can arbirarily associate labels and instructions, but must be
17572 * consistent in giving the chosen label as the target of branches
17573 * to an instruction and calling resolveForwardBranches with the
17574 * given label immediately before emitting the target instruction.
17575 * See the header comments of ForwardReference for more details.
17576 *
17577 * @param label the label associated with the branch target instrucion
17578 */
17579 public final void emitJMP_Label(int label) {
17580 int miStart = mi;
17581 ForwardReference r =
17582 new ForwardReference.UnconditionalBranch(mi, label);
17583 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
17584 setMachineCodes(mi++, (byte) 0xE9);
17585 mi += 4; // leave space for displacement
17586 if (lister != null) lister.I(miStart, "JMP", label);
17587 }
17588
17589 /**
17590 * Generate a JMP to immediate. That is,
17591 * <PRE>
17592 * pc = imm
17593 * </PRE>
17594 *
17595 * @param imm offset to immediate JMP to (within current instructions)
17596 */
17597 public final void emitJMP_Imm(int imm) {
17598 int miStart = mi;
17599 // can we fit the offset from the next instruction into 8
17600 // bits, assuming this instruction is 2 bytes (which it will
17601 // be if the offset fits into 8 bits)?
17602 int relOffset = imm - (mi + 2);
17603 if (fits(relOffset,8)) {
17604 // yes, so use short form.
17605 setMachineCodes(mi++, (byte) 0xEB);
17606 emitImm8((byte) relOffset);
17607 } else {
17608 // no, must use 32 bit offset and ignore relOffset to
17609 // account for the fact that this instruction now has to
17610 // be 5 bytes long.
17611 setMachineCodes(mi++, (byte) 0xE9);
17612 // offset of next instruction (this instruction is 5 bytes,
17613 // but we just accounted for one of them in the mi++ above)
17614 emitImm32(imm - (mi + 4));
17615 }
17616 if (lister != null) lister.I(miStart, "JMP", imm);
17617 }
17618
17619 /**
17620 * Generate a JMP to register. That is,
17621 * <PRE>
17622 * pc = dstReg
17623 * </PRE>
17624 *
17625 * @param dstReg register containing destination address
17626 */
17627 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17628 public final void emitJMP_Reg(GPR dstReg) {
17629 int miStart = mi;
17630 generateREXprefix(false, null, null, dstReg);
17631 setMachineCodes(mi++, (byte) 0xFF);
17632 // "register 0x4" is really part of the JMP opcode
17633 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
17634 if (lister != null) lister.R(miStart, "JMP", dstReg);
17635 }
17636
17637 /**
17638 * Generate a JMP to register and displacement. That is,
17639 * <PRE>
17640 * pc = [dstBase + dstDisp]
17641 * </PRE>
17642 *
17643 * @param dstBase the destination base address register
17644 * @param dstDisp the destination displacement
17645 */
17646 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17647 public final void emitJMP_RegDisp(GPR dstBase, Offset dstDisp) {
17648 int miStart = mi;
17649 generateREXprefix(false, null, null, dstBase);
17650 setMachineCodes(mi++, (byte) 0xFF);
17651 // "register 0x4" is really part of the JMP opcode
17652 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
17653 if (lister != null) lister.RD(miStart, "JMP", dstBase, dstDisp);
17654 }
17655
17656 /**
17657 * Generate a JMP to register indirect. That is,
17658 * <PRE>
17659 * pc = [dstBase]
17660 * </PRE>
17661 *
17662 * @param dstBase the destination base address register
17663 */
17664 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17665 public final void emitJMP_RegInd(GPR dstBase) {
17666 int miStart = mi;
17667 generateREXprefix(false, null, null, dstBase);
17668 setMachineCodes(mi++, (byte) 0xFF);
17669 // "register 0x4" is really part of the JMP opcode
17670 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
17671 if (lister != null) lister.RN(miStart, "JMP", dstBase);
17672 }
17673
17674 /**
17675 * Generate a JMP to register offset. That is,
17676 * <PRE>
17677 * pc = [dstIndex<<dstScale + dstDisp]
17678 * </PRE>
17679 *
17680 * @param dstIndex the destination index register
17681 * @param dstScale the destination shift amount
17682 * @param dstDisp the destination displacement
17683 */
17684 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17685 public final void emitJMP_RegOff(GPR dstIndex, short dstScale, Offset dstDisp) {
17686 int miStart = mi;
17687 generateREXprefix(false, null, dstIndex, null);
17688 setMachineCodes(mi++, (byte) 0xFF);
17689 // "register 0x4" is really part of the JMP opcode
17690 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
17691 if (lister != null) lister.RFD(miStart, "JMP", dstIndex, dstScale, dstDisp);
17692 }
17693
17694 /**
17695 * Generate a JMP to absolute address. That is,
17696 * <PRE>
17697 * pc = [dstDisp]
17698 * </PRE>
17699 *
17700 * @param dstDisp the destination displacement
17701 */
17702 public final void emitJMP_Abs(Address dstDisp) {
17703 int miStart = mi;
17704 setMachineCodes(mi++, (byte) 0xFF);
17705 // "register 0x4" is really part of the JMP opcode
17706 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
17707 if (lister != null) lister.RA(miStart, "JMP", dstDisp);
17708 }
17709
17710 /**
17711 * Generate a JMP to register offset. That is,
17712 * <PRE>
17713 * pc = [dstBase + dstIndex<<dstScale + dstDisp]
17714 * </PRE>
17715 *
17716 * @param dstBase the destination base register
17717 * @param dstIndex the destination index register
17718 * @param dstScale the destination shift amount
17719 * @param dstDisp the destination displacement
17720 */
17721 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17722 public final void emitJMP_RegIdx(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp) {
17723 int miStart = mi;
17724 generateREXprefix(false, null, dstIndex, dstBase);
17725 setMachineCodes(mi++, (byte) 0xFF);
17726 // "register 0x4" is really part of the JMP opcode
17727 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
17728 if (lister != null) lister.RXD(miStart, "JMP", dstBase, dstIndex, dstScale, dstDisp);
17729 }
17730
17731 /**
17732 * Generate a DEC on a register. That is,
17733 * <PRE>
17734 * -- reg
17735 * </PRE>
17736 *
17737 * @param reg register to operate upon
17738 */
17739 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17740 public void emitDEC_Reg(GPR reg) {
17741 int miStart = mi;
17742 // no group 1 to 4 prefix byte
17743 generateREXprefix(false, null, null, reg);
17744 if (!VM.buildFor32Addr()) {
17745 setMachineCodes(mi++, (byte) (0xFF));
17746 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
17747 } else {
17748 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
17749 }
17750 if (lister != null) lister.R(miStart, "DEC", reg);
17751 }
17752 /**
17753 * Generate a DEC to register-displacement offset. That is,
17754 * <PRE>
17755 * -- [base + disp]
17756 * </PRE>
17757 *
17758 * @param base the destination base register
17759 * @param disp the destination displacement
17760 */
17761 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17762 public final void emitDEC_RegDisp(GPR base, Offset disp) {
17763 int miStart = mi;
17764 // no group 1 to 4 prefix byte
17765 generateREXprefix(false, null, null, base);
17766 setMachineCodes(mi++, (byte) 0xFF);
17767 // "register 0x1" is really part of the opcode
17768 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
17769 if (lister != null) lister.RD(miStart, "DEC", base, disp);
17770 }
17771
17772 /**
17773 * Generate a DEC to register indirect. That is,
17774 * <PRE>
17775 * -- [reg]
17776 * </PRE>
17777 *
17778 * @param base the destination base register
17779 */
17780 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17781 public final void emitDEC_RegInd(GPR base) {
17782 int miStart = mi;
17783 // no group 1 to 4 prefix byte
17784 generateREXprefix(false, null, null, base);
17785 setMachineCodes(mi++, (byte) 0xFF);
17786 // "register 0x1" is really part of the opcode
17787 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
17788 if (lister != null) lister.RN(miStart, "DEC", base);
17789 }
17790
17791 /**
17792 * Generate a DEC to register offset. That is,
17793 * <PRE>
17794 * -- [index<<scale + disp]
17795 * </PRE>
17796 *
17797 * @param index the destination index register
17798 * @param scale the destination shift amount
17799 * @param disp the destination displacement
17800 */
17801 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17802 public final void emitDEC_RegOff(GPR index, short scale, Offset disp) {
17803 int miStart = mi;
17804 // no group 1 to 4 prefix byte
17805 generateREXprefix(false, null, index, null);
17806 setMachineCodes(mi++, (byte) 0xFF);
17807 // "register 0x1" is really part of the opcode
17808 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
17809 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
17810 }
17811
17812 /**
17813 * Generate a DEC to absolute address. That is,
17814 * <PRE>
17815 * -- [disp]
17816 * </PRE>
17817 *
17818 * @param disp the destination displacement
17819 */
17820 public final void emitDEC_Abs(Address disp) {
17821 int miStart = mi;
17822 // no group 1 to 4 prefix byte
17823 generateREXprefix(false, null, null, null);
17824 setMachineCodes(mi++, (byte) 0xFF);
17825 // "register 0x1" is really part of the opcode
17826 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
17827 if (lister != null) lister.RA(miStart, "DEC", disp);
17828 }
17829
17830 /**
17831 * Generate a DEC to register offset. That is,
17832 * <PRE>
17833 * -- [base + index<<scale + disp]
17834 * </PRE>
17835 *
17836 * @param base the destination base register
17837 * @param index the destination index register
17838 * @param scale the destination shift amount
17839 * @param disp the destination displacement
17840 */
17841 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17842 public final void emitDEC_RegIdx(GPR base, GPR index, short scale, Offset disp) {
17843 int miStart = mi;
17844 // no group 1 to 4 prefix byte
17845 generateREXprefix(false, null, index, base);
17846 setMachineCodes(mi++, (byte) 0xFF);
17847 // "register 0x1" is really part of the opcode
17848 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
17849 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
17850 }
17851
17852 /**
17853 * Generate a DEC on a register. That is,
17854 * <PRE>
17855 * -- (byte) reg
17856 * </PRE>
17857 *
17858 * @param reg register to operate upon
17859 */
17860 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17861 public final void emitDEC_Reg_Byte(GPR reg) {
17862 int miStart = mi;
17863 // no group 1 to 4 prefix byte
17864 generateREXprefix(false, null, null, reg);
17865 setMachineCodes(mi++, (byte) 0xFE);
17866 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
17867 if (lister != null) lister.R(miStart, "DEC", reg);
17868 }
17869 /**
17870 * Generate a DEC to register-displacement offset. That is,
17871 * <PRE>
17872 * -- (byte) [base + disp]
17873 * </PRE>
17874 *
17875 * @param base the destination base register
17876 * @param disp the destination displacement
17877 */
17878 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17879 public final void emitDEC_RegDisp_Byte(GPR base, Offset disp) {
17880 int miStart = mi;
17881 // no group 1 to 4 prefix byte
17882 generateREXprefix(false, null, null, base);
17883 setMachineCodes(mi++, (byte) 0xFE);
17884 // "register 0x1" is really part of the opcode
17885 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
17886 if (lister != null) lister.RD(miStart, "DEC", base, disp);
17887 }
17888
17889 /**
17890 * Generate a DEC to register indirect. That is,
17891 * <PRE>
17892 * -- (byte) [reg]
17893 * </PRE>
17894 *
17895 * @param base the destination base register
17896 */
17897 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17898 public final void emitDEC_RegInd_Byte(GPR base) {
17899 int miStart = mi;
17900 // no group 1 to 4 prefix byte
17901 generateREXprefix(false, null, null, base);
17902 setMachineCodes(mi++, (byte) 0xFE);
17903 // "register 0x1" is really part of the opcode
17904 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
17905 if (lister != null) lister.RN(miStart, "DEC", base);
17906 }
17907
17908 /**
17909 * Generate a DEC to register offset. That is,
17910 * <PRE>
17911 * -- (byte) [index<<scale + disp]
17912 * </PRE>
17913 *
17914 * @param index the destination index register
17915 * @param scale the destination shift amount
17916 * @param disp the destination displacement
17917 */
17918 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17919 public final void emitDEC_RegOff_Byte(GPR index, short scale, Offset disp) {
17920 int miStart = mi;
17921 // no group 1 to 4 prefix byte
17922 generateREXprefix(false, null, index, null);
17923 setMachineCodes(mi++, (byte) 0xFE);
17924 // "register 0x1" is really part of the opcode
17925 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
17926 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
17927 }
17928
17929 /**
17930 * Generate a DEC to absolute address. That is,
17931 * <PRE>
17932 * -- (byte) [disp]
17933 * </PRE>
17934 *
17935 * @param disp the destination displacement
17936 */
17937 public final void emitDEC_Abs_Byte(Address disp) {
17938 int miStart = mi;
17939 // no group 1 to 4 prefix byte
17940 generateREXprefix(false, null, null, null);
17941 setMachineCodes(mi++, (byte) 0xFE);
17942 // "register 0x1" is really part of the opcode
17943 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
17944 if (lister != null) lister.RA(miStart, "DEC", disp);
17945 }
17946
17947 /**
17948 * Generate a DEC to register offset. That is,
17949 * <PRE>
17950 * -- (byte) [base + index<<scale + disp]
17951 * </PRE>
17952 *
17953 * @param base the destination base register
17954 * @param index the destination index register
17955 * @param scale the destination shift amount
17956 * @param disp the destination displacement
17957 */
17958 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17959 public final void emitDEC_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
17960 int miStart = mi;
17961 // no group 1 to 4 prefix byte
17962 generateREXprefix(false, null, index, base);
17963 setMachineCodes(mi++, (byte) 0xFE);
17964 // "register 0x1" is really part of the opcode
17965 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
17966 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
17967 }
17968
17969 /**
17970 * Generate a DEC on a register. That is,
17971 * <PRE>
17972 * -- (word) reg
17973 * </PRE>
17974 *
17975 * @param reg register to operate upon
17976 */
17977 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17978 public void emitDEC_Reg_Word(GPR reg) {
17979 int miStart = mi;
17980 setMachineCodes(mi++, (byte) 0x66);
17981 generateREXprefix(false, null, null, reg);
17982 if (!VM.buildFor32Addr()) {
17983 setMachineCodes(mi++, (byte) (0xFF));
17984 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
17985 } else {
17986 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
17987 }
17988 if (lister != null) lister.R(miStart, "DEC", reg);
17989 }
17990 /**
17991 * Generate a DEC to register-displacement offset. That is,
17992 * <PRE>
17993 * -- (word) [base + disp]
17994 * </PRE>
17995 *
17996 * @param base the destination base register
17997 * @param disp the destination displacement
17998 */
17999 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18000 public final void emitDEC_RegDisp_Word(GPR base, Offset disp) {
18001 int miStart = mi;
18002 setMachineCodes(mi++, (byte) 0x66);
18003 generateREXprefix(false, null, null, base);
18004 setMachineCodes(mi++, (byte) 0xFF);
18005 // "register 0x1" is really part of the opcode
18006 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
18007 if (lister != null) lister.RD(miStart, "DEC", base, disp);
18008 }
18009
18010 /**
18011 * Generate a DEC to register indirect. That is,
18012 * <PRE>
18013 * -- (word) [reg]
18014 * </PRE>
18015 *
18016 * @param base the destination base register
18017 */
18018 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18019 public final void emitDEC_RegInd_Word(GPR base) {
18020 int miStart = mi;
18021 setMachineCodes(mi++, (byte) 0x66);
18022 generateREXprefix(false, null, null, base);
18023 setMachineCodes(mi++, (byte) 0xFF);
18024 // "register 0x1" is really part of the opcode
18025 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
18026 if (lister != null) lister.RN(miStart, "DEC", base);
18027 }
18028
18029 /**
18030 * Generate a DEC to register offset. That is,
18031 * <PRE>
18032 * -- (word) [index<<scale + disp]
18033 * </PRE>
18034 *
18035 * @param index the destination index register
18036 * @param scale the destination shift amount
18037 * @param disp the destination displacement
18038 */
18039 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18040 public final void emitDEC_RegOff_Word(GPR index, short scale, Offset disp) {
18041 int miStart = mi;
18042 setMachineCodes(mi++, (byte) 0x66);
18043 generateREXprefix(false, null, index, null);
18044 setMachineCodes(mi++, (byte) 0xFF);
18045 // "register 0x1" is really part of the opcode
18046 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
18047 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
18048 }
18049
18050 /**
18051 * Generate a DEC to absolute address. That is,
18052 * <PRE>
18053 * -- (word) [disp]
18054 * </PRE>
18055 *
18056 * @param disp the destination displacement
18057 */
18058 public final void emitDEC_Abs_Word(Address disp) {
18059 int miStart = mi;
18060 setMachineCodes(mi++, (byte) 0x66);
18061 generateREXprefix(false, null, null, null);
18062 setMachineCodes(mi++, (byte) 0xFF);
18063 // "register 0x1" is really part of the opcode
18064 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
18065 if (lister != null) lister.RA(miStart, "DEC", disp);
18066 }
18067
18068 /**
18069 * Generate a DEC to register offset. That is,
18070 * <PRE>
18071 * -- (word) [base + index<<scale + disp]
18072 * </PRE>
18073 *
18074 * @param base the destination base register
18075 * @param index the destination index register
18076 * @param scale the destination shift amount
18077 * @param disp the destination displacement
18078 */
18079 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18080 public final void emitDEC_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
18081 int miStart = mi;
18082 setMachineCodes(mi++, (byte) 0x66);
18083 generateREXprefix(false, null, index, base);
18084 setMachineCodes(mi++, (byte) 0xFF);
18085 // "register 0x1" is really part of the opcode
18086 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
18087 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
18088 }
18089
18090 /**
18091 * Generate a DEC on a register. That is,
18092 * <PRE>
18093 * -- (quad) reg
18094 * </PRE>
18095 *
18096 * @param reg register to operate upon
18097 */
18098 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18099 public void emitDEC_Reg_Quad(GPR reg) {
18100 int miStart = mi;
18101 // no group 1 to 4 prefix byte
18102 generateREXprefix(true, null, null, reg);
18103 if (!VM.buildFor32Addr()) {
18104 setMachineCodes(mi++, (byte) (0xFF));
18105 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
18106 } else {
18107 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
18108 }
18109 if (lister != null) lister.R(miStart, "DEC", reg);
18110 }
18111 /**
18112 * Generate a DEC to register-displacement offset. That is,
18113 * <PRE>
18114 * -- (quad) [base + disp]
18115 * </PRE>
18116 *
18117 * @param base the destination base register
18118 * @param disp the destination displacement
18119 */
18120 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18121 public final void emitDEC_RegDisp_Quad(GPR base, Offset disp) {
18122 int miStart = mi;
18123 // no group 1 to 4 prefix byte
18124 generateREXprefix(true, null, null, base);
18125 setMachineCodes(mi++, (byte) 0xFF);
18126 // "register 0x1" is really part of the opcode
18127 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
18128 if (lister != null) lister.RD(miStart, "DEC", base, disp);
18129 }
18130
18131 /**
18132 * Generate a DEC to register indirect. That is,
18133 * <PRE>
18134 * -- (quad) [reg]
18135 * </PRE>
18136 *
18137 * @param base the destination base register
18138 */
18139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18140 public final void emitDEC_RegInd_Quad(GPR base) {
18141 int miStart = mi;
18142 // no group 1 to 4 prefix byte
18143 generateREXprefix(true, null, null, base);
18144 setMachineCodes(mi++, (byte) 0xFF);
18145 // "register 0x1" is really part of the opcode
18146 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
18147 if (lister != null) lister.RN(miStart, "DEC", base);
18148 }
18149
18150 /**
18151 * Generate a DEC to register offset. That is,
18152 * <PRE>
18153 * -- (quad) [index<<scale + disp]
18154 * </PRE>
18155 *
18156 * @param index the destination index register
18157 * @param scale the destination shift amount
18158 * @param disp the destination displacement
18159 */
18160 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18161 public final void emitDEC_RegOff_Quad(GPR index, short scale, Offset disp) {
18162 int miStart = mi;
18163 // no group 1 to 4 prefix byte
18164 generateREXprefix(true, null, index, null);
18165 setMachineCodes(mi++, (byte) 0xFF);
18166 // "register 0x1" is really part of the opcode
18167 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
18168 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
18169 }
18170
18171 /**
18172 * Generate a DEC to absolute address. That is,
18173 * <PRE>
18174 * -- (quad) [disp]
18175 * </PRE>
18176 *
18177 * @param disp the destination displacement
18178 */
18179 public final void emitDEC_Abs_Quad(Address disp) {
18180 int miStart = mi;
18181 // no group 1 to 4 prefix byte
18182 generateREXprefix(true, null, null, null);
18183 setMachineCodes(mi++, (byte) 0xFF);
18184 // "register 0x1" is really part of the opcode
18185 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
18186 if (lister != null) lister.RA(miStart, "DEC", disp);
18187 }
18188
18189 /**
18190 * Generate a DEC to register offset. That is,
18191 * <PRE>
18192 * -- (quad) [base + index<<scale + disp]
18193 * </PRE>
18194 *
18195 * @param base the destination base register
18196 * @param index the destination index register
18197 * @param scale the destination shift amount
18198 * @param disp the destination displacement
18199 */
18200 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18201 public final void emitDEC_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
18202 int miStart = mi;
18203 // no group 1 to 4 prefix byte
18204 generateREXprefix(true, null, index, base);
18205 setMachineCodes(mi++, (byte) 0xFF);
18206 // "register 0x1" is really part of the opcode
18207 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
18208 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
18209 }
18210
18211 /**
18212 * Generate a INC on a register. That is,
18213 * <PRE>
18214 * ++ reg
18215 * </PRE>
18216 *
18217 * @param reg register to operate upon
18218 */
18219 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18220 public void emitINC_Reg(GPR reg) {
18221 int miStart = mi;
18222 // no group 1 to 4 prefix byte
18223 generateREXprefix(false, null, null, reg);
18224 if (!VM.buildFor32Addr()) {
18225 setMachineCodes(mi++, (byte) (0xFF));
18226 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18227 } else {
18228 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18229 }
18230 if (lister != null) lister.R(miStart, "INC", reg);
18231 }
18232 /**
18233 * Generate a INC to register-displacement offset. That is,
18234 * <PRE>
18235 * ++ [base + disp]
18236 * </PRE>
18237 *
18238 * @param base the destination base register
18239 * @param disp the destination displacement
18240 */
18241 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18242 public final void emitINC_RegDisp(GPR base, Offset disp) {
18243 int miStart = mi;
18244 // no group 1 to 4 prefix byte
18245 generateREXprefix(false, null, null, base);
18246 setMachineCodes(mi++, (byte) 0xFF);
18247 // "register 0x0" is really part of the opcode
18248 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18249 if (lister != null) lister.RD(miStart, "INC", base, disp);
18250 }
18251
18252 /**
18253 * Generate a INC to register indirect. That is,
18254 * <PRE>
18255 * ++ [reg]
18256 * </PRE>
18257 *
18258 * @param base the destination base register
18259 */
18260 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18261 public final void emitINC_RegInd(GPR base) {
18262 int miStart = mi;
18263 // no group 1 to 4 prefix byte
18264 generateREXprefix(false, null, null, base);
18265 setMachineCodes(mi++, (byte) 0xFF);
18266 // "register 0x0" is really part of the opcode
18267 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18268 if (lister != null) lister.RN(miStart, "INC", base);
18269 }
18270
18271 /**
18272 * Generate a INC to register offset. That is,
18273 * <PRE>
18274 * ++ [index<<scale + disp]
18275 * </PRE>
18276 *
18277 * @param index the destination index register
18278 * @param scale the destination shift amount
18279 * @param disp the destination displacement
18280 */
18281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18282 public final void emitINC_RegOff(GPR index, short scale, Offset disp) {
18283 int miStart = mi;
18284 // no group 1 to 4 prefix byte
18285 generateREXprefix(false, null, index, null);
18286 setMachineCodes(mi++, (byte) 0xFF);
18287 // "register 0x0" is really part of the opcode
18288 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18289 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18290 }
18291
18292 /**
18293 * Generate a INC to absolute address. That is,
18294 * <PRE>
18295 * ++ [disp]
18296 * </PRE>
18297 *
18298 * @param disp the destination displacement
18299 */
18300 public final void emitINC_Abs(Address disp) {
18301 int miStart = mi;
18302 // no group 1 to 4 prefix byte
18303 generateREXprefix(false, null, null, null);
18304 setMachineCodes(mi++, (byte) 0xFF);
18305 // "register 0x0" is really part of the opcode
18306 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18307 if (lister != null) lister.RA(miStart, "INC", disp);
18308 }
18309
18310 /**
18311 * Generate a INC to register offset. That is,
18312 * <PRE>
18313 * ++ [base + index<<scale + disp]
18314 * </PRE>
18315 *
18316 * @param base the destination base register
18317 * @param index the destination index register
18318 * @param scale the destination shift amount
18319 * @param disp the destination displacement
18320 */
18321 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18322 public final void emitINC_RegIdx(GPR base, GPR index, short scale, Offset disp) {
18323 int miStart = mi;
18324 // no group 1 to 4 prefix byte
18325 generateREXprefix(false, null, index, base);
18326 setMachineCodes(mi++, (byte) 0xFF);
18327 // "register 0x0" is really part of the opcode
18328 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18329 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18330 }
18331
18332 /**
18333 * Generate a INC on a register. That is,
18334 * <PRE>
18335 * ++ (byte) reg
18336 * </PRE>
18337 *
18338 * @param reg register to operate upon
18339 */
18340 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18341 public final void emitINC_Reg_Byte(GPR reg) {
18342 int miStart = mi;
18343 // no group 1 to 4 prefix byte
18344 generateREXprefix(false, null, null, reg);
18345 setMachineCodes(mi++, (byte) 0xFE);
18346 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18347 if (lister != null) lister.R(miStart, "INC", reg);
18348 }
18349 /**
18350 * Generate a INC to register-displacement offset. That is,
18351 * <PRE>
18352 * ++ (byte) [base + disp]
18353 * </PRE>
18354 *
18355 * @param base the destination base register
18356 * @param disp the destination displacement
18357 */
18358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18359 public final void emitINC_RegDisp_Byte(GPR base, Offset disp) {
18360 int miStart = mi;
18361 // no group 1 to 4 prefix byte
18362 generateREXprefix(false, null, null, base);
18363 setMachineCodes(mi++, (byte) 0xFE);
18364 // "register 0x0" is really part of the opcode
18365 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18366 if (lister != null) lister.RD(miStart, "INC", base, disp);
18367 }
18368
18369 /**
18370 * Generate a INC to register indirect. That is,
18371 * <PRE>
18372 * ++ (byte) [reg]
18373 * </PRE>
18374 *
18375 * @param base the destination base register
18376 */
18377 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18378 public final void emitINC_RegInd_Byte(GPR base) {
18379 int miStart = mi;
18380 // no group 1 to 4 prefix byte
18381 generateREXprefix(false, null, null, base);
18382 setMachineCodes(mi++, (byte) 0xFE);
18383 // "register 0x0" is really part of the opcode
18384 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18385 if (lister != null) lister.RN(miStart, "INC", base);
18386 }
18387
18388 /**
18389 * Generate a INC to register offset. That is,
18390 * <PRE>
18391 * ++ (byte) [index<<scale + disp]
18392 * </PRE>
18393 *
18394 * @param index the destination index register
18395 * @param scale the destination shift amount
18396 * @param disp the destination displacement
18397 */
18398 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18399 public final void emitINC_RegOff_Byte(GPR index, short scale, Offset disp) {
18400 int miStart = mi;
18401 // no group 1 to 4 prefix byte
18402 generateREXprefix(false, null, index, null);
18403 setMachineCodes(mi++, (byte) 0xFE);
18404 // "register 0x0" is really part of the opcode
18405 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18406 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18407 }
18408
18409 /**
18410 * Generate a INC to absolute address. That is,
18411 * <PRE>
18412 * ++ (byte) [disp]
18413 * </PRE>
18414 *
18415 * @param disp the destination displacement
18416 */
18417 public final void emitINC_Abs_Byte(Address disp) {
18418 int miStart = mi;
18419 // no group 1 to 4 prefix byte
18420 generateREXprefix(false, null, null, null);
18421 setMachineCodes(mi++, (byte) 0xFE);
18422 // "register 0x0" is really part of the opcode
18423 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18424 if (lister != null) lister.RA(miStart, "INC", disp);
18425 }
18426
18427 /**
18428 * Generate a INC to register offset. That is,
18429 * <PRE>
18430 * ++ (byte) [base + index<<scale + disp]
18431 * </PRE>
18432 *
18433 * @param base the destination base register
18434 * @param index the destination index register
18435 * @param scale the destination shift amount
18436 * @param disp the destination displacement
18437 */
18438 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18439 public final void emitINC_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
18440 int miStart = mi;
18441 // no group 1 to 4 prefix byte
18442 generateREXprefix(false, null, index, base);
18443 setMachineCodes(mi++, (byte) 0xFE);
18444 // "register 0x0" is really part of the opcode
18445 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18446 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18447 }
18448
18449 /**
18450 * Generate a INC on a register. That is,
18451 * <PRE>
18452 * ++ (word) reg
18453 * </PRE>
18454 *
18455 * @param reg register to operate upon
18456 */
18457 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18458 public void emitINC_Reg_Word(GPR reg) {
18459 int miStart = mi;
18460 setMachineCodes(mi++, (byte) 0x66);
18461 generateREXprefix(false, null, null, reg);
18462 if (!VM.buildFor32Addr()) {
18463 setMachineCodes(mi++, (byte) (0xFF));
18464 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18465 } else {
18466 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18467 }
18468 if (lister != null) lister.R(miStart, "INC", reg);
18469 }
18470 /**
18471 * Generate a INC to register-displacement offset. That is,
18472 * <PRE>
18473 * ++ (word) [base + disp]
18474 * </PRE>
18475 *
18476 * @param base the destination base register
18477 * @param disp the destination displacement
18478 */
18479 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18480 public final void emitINC_RegDisp_Word(GPR base, Offset disp) {
18481 int miStart = mi;
18482 setMachineCodes(mi++, (byte) 0x66);
18483 generateREXprefix(false, null, null, base);
18484 setMachineCodes(mi++, (byte) 0xFF);
18485 // "register 0x0" is really part of the opcode
18486 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18487 if (lister != null) lister.RD(miStart, "INC", base, disp);
18488 }
18489
18490 /**
18491 * Generate a INC to register indirect. That is,
18492 * <PRE>
18493 * ++ (word) [reg]
18494 * </PRE>
18495 *
18496 * @param base the destination base register
18497 */
18498 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18499 public final void emitINC_RegInd_Word(GPR base) {
18500 int miStart = mi;
18501 setMachineCodes(mi++, (byte) 0x66);
18502 generateREXprefix(false, null, null, base);
18503 setMachineCodes(mi++, (byte) 0xFF);
18504 // "register 0x0" is really part of the opcode
18505 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18506 if (lister != null) lister.RN(miStart, "INC", base);
18507 }
18508
18509 /**
18510 * Generate a INC to register offset. That is,
18511 * <PRE>
18512 * ++ (word) [index<<scale + disp]
18513 * </PRE>
18514 *
18515 * @param index the destination index register
18516 * @param scale the destination shift amount
18517 * @param disp the destination displacement
18518 */
18519 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18520 public final void emitINC_RegOff_Word(GPR index, short scale, Offset disp) {
18521 int miStart = mi;
18522 setMachineCodes(mi++, (byte) 0x66);
18523 generateREXprefix(false, null, index, null);
18524 setMachineCodes(mi++, (byte) 0xFF);
18525 // "register 0x0" is really part of the opcode
18526 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18527 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18528 }
18529
18530 /**
18531 * Generate a INC to absolute address. That is,
18532 * <PRE>
18533 * ++ (word) [disp]
18534 * </PRE>
18535 *
18536 * @param disp the destination displacement
18537 */
18538 public final void emitINC_Abs_Word(Address disp) {
18539 int miStart = mi;
18540 setMachineCodes(mi++, (byte) 0x66);
18541 generateREXprefix(false, null, null, null);
18542 setMachineCodes(mi++, (byte) 0xFF);
18543 // "register 0x0" is really part of the opcode
18544 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18545 if (lister != null) lister.RA(miStart, "INC", disp);
18546 }
18547
18548 /**
18549 * Generate a INC to register offset. That is,
18550 * <PRE>
18551 * ++ (word) [base + index<<scale + disp]
18552 * </PRE>
18553 *
18554 * @param base the destination base register
18555 * @param index the destination index register
18556 * @param scale the destination shift amount
18557 * @param disp the destination displacement
18558 */
18559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18560 public final void emitINC_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
18561 int miStart = mi;
18562 setMachineCodes(mi++, (byte) 0x66);
18563 generateREXprefix(false, null, index, base);
18564 setMachineCodes(mi++, (byte) 0xFF);
18565 // "register 0x0" is really part of the opcode
18566 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18567 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18568 }
18569
18570 /**
18571 * Generate a INC on a register. That is,
18572 * <PRE>
18573 * ++ (quad) reg
18574 * </PRE>
18575 *
18576 * @param reg register to operate upon
18577 */
18578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18579 public void emitINC_Reg_Quad(GPR reg) {
18580 int miStart = mi;
18581 // no group 1 to 4 prefix byte
18582 generateREXprefix(true, null, null, reg);
18583 if (!VM.buildFor32Addr()) {
18584 setMachineCodes(mi++, (byte) (0xFF));
18585 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18586 } else {
18587 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18588 }
18589 if (lister != null) lister.R(miStart, "INC", reg);
18590 }
18591 /**
18592 * Generate a INC to register-displacement offset. That is,
18593 * <PRE>
18594 * ++ (quad) [base + disp]
18595 * </PRE>
18596 *
18597 * @param base the destination base register
18598 * @param disp the destination displacement
18599 */
18600 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18601 public final void emitINC_RegDisp_Quad(GPR base, Offset disp) {
18602 int miStart = mi;
18603 // no group 1 to 4 prefix byte
18604 generateREXprefix(true, null, null, base);
18605 setMachineCodes(mi++, (byte) 0xFF);
18606 // "register 0x0" is really part of the opcode
18607 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18608 if (lister != null) lister.RD(miStart, "INC", base, disp);
18609 }
18610
18611 /**
18612 * Generate a INC to register indirect. That is,
18613 * <PRE>
18614 * ++ (quad) [reg]
18615 * </PRE>
18616 *
18617 * @param base the destination base register
18618 */
18619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18620 public final void emitINC_RegInd_Quad(GPR base) {
18621 int miStart = mi;
18622 // no group 1 to 4 prefix byte
18623 generateREXprefix(true, null, null, base);
18624 setMachineCodes(mi++, (byte) 0xFF);
18625 // "register 0x0" is really part of the opcode
18626 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18627 if (lister != null) lister.RN(miStart, "INC", base);
18628 }
18629
18630 /**
18631 * Generate a INC to register offset. That is,
18632 * <PRE>
18633 * ++ (quad) [index<<scale + disp]
18634 * </PRE>
18635 *
18636 * @param index the destination index register
18637 * @param scale the destination shift amount
18638 * @param disp the destination displacement
18639 */
18640 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18641 public final void emitINC_RegOff_Quad(GPR index, short scale, Offset disp) {
18642 int miStart = mi;
18643 // no group 1 to 4 prefix byte
18644 generateREXprefix(true, null, index, null);
18645 setMachineCodes(mi++, (byte) 0xFF);
18646 // "register 0x0" is really part of the opcode
18647 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18648 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18649 }
18650
18651 /**
18652 * Generate a INC to absolute address. That is,
18653 * <PRE>
18654 * ++ (quad) [disp]
18655 * </PRE>
18656 *
18657 * @param disp the destination displacement
18658 */
18659 public final void emitINC_Abs_Quad(Address disp) {
18660 int miStart = mi;
18661 // no group 1 to 4 prefix byte
18662 generateREXprefix(true, null, null, null);
18663 setMachineCodes(mi++, (byte) 0xFF);
18664 // "register 0x0" is really part of the opcode
18665 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18666 if (lister != null) lister.RA(miStart, "INC", disp);
18667 }
18668
18669 /**
18670 * Generate a INC to register offset. That is,
18671 * <PRE>
18672 * ++ (quad) [base + index<<scale + disp]
18673 * </PRE>
18674 *
18675 * @param base the destination base register
18676 * @param index the destination index register
18677 * @param scale the destination shift amount
18678 * @param disp the destination displacement
18679 */
18680 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18681 public final void emitINC_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
18682 int miStart = mi;
18683 // no group 1 to 4 prefix byte
18684 generateREXprefix(true, null, index, base);
18685 setMachineCodes(mi++, (byte) 0xFF);
18686 // "register 0x0" is really part of the opcode
18687 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18688 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18689 }
18690
18691 /**
18692 * Generate a NEG on a register. That is,
18693 * <PRE>
18694 * - reg
18695 * </PRE>
18696 *
18697 * @param reg register to operate upon
18698 */
18699 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18700 public final void emitNEG_Reg(GPR reg) {
18701 int miStart = mi;
18702 // no group 1 to 4 prefix byte
18703 generateREXprefix(false, null, null, reg);
18704 setMachineCodes(mi++, (byte) 0xF7);
18705 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18706 if (lister != null) lister.R(miStart, "NEG", reg);
18707 }
18708 /**
18709 * Generate a NEG to register-displacement offset. That is,
18710 * <PRE>
18711 * - [base + disp]
18712 * </PRE>
18713 *
18714 * @param base the destination base register
18715 * @param disp the destination displacement
18716 */
18717 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18718 public final void emitNEG_RegDisp(GPR base, Offset disp) {
18719 int miStart = mi;
18720 // no group 1 to 4 prefix byte
18721 generateREXprefix(false, null, null, base);
18722 setMachineCodes(mi++, (byte) 0xF7);
18723 // "register 0x3" is really part of the opcode
18724 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18725 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18726 }
18727
18728 /**
18729 * Generate a NEG to register indirect. That is,
18730 * <PRE>
18731 * - [reg]
18732 * </PRE>
18733 *
18734 * @param base the destination base register
18735 */
18736 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18737 public final void emitNEG_RegInd(GPR base) {
18738 int miStart = mi;
18739 // no group 1 to 4 prefix byte
18740 generateREXprefix(false, null, null, base);
18741 setMachineCodes(mi++, (byte) 0xF7);
18742 // "register 0x3" is really part of the opcode
18743 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18744 if (lister != null) lister.RN(miStart, "NEG", base);
18745 }
18746
18747 /**
18748 * Generate a NEG to register offset. That is,
18749 * <PRE>
18750 * - [index<<scale + disp]
18751 * </PRE>
18752 *
18753 * @param index the destination index register
18754 * @param scale the destination shift amount
18755 * @param disp the destination displacement
18756 */
18757 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18758 public final void emitNEG_RegOff(GPR index, short scale, Offset disp) {
18759 int miStart = mi;
18760 // no group 1 to 4 prefix byte
18761 generateREXprefix(false, null, index, null);
18762 setMachineCodes(mi++, (byte) 0xF7);
18763 // "register 0x3" is really part of the opcode
18764 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
18765 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
18766 }
18767
18768 /**
18769 * Generate a NEG to absolute address. That is,
18770 * <PRE>
18771 * - [disp]
18772 * </PRE>
18773 *
18774 * @param disp the destination displacement
18775 */
18776 public final void emitNEG_Abs(Address disp) {
18777 int miStart = mi;
18778 // no group 1 to 4 prefix byte
18779 generateREXprefix(false, null, null, null);
18780 setMachineCodes(mi++, (byte) 0xF7);
18781 // "register 0x3" is really part of the opcode
18782 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
18783 if (lister != null) lister.RA(miStart, "NEG", disp);
18784 }
18785
18786 /**
18787 * Generate a NEG to register offset. That is,
18788 * <PRE>
18789 * - [base + index<<scale + disp]
18790 * </PRE>
18791 *
18792 * @param base the destination base register
18793 * @param index the destination index register
18794 * @param scale the destination shift amount
18795 * @param disp the destination displacement
18796 */
18797 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18798 public final void emitNEG_RegIdx(GPR base, GPR index, short scale, Offset disp) {
18799 int miStart = mi;
18800 // no group 1 to 4 prefix byte
18801 generateREXprefix(false, null, index, base);
18802 setMachineCodes(mi++, (byte) 0xF7);
18803 // "register 0x3" is really part of the opcode
18804 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
18805 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
18806 }
18807
18808 /**
18809 * Generate a NEG on a register. That is,
18810 * <PRE>
18811 * - (byte) reg
18812 * </PRE>
18813 *
18814 * @param reg register to operate upon
18815 */
18816 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18817 public final void emitNEG_Reg_Byte(GPR reg) {
18818 int miStart = mi;
18819 // no group 1 to 4 prefix byte
18820 generateREXprefix(false, null, null, reg);
18821 setMachineCodes(mi++, (byte) 0xF6);
18822 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18823 if (lister != null) lister.R(miStart, "NEG", reg);
18824 }
18825 /**
18826 * Generate a NEG to register-displacement offset. That is,
18827 * <PRE>
18828 * - (byte) [base + disp]
18829 * </PRE>
18830 *
18831 * @param base the destination base register
18832 * @param disp the destination displacement
18833 */
18834 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18835 public final void emitNEG_RegDisp_Byte(GPR base, Offset disp) {
18836 int miStart = mi;
18837 // no group 1 to 4 prefix byte
18838 generateREXprefix(false, null, null, base);
18839 setMachineCodes(mi++, (byte) 0xF6);
18840 // "register 0x3" is really part of the opcode
18841 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18842 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18843 }
18844
18845 /**
18846 * Generate a NEG to register indirect. That is,
18847 * <PRE>
18848 * - (byte) [reg]
18849 * </PRE>
18850 *
18851 * @param base the destination base register
18852 */
18853 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18854 public final void emitNEG_RegInd_Byte(GPR base) {
18855 int miStart = mi;
18856 // no group 1 to 4 prefix byte
18857 generateREXprefix(false, null, null, base);
18858 setMachineCodes(mi++, (byte) 0xF6);
18859 // "register 0x3" is really part of the opcode
18860 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18861 if (lister != null) lister.RN(miStart, "NEG", base);
18862 }
18863
18864 /**
18865 * Generate a NEG to register offset. That is,
18866 * <PRE>
18867 * - (byte) [index<<scale + disp]
18868 * </PRE>
18869 *
18870 * @param index the destination index register
18871 * @param scale the destination shift amount
18872 * @param disp the destination displacement
18873 */
18874 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18875 public final void emitNEG_RegOff_Byte(GPR index, short scale, Offset disp) {
18876 int miStart = mi;
18877 // no group 1 to 4 prefix byte
18878 generateREXprefix(false, null, index, null);
18879 setMachineCodes(mi++, (byte) 0xF6);
18880 // "register 0x3" is really part of the opcode
18881 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
18882 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
18883 }
18884
18885 /**
18886 * Generate a NEG to absolute address. That is,
18887 * <PRE>
18888 * - (byte) [disp]
18889 * </PRE>
18890 *
18891 * @param disp the destination displacement
18892 */
18893 public final void emitNEG_Abs_Byte(Address disp) {
18894 int miStart = mi;
18895 // no group 1 to 4 prefix byte
18896 generateREXprefix(false, null, null, null);
18897 setMachineCodes(mi++, (byte) 0xF6);
18898 // "register 0x3" is really part of the opcode
18899 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
18900 if (lister != null) lister.RA(miStart, "NEG", disp);
18901 }
18902
18903 /**
18904 * Generate a NEG to register offset. That is,
18905 * <PRE>
18906 * - (byte) [base + index<<scale + disp]
18907 * </PRE>
18908 *
18909 * @param base the destination base register
18910 * @param index the destination index register
18911 * @param scale the destination shift amount
18912 * @param disp the destination displacement
18913 */
18914 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18915 public final void emitNEG_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
18916 int miStart = mi;
18917 // no group 1 to 4 prefix byte
18918 generateREXprefix(false, null, index, base);
18919 setMachineCodes(mi++, (byte) 0xF6);
18920 // "register 0x3" is really part of the opcode
18921 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
18922 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
18923 }
18924
18925 /**
18926 * Generate a NEG on a register. That is,
18927 * <PRE>
18928 * - (word) reg
18929 * </PRE>
18930 *
18931 * @param reg register to operate upon
18932 */
18933 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18934 public final void emitNEG_Reg_Word(GPR reg) {
18935 int miStart = mi;
18936 setMachineCodes(mi++, (byte) 0x66);
18937 generateREXprefix(false, null, null, reg);
18938 setMachineCodes(mi++, (byte) 0xF7);
18939 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18940 if (lister != null) lister.R(miStart, "NEG", reg);
18941 }
18942 /**
18943 * Generate a NEG to register-displacement offset. That is,
18944 * <PRE>
18945 * - (word) [base + disp]
18946 * </PRE>
18947 *
18948 * @param base the destination base register
18949 * @param disp the destination displacement
18950 */
18951 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18952 public final void emitNEG_RegDisp_Word(GPR base, Offset disp) {
18953 int miStart = mi;
18954 setMachineCodes(mi++, (byte) 0x66);
18955 generateREXprefix(false, null, null, base);
18956 setMachineCodes(mi++, (byte) 0xF7);
18957 // "register 0x3" is really part of the opcode
18958 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18959 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18960 }
18961
18962 /**
18963 * Generate a NEG to register indirect. That is,
18964 * <PRE>
18965 * - (word) [reg]
18966 * </PRE>
18967 *
18968 * @param base the destination base register
18969 */
18970 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18971 public final void emitNEG_RegInd_Word(GPR base) {
18972 int miStart = mi;
18973 setMachineCodes(mi++, (byte) 0x66);
18974 generateREXprefix(false, null, null, base);
18975 setMachineCodes(mi++, (byte) 0xF7);
18976 // "register 0x3" is really part of the opcode
18977 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18978 if (lister != null) lister.RN(miStart, "NEG", base);
18979 }
18980
18981 /**
18982 * Generate a NEG to register offset. That is,
18983 * <PRE>
18984 * - (word) [index<<scale + disp]
18985 * </PRE>
18986 *
18987 * @param index the destination index register
18988 * @param scale the destination shift amount
18989 * @param disp the destination displacement
18990 */
18991 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18992 public final void emitNEG_RegOff_Word(GPR index, short scale, Offset disp) {
18993 int miStart = mi;
18994 setMachineCodes(mi++, (byte) 0x66);
18995 generateREXprefix(false, null, index, null);
18996 setMachineCodes(mi++, (byte) 0xF7);
18997 // "register 0x3" is really part of the opcode
18998 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
18999 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
19000 }
19001
19002 /**
19003 * Generate a NEG to absolute address. That is,
19004 * <PRE>
19005 * - (word) [disp]
19006 * </PRE>
19007 *
19008 * @param disp the destination displacement
19009 */
19010 public final void emitNEG_Abs_Word(Address disp) {
19011 int miStart = mi;
19012 setMachineCodes(mi++, (byte) 0x66);
19013 generateREXprefix(false, null, null, null);
19014 setMachineCodes(mi++, (byte) 0xF7);
19015 // "register 0x3" is really part of the opcode
19016 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
19017 if (lister != null) lister.RA(miStart, "NEG", disp);
19018 }
19019
19020 /**
19021 * Generate a NEG to register offset. That is,
19022 * <PRE>
19023 * - (word) [base + index<<scale + disp]
19024 * </PRE>
19025 *
19026 * @param base the destination base register
19027 * @param index the destination index register
19028 * @param scale the destination shift amount
19029 * @param disp the destination displacement
19030 */
19031 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19032 public final void emitNEG_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
19033 int miStart = mi;
19034 setMachineCodes(mi++, (byte) 0x66);
19035 generateREXprefix(false, null, index, base);
19036 setMachineCodes(mi++, (byte) 0xF7);
19037 // "register 0x3" is really part of the opcode
19038 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
19039 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
19040 }
19041
19042 /**
19043 * Generate a NEG on a register. That is,
19044 * <PRE>
19045 * - (quad) reg
19046 * </PRE>
19047 *
19048 * @param reg register to operate upon
19049 */
19050 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19051 public final void emitNEG_Reg_Quad(GPR reg) {
19052 int miStart = mi;
19053 // no group 1 to 4 prefix byte
19054 generateREXprefix(true, null, null, reg);
19055 setMachineCodes(mi++, (byte) 0xF7);
19056 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
19057 if (lister != null) lister.R(miStart, "NEG", reg);
19058 }
19059 /**
19060 * Generate a NEG to register-displacement offset. That is,
19061 * <PRE>
19062 * - (quad) [base + disp]
19063 * </PRE>
19064 *
19065 * @param base the destination base register
19066 * @param disp the destination displacement
19067 */
19068 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19069 public final void emitNEG_RegDisp_Quad(GPR base, Offset disp) {
19070 int miStart = mi;
19071 // no group 1 to 4 prefix byte
19072 generateREXprefix(true, null, null, base);
19073 setMachineCodes(mi++, (byte) 0xF7);
19074 // "register 0x3" is really part of the opcode
19075 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
19076 if (lister != null) lister.RD(miStart, "NEG", base, disp);
19077 }
19078
19079 /**
19080 * Generate a NEG to register indirect. That is,
19081 * <PRE>
19082 * - (quad) [reg]
19083 * </PRE>
19084 *
19085 * @param base the destination base register
19086 */
19087 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19088 public final void emitNEG_RegInd_Quad(GPR base) {
19089 int miStart = mi;
19090 // no group 1 to 4 prefix byte
19091 generateREXprefix(true, null, null, base);
19092 setMachineCodes(mi++, (byte) 0xF7);
19093 // "register 0x3" is really part of the opcode
19094 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
19095 if (lister != null) lister.RN(miStart, "NEG", base);
19096 }
19097
19098 /**
19099 * Generate a NEG to register offset. That is,
19100 * <PRE>
19101 * - (quad) [index<<scale + disp]
19102 * </PRE>
19103 *
19104 * @param index the destination index register
19105 * @param scale the destination shift amount
19106 * @param disp the destination displacement
19107 */
19108 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19109 public final void emitNEG_RegOff_Quad(GPR index, short scale, Offset disp) {
19110 int miStart = mi;
19111 // no group 1 to 4 prefix byte
19112 generateREXprefix(true, null, index, null);
19113 setMachineCodes(mi++, (byte) 0xF7);
19114 // "register 0x3" is really part of the opcode
19115 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
19116 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
19117 }
19118
19119 /**
19120 * Generate a NEG to absolute address. That is,
19121 * <PRE>
19122 * - (quad) [disp]
19123 * </PRE>
19124 *
19125 * @param disp the destination displacement
19126 */
19127 public final void emitNEG_Abs_Quad(Address disp) {
19128 int miStart = mi;
19129 // no group 1 to 4 prefix byte
19130 generateREXprefix(true, null, null, null);
19131 setMachineCodes(mi++, (byte) 0xF7);
19132 // "register 0x3" is really part of the opcode
19133 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
19134 if (lister != null) lister.RA(miStart, "NEG", disp);
19135 }
19136
19137 /**
19138 * Generate a NEG to register offset. That is,
19139 * <PRE>
19140 * - (quad) [base + index<<scale + disp]
19141 * </PRE>
19142 *
19143 * @param base the destination base register
19144 * @param index the destination index register
19145 * @param scale the destination shift amount
19146 * @param disp the destination displacement
19147 */
19148 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19149 public final void emitNEG_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
19150 int miStart = mi;
19151 // no group 1 to 4 prefix byte
19152 generateREXprefix(true, null, index, base);
19153 setMachineCodes(mi++, (byte) 0xF7);
19154 // "register 0x3" is really part of the opcode
19155 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
19156 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
19157 }
19158
19159 /**
19160 * Generate a NOT on a register. That is,
19161 * <PRE>
19162 * ~ reg
19163 * </PRE>
19164 *
19165 * @param reg register to operate upon
19166 */
19167 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19168 public final void emitNOT_Reg(GPR reg) {
19169 int miStart = mi;
19170 // no group 1 to 4 prefix byte
19171 generateREXprefix(false, null, null, reg);
19172 setMachineCodes(mi++, (byte) 0xF7);
19173 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19174 if (lister != null) lister.R(miStart, "NOT", reg);
19175 }
19176 /**
19177 * Generate a NOT to register-displacement offset. That is,
19178 * <PRE>
19179 * ~ [base + disp]
19180 * </PRE>
19181 *
19182 * @param base the destination base register
19183 * @param disp the destination displacement
19184 */
19185 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19186 public final void emitNOT_RegDisp(GPR base, Offset disp) {
19187 int miStart = mi;
19188 // no group 1 to 4 prefix byte
19189 generateREXprefix(false, null, null, base);
19190 setMachineCodes(mi++, (byte) 0xF7);
19191 // "register 0x2" is really part of the opcode
19192 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19193 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19194 }
19195
19196 /**
19197 * Generate a NOT to register indirect. That is,
19198 * <PRE>
19199 * ~ [reg]
19200 * </PRE>
19201 *
19202 * @param base the destination base register
19203 */
19204 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19205 public final void emitNOT_RegInd(GPR base) {
19206 int miStart = mi;
19207 // no group 1 to 4 prefix byte
19208 generateREXprefix(false, null, null, base);
19209 setMachineCodes(mi++, (byte) 0xF7);
19210 // "register 0x2" is really part of the opcode
19211 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19212 if (lister != null) lister.RN(miStart, "NOT", base);
19213 }
19214
19215 /**
19216 * Generate a NOT to register offset. That is,
19217 * <PRE>
19218 * ~ [index<<scale + disp]
19219 * </PRE>
19220 *
19221 * @param index the destination index register
19222 * @param scale the destination shift amount
19223 * @param disp the destination displacement
19224 */
19225 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19226 public final void emitNOT_RegOff(GPR index, short scale, Offset disp) {
19227 int miStart = mi;
19228 // no group 1 to 4 prefix byte
19229 generateREXprefix(false, null, index, null);
19230 setMachineCodes(mi++, (byte) 0xF7);
19231 // "register 0x2" is really part of the opcode
19232 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19233 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19234 }
19235
19236 /**
19237 * Generate a NOT to absolute address. That is,
19238 * <PRE>
19239 * ~ [disp]
19240 * </PRE>
19241 *
19242 * @param disp the destination displacement
19243 */
19244 public final void emitNOT_Abs(Address disp) {
19245 int miStart = mi;
19246 // no group 1 to 4 prefix byte
19247 generateREXprefix(false, null, null, null);
19248 setMachineCodes(mi++, (byte) 0xF7);
19249 // "register 0x2" is really part of the opcode
19250 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19251 if (lister != null) lister.RA(miStart, "NOT", disp);
19252 }
19253
19254 /**
19255 * Generate a NOT to register offset. That is,
19256 * <PRE>
19257 * ~ [base + index<<scale + disp]
19258 * </PRE>
19259 *
19260 * @param base the destination base register
19261 * @param index the destination index register
19262 * @param scale the destination shift amount
19263 * @param disp the destination displacement
19264 */
19265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19266 public final void emitNOT_RegIdx(GPR base, GPR index, short scale, Offset disp) {
19267 int miStart = mi;
19268 // no group 1 to 4 prefix byte
19269 generateREXprefix(false, null, index, base);
19270 setMachineCodes(mi++, (byte) 0xF7);
19271 // "register 0x2" is really part of the opcode
19272 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19273 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19274 }
19275
19276 /**
19277 * Generate a NOT on a register. That is,
19278 * <PRE>
19279 * ~ (byte) reg
19280 * </PRE>
19281 *
19282 * @param reg register to operate upon
19283 */
19284 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19285 public final void emitNOT_Reg_Byte(GPR reg) {
19286 int miStart = mi;
19287 // no group 1 to 4 prefix byte
19288 generateREXprefix(false, null, null, reg);
19289 setMachineCodes(mi++, (byte) 0xF6);
19290 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19291 if (lister != null) lister.R(miStart, "NOT", reg);
19292 }
19293 /**
19294 * Generate a NOT to register-displacement offset. That is,
19295 * <PRE>
19296 * ~ (byte) [base + disp]
19297 * </PRE>
19298 *
19299 * @param base the destination base register
19300 * @param disp the destination displacement
19301 */
19302 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19303 public final void emitNOT_RegDisp_Byte(GPR base, Offset disp) {
19304 int miStart = mi;
19305 // no group 1 to 4 prefix byte
19306 generateREXprefix(false, null, null, base);
19307 setMachineCodes(mi++, (byte) 0xF6);
19308 // "register 0x2" is really part of the opcode
19309 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19310 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19311 }
19312
19313 /**
19314 * Generate a NOT to register indirect. That is,
19315 * <PRE>
19316 * ~ (byte) [reg]
19317 * </PRE>
19318 *
19319 * @param base the destination base register
19320 */
19321 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19322 public final void emitNOT_RegInd_Byte(GPR base) {
19323 int miStart = mi;
19324 // no group 1 to 4 prefix byte
19325 generateREXprefix(false, null, null, base);
19326 setMachineCodes(mi++, (byte) 0xF6);
19327 // "register 0x2" is really part of the opcode
19328 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19329 if (lister != null) lister.RN(miStart, "NOT", base);
19330 }
19331
19332 /**
19333 * Generate a NOT to register offset. That is,
19334 * <PRE>
19335 * ~ (byte) [index<<scale + disp]
19336 * </PRE>
19337 *
19338 * @param index the destination index register
19339 * @param scale the destination shift amount
19340 * @param disp the destination displacement
19341 */
19342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19343 public final void emitNOT_RegOff_Byte(GPR index, short scale, Offset disp) {
19344 int miStart = mi;
19345 // no group 1 to 4 prefix byte
19346 generateREXprefix(false, null, index, null);
19347 setMachineCodes(mi++, (byte) 0xF6);
19348 // "register 0x2" is really part of the opcode
19349 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19350 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19351 }
19352
19353 /**
19354 * Generate a NOT to absolute address. That is,
19355 * <PRE>
19356 * ~ (byte) [disp]
19357 * </PRE>
19358 *
19359 * @param disp the destination displacement
19360 */
19361 public final void emitNOT_Abs_Byte(Address disp) {
19362 int miStart = mi;
19363 // no group 1 to 4 prefix byte
19364 generateREXprefix(false, null, null, null);
19365 setMachineCodes(mi++, (byte) 0xF6);
19366 // "register 0x2" is really part of the opcode
19367 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19368 if (lister != null) lister.RA(miStart, "NOT", disp);
19369 }
19370
19371 /**
19372 * Generate a NOT to register offset. That is,
19373 * <PRE>
19374 * ~ (byte) [base + index<<scale + disp]
19375 * </PRE>
19376 *
19377 * @param base the destination base register
19378 * @param index the destination index register
19379 * @param scale the destination shift amount
19380 * @param disp the destination displacement
19381 */
19382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19383 public final void emitNOT_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
19384 int miStart = mi;
19385 // no group 1 to 4 prefix byte
19386 generateREXprefix(false, null, index, base);
19387 setMachineCodes(mi++, (byte) 0xF6);
19388 // "register 0x2" is really part of the opcode
19389 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19390 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19391 }
19392
19393 /**
19394 * Generate a NOT on a register. That is,
19395 * <PRE>
19396 * ~ (word) reg
19397 * </PRE>
19398 *
19399 * @param reg register to operate upon
19400 */
19401 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19402 public final void emitNOT_Reg_Word(GPR reg) {
19403 int miStart = mi;
19404 setMachineCodes(mi++, (byte) 0x66);
19405 generateREXprefix(false, null, null, reg);
19406 setMachineCodes(mi++, (byte) 0xF7);
19407 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19408 if (lister != null) lister.R(miStart, "NOT", reg);
19409 }
19410 /**
19411 * Generate a NOT to register-displacement offset. That is,
19412 * <PRE>
19413 * ~ (word) [base + disp]
19414 * </PRE>
19415 *
19416 * @param base the destination base register
19417 * @param disp the destination displacement
19418 */
19419 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19420 public final void emitNOT_RegDisp_Word(GPR base, Offset disp) {
19421 int miStart = mi;
19422 setMachineCodes(mi++, (byte) 0x66);
19423 generateREXprefix(false, null, null, base);
19424 setMachineCodes(mi++, (byte) 0xF7);
19425 // "register 0x2" is really part of the opcode
19426 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19427 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19428 }
19429
19430 /**
19431 * Generate a NOT to register indirect. That is,
19432 * <PRE>
19433 * ~ (word) [reg]
19434 * </PRE>
19435 *
19436 * @param base the destination base register
19437 */
19438 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19439 public final void emitNOT_RegInd_Word(GPR base) {
19440 int miStart = mi;
19441 setMachineCodes(mi++, (byte) 0x66);
19442 generateREXprefix(false, null, null, base);
19443 setMachineCodes(mi++, (byte) 0xF7);
19444 // "register 0x2" is really part of the opcode
19445 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19446 if (lister != null) lister.RN(miStart, "NOT", base);
19447 }
19448
19449 /**
19450 * Generate a NOT to register offset. That is,
19451 * <PRE>
19452 * ~ (word) [index<<scale + disp]
19453 * </PRE>
19454 *
19455 * @param index the destination index register
19456 * @param scale the destination shift amount
19457 * @param disp the destination displacement
19458 */
19459 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19460 public final void emitNOT_RegOff_Word(GPR index, short scale, Offset disp) {
19461 int miStart = mi;
19462 setMachineCodes(mi++, (byte) 0x66);
19463 generateREXprefix(false, null, index, null);
19464 setMachineCodes(mi++, (byte) 0xF7);
19465 // "register 0x2" is really part of the opcode
19466 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19467 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19468 }
19469
19470 /**
19471 * Generate a NOT to absolute address. That is,
19472 * <PRE>
19473 * ~ (word) [disp]
19474 * </PRE>
19475 *
19476 * @param disp the destination displacement
19477 */
19478 public final void emitNOT_Abs_Word(Address disp) {
19479 int miStart = mi;
19480 setMachineCodes(mi++, (byte) 0x66);
19481 generateREXprefix(false, null, null, null);
19482 setMachineCodes(mi++, (byte) 0xF7);
19483 // "register 0x2" is really part of the opcode
19484 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19485 if (lister != null) lister.RA(miStart, "NOT", disp);
19486 }
19487
19488 /**
19489 * Generate a NOT to register offset. That is,
19490 * <PRE>
19491 * ~ (word) [base + index<<scale + disp]
19492 * </PRE>
19493 *
19494 * @param base the destination base register
19495 * @param index the destination index register
19496 * @param scale the destination shift amount
19497 * @param disp the destination displacement
19498 */
19499 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19500 public final void emitNOT_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
19501 int miStart = mi;
19502 setMachineCodes(mi++, (byte) 0x66);
19503 generateREXprefix(false, null, index, base);
19504 setMachineCodes(mi++, (byte) 0xF7);
19505 // "register 0x2" is really part of the opcode
19506 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19507 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19508 }
19509
19510 /**
19511 * Generate a NOT on a register. That is,
19512 * <PRE>
19513 * ~ (quad) reg
19514 * </PRE>
19515 *
19516 * @param reg register to operate upon
19517 */
19518 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19519 public final void emitNOT_Reg_Quad(GPR reg) {
19520 int miStart = mi;
19521 // no group 1 to 4 prefix byte
19522 generateREXprefix(true, null, null, reg);
19523 setMachineCodes(mi++, (byte) 0xF7);
19524 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19525 if (lister != null) lister.R(miStart, "NOT", reg);
19526 }
19527 /**
19528 * Generate a NOT to register-displacement offset. That is,
19529 * <PRE>
19530 * ~ (quad) [base + disp]
19531 * </PRE>
19532 *
19533 * @param base the destination base register
19534 * @param disp the destination displacement
19535 */
19536 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19537 public final void emitNOT_RegDisp_Quad(GPR base, Offset disp) {
19538 int miStart = mi;
19539 // no group 1 to 4 prefix byte
19540 generateREXprefix(true, null, null, base);
19541 setMachineCodes(mi++, (byte) 0xF7);
19542 // "register 0x2" is really part of the opcode
19543 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19544 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19545 }
19546
19547 /**
19548 * Generate a NOT to register indirect. That is,
19549 * <PRE>
19550 * ~ (quad) [reg]
19551 * </PRE>
19552 *
19553 * @param base the destination base register
19554 */
19555 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19556 public final void emitNOT_RegInd_Quad(GPR base) {
19557 int miStart = mi;
19558 // no group 1 to 4 prefix byte
19559 generateREXprefix(true, null, null, base);
19560 setMachineCodes(mi++, (byte) 0xF7);
19561 // "register 0x2" is really part of the opcode
19562 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19563 if (lister != null) lister.RN(miStart, "NOT", base);
19564 }
19565
19566 /**
19567 * Generate a NOT to register offset. That is,
19568 * <PRE>
19569 * ~ (quad) [index<<scale + disp]
19570 * </PRE>
19571 *
19572 * @param index the destination index register
19573 * @param scale the destination shift amount
19574 * @param disp the destination displacement
19575 */
19576 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19577 public final void emitNOT_RegOff_Quad(GPR index, short scale, Offset disp) {
19578 int miStart = mi;
19579 // no group 1 to 4 prefix byte
19580 generateREXprefix(true, null, index, null);
19581 setMachineCodes(mi++, (byte) 0xF7);
19582 // "register 0x2" is really part of the opcode
19583 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19584 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19585 }
19586
19587 /**
19588 * Generate a NOT to absolute address. That is,
19589 * <PRE>
19590 * ~ (quad) [disp]
19591 * </PRE>
19592 *
19593 * @param disp the destination displacement
19594 */
19595 public final void emitNOT_Abs_Quad(Address disp) {
19596 int miStart = mi;
19597 // no group 1 to 4 prefix byte
19598 generateREXprefix(true, null, null, null);
19599 setMachineCodes(mi++, (byte) 0xF7);
19600 // "register 0x2" is really part of the opcode
19601 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19602 if (lister != null) lister.RA(miStart, "NOT", disp);
19603 }
19604
19605 /**
19606 * Generate a NOT to register offset. That is,
19607 * <PRE>
19608 * ~ (quad) [base + index<<scale + disp]
19609 * </PRE>
19610 *
19611 * @param base the destination base register
19612 * @param index the destination index register
19613 * @param scale the destination shift amount
19614 * @param disp the destination displacement
19615 */
19616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19617 public final void emitNOT_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
19618 int miStart = mi;
19619 // no group 1 to 4 prefix byte
19620 generateREXprefix(true, null, index, base);
19621 setMachineCodes(mi++, (byte) 0xF7);
19622 // "register 0x2" is really part of the opcode
19623 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19624 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19625 }
19626
19627 /**
19628 * Generate a MUL by register. That is,
19629 * <PRE>
19630 * EAX:EDX = EAX * srcReg
19631 * </PRE>
19632 *
19633 * @param dstReg must always be EAX/R0
19634 * @param srcReg the source register
19635 */
19636 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19637 public final void emitMUL_Reg_Reg(GPR dstReg, GPR srcReg) {
19638 int miStart = mi;
19639 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19640 generateREXprefix(false, null, null, srcReg);
19641 setMachineCodes(mi++, (byte) 0xF7);
19642 emitRegRegOperands(srcReg, GPR.getForOpcode(0x4));
19643 if (lister != null) lister.RR(miStart, "MUL", dstReg, srcReg);
19644 }
19645
19646 /**
19647 * Generate a MUL by register displacement. That is,
19648 * <PRE>
19649 * EAX:EDX = EAX * [srcBase + srcDisp]
19650 * </PRE>
19651 *
19652 * @param dstReg must always be EAX/R0
19653 * @param srcBase the source base register
19654 * @param srcDisp the source displacement
19655 */
19656 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19657 public final void emitMUL_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
19658 int miStart = mi;
19659 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19660 generateREXprefix(false, null, null, srcBase);
19661 setMachineCodes(mi++, (byte) 0xF7);
19662 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x4));
19663 if (lister != null) lister.RRD(miStart, "MUL", dstReg, srcBase, srcDisp);
19664 }
19665
19666 /**
19667 * Generate a MUL by register indirect. That is,
19668 * <PRE>
19669 * EAX:EDX = EAX * [srcBase]
19670 * </PRE>
19671 *
19672 * @param dstReg must always be EAX/R0
19673 * @param srcBase the source base register
19674 */
19675 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19676 public final void emitMUL_Reg_RegInd(GPR dstReg, GPR srcBase) {
19677 int miStart = mi;
19678 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19679 generateREXprefix(false, null, null, srcBase);
19680 setMachineCodes(mi++, (byte) 0xF7);
19681 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x4));
19682 if (lister != null) lister.RRN(miStart, "MUL", dstReg, srcBase);
19683 }
19684
19685 /**
19686 * Generate a MUL by register indexed. That is,
19687 * <PRE>
19688 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19689 * </PRE>
19690 *
19691 * @param dstReg must always be EAX/R0
19692 * @param srcBase the source base register
19693 * @param srcIndex the source index register
19694 * @param srcScale the source scale of the index
19695 * @param srcDisp the source displacement
19696 */
19697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19698 public final void emitMUL_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19699 int miStart = mi;
19700 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19701 generateREXprefix(false, null, srcIndex, srcBase);
19702 setMachineCodes(mi++, (byte) 0xF7);
19703 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19704 if (lister != null) lister.RRXD(miStart, "MUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19705 }
19706
19707 /**
19708 * Generate a MUL by register offseted. That is,
19709 * <PRE>
19710 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19711 * </PRE>
19712 *
19713 * @param dstReg must always be EAX/R0
19714 * @param srcIndex the source index register
19715 * @param srcScale the source scale of the index
19716 * @param srcDisp the source displacement
19717 */
19718 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19719 public final void emitMUL_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19720 int miStart = mi;
19721 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19722 generateREXprefix(false, null, srcIndex, null);
19723 setMachineCodes(mi++, (byte) 0xF7);
19724 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19725 if (lister != null) lister.RRFD(miStart, "MUL", dstReg, srcIndex, srcScale, srcDisp);
19726 }
19727
19728 /**
19729 * Generate a MUL by absolute address. That is,
19730 * <PRE>
19731 * EAX:EDX = EAX * [srcDisp]
19732 * </PRE>
19733 *
19734 * @param dstReg must always be EAX/R0
19735 * @param srcDisp the source displacement
19736 */
19737 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19738 public final void emitMUL_Reg_Abs(GPR dstReg, Address srcDisp) {
19739 int miStart = mi;
19740 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19741 generateREXprefix(false, null, null, null);
19742 setMachineCodes(mi++, (byte) 0xF7);
19743 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x4));
19744 if (lister != null) lister.RRA(miStart, "MUL", dstReg, srcDisp);
19745 }
19746
19747 /**
19748 * Generate a MUL by register. That is,
19749 * <PRE>
19750 * EAX:EDX = EAX * srcReg
19751 * </PRE>
19752 *
19753 * @param dstReg must always be EAX/R0
19754 * @param srcReg the source register
19755 */
19756 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19757 public final void emitMUL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
19758 int miStart = mi;
19759 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19760 generateREXprefix(true, null, null, srcReg);
19761 setMachineCodes(mi++, (byte) 0xF7);
19762 emitRegRegOperands(srcReg, GPR.getForOpcode(0x4));
19763 if (lister != null) lister.RR(miStart, "MUL", dstReg, srcReg);
19764 }
19765
19766 /**
19767 * Generate a MUL by register displacement. That is,
19768 * <PRE>
19769 * EAX:EDX = EAX * [srcBase + srcDisp]
19770 * </PRE>
19771 *
19772 * @param dstReg must always be EAX/R0
19773 * @param srcBase the source base register
19774 * @param srcDisp the source displacement
19775 */
19776 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19777 public final void emitMUL_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
19778 int miStart = mi;
19779 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19780 generateREXprefix(true, null, null, srcBase);
19781 setMachineCodes(mi++, (byte) 0xF7);
19782 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x4));
19783 if (lister != null) lister.RRD(miStart, "MUL", dstReg, srcBase, srcDisp);
19784 }
19785
19786 /**
19787 * Generate a MUL by register indirect. That is,
19788 * <PRE>
19789 * EAX:EDX = EAX * [srcBase]
19790 * </PRE>
19791 *
19792 * @param dstReg must always be EAX/R0
19793 * @param srcBase the source base register
19794 */
19795 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19796 public final void emitMUL_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
19797 int miStart = mi;
19798 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19799 generateREXprefix(true, null, null, srcBase);
19800 setMachineCodes(mi++, (byte) 0xF7);
19801 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x4));
19802 if (lister != null) lister.RRN(miStart, "MUL", dstReg, srcBase);
19803 }
19804
19805 /**
19806 * Generate a MUL by register indexed. That is,
19807 * <PRE>
19808 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19809 * </PRE>
19810 *
19811 * @param dstReg must always be EAX/R0
19812 * @param srcBase the source base register
19813 * @param srcIndex the source index register
19814 * @param srcScale the source scale of the index
19815 * @param srcDisp the source displacement
19816 */
19817 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19818 public final void emitMUL_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19819 int miStart = mi;
19820 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19821 generateREXprefix(true, null, srcIndex, srcBase);
19822 setMachineCodes(mi++, (byte) 0xF7);
19823 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19824 if (lister != null) lister.RRXD(miStart, "MUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19825 }
19826
19827 /**
19828 * Generate a MUL by register offseted. That is,
19829 * <PRE>
19830 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19831 * </PRE>
19832 *
19833 * @param dstReg must always be EAX/R0
19834 * @param srcIndex the source index register
19835 * @param srcScale the source scale of the index
19836 * @param srcDisp the source displacement
19837 */
19838 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19839 public final void emitMUL_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19840 int miStart = mi;
19841 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19842 generateREXprefix(true, null, srcIndex, null);
19843 setMachineCodes(mi++, (byte) 0xF7);
19844 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19845 if (lister != null) lister.RRFD(miStart, "MUL", dstReg, srcIndex, srcScale, srcDisp);
19846 }
19847
19848 /**
19849 * Generate a MUL by absolute address. That is,
19850 * <PRE>
19851 * EAX:EDX = EAX * [srcDisp]
19852 * </PRE>
19853 *
19854 * @param dstReg must always be EAX/R0
19855 * @param srcDisp the source displacement
19856 */
19857 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19858 public final void emitMUL_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
19859 int miStart = mi;
19860 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19861 generateREXprefix(true, null, null, null);
19862 setMachineCodes(mi++, (byte) 0xF7);
19863 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x4));
19864 if (lister != null) lister.RRA(miStart, "MUL", dstReg, srcDisp);
19865 }
19866
19867 /**
19868 * Generate a IMUL1 by register. That is,
19869 * <PRE>
19870 * EAX:EDX = EAX * srcReg
19871 * </PRE>
19872 *
19873 * @param dstReg must always be EAX/R0
19874 * @param srcReg the source register
19875 */
19876 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19877 public final void emitIMUL1_Reg_Reg(GPR dstReg, GPR srcReg) {
19878 int miStart = mi;
19879 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19880 generateREXprefix(false, null, null, srcReg);
19881 setMachineCodes(mi++, (byte) 0xF7);
19882 emitRegRegOperands(srcReg, GPR.getForOpcode(0x5));
19883 if (lister != null) lister.RR(miStart, "IMUL1", dstReg, srcReg);
19884 }
19885
19886 /**
19887 * Generate a IMUL1 by register displacement. That is,
19888 * <PRE>
19889 * EAX:EDX = EAX * [srcBase + srcDisp]
19890 * </PRE>
19891 *
19892 * @param dstReg must always be EAX/R0
19893 * @param srcBase the source base register
19894 * @param srcDisp the source displacement
19895 */
19896 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19897 public final void emitIMUL1_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
19898 int miStart = mi;
19899 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19900 generateREXprefix(false, null, null, srcBase);
19901 setMachineCodes(mi++, (byte) 0xF7);
19902 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x5));
19903 if (lister != null) lister.RRD(miStart, "IMUL1", dstReg, srcBase, srcDisp);
19904 }
19905
19906 /**
19907 * Generate a IMUL1 by register indirect. That is,
19908 * <PRE>
19909 * EAX:EDX = EAX * [srcBase]
19910 * </PRE>
19911 *
19912 * @param dstReg must always be EAX/R0
19913 * @param srcBase the source base register
19914 */
19915 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19916 public final void emitIMUL1_Reg_RegInd(GPR dstReg, GPR srcBase) {
19917 int miStart = mi;
19918 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19919 generateREXprefix(false, null, null, srcBase);
19920 setMachineCodes(mi++, (byte) 0xF7);
19921 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x5));
19922 if (lister != null) lister.RRN(miStart, "IMUL1", dstReg, srcBase);
19923 }
19924
19925 /**
19926 * Generate a IMUL1 by register indexed. That is,
19927 * <PRE>
19928 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19929 * </PRE>
19930 *
19931 * @param dstReg must always be EAX/R0
19932 * @param srcBase the source base register
19933 * @param srcIndex the source index register
19934 * @param srcScale the source scale of the index
19935 * @param srcDisp the source displacement
19936 */
19937 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19938 public final void emitIMUL1_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19939 int miStart = mi;
19940 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19941 generateREXprefix(false, null, srcIndex, srcBase);
19942 setMachineCodes(mi++, (byte) 0xF7);
19943 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
19944 if (lister != null) lister.RRXD(miStart, "IMUL1", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19945 }
19946
19947 /**
19948 * Generate a IMUL1 by register offseted. That is,
19949 * <PRE>
19950 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19951 * </PRE>
19952 *
19953 * @param dstReg must always be EAX/R0
19954 * @param srcIndex the source index register
19955 * @param srcScale the source scale of the index
19956 * @param srcDisp the source displacement
19957 */
19958 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19959 public final void emitIMUL1_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19960 int miStart = mi;
19961 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19962 generateREXprefix(false, null, srcIndex, null);
19963 setMachineCodes(mi++, (byte) 0xF7);
19964 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
19965 if (lister != null) lister.RRFD(miStart, "IMUL1", dstReg, srcIndex, srcScale, srcDisp);
19966 }
19967
19968 /**
19969 * Generate a IMUL1 by absolute address. That is,
19970 * <PRE>
19971 * EAX:EDX = EAX * [srcDisp]
19972 * </PRE>
19973 *
19974 * @param dstReg must always be EAX/R0
19975 * @param srcDisp the source displacement
19976 */
19977 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19978 public final void emitIMUL1_Reg_Abs(GPR dstReg, Address srcDisp) {
19979 int miStart = mi;
19980 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19981 generateREXprefix(false, null, null, null);
19982 setMachineCodes(mi++, (byte) 0xF7);
19983 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x5));
19984 if (lister != null) lister.RRA(miStart, "IMUL1", dstReg, srcDisp);
19985 }
19986
19987 /**
19988 * Generate a IMUL1 by register. That is,
19989 * <PRE>
19990 * EAX:EDX = EAX * srcReg
19991 * </PRE>
19992 *
19993 * @param dstReg must always be EAX/R0
19994 * @param srcReg the source register
19995 */
19996 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19997 public final void emitIMUL1_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
19998 int miStart = mi;
19999 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20000 generateREXprefix(true, null, null, srcReg);
20001 setMachineCodes(mi++, (byte) 0xF7);
20002 emitRegRegOperands(srcReg, GPR.getForOpcode(0x5));
20003 if (lister != null) lister.RR(miStart, "IMUL1", dstReg, srcReg);
20004 }
20005
20006 /**
20007 * Generate a IMUL1 by register displacement. That is,
20008 * <PRE>
20009 * EAX:EDX = EAX * [srcBase + srcDisp]
20010 * </PRE>
20011 *
20012 * @param dstReg must always be EAX/R0
20013 * @param srcBase the source base register
20014 * @param srcDisp the source displacement
20015 */
20016 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20017 public final void emitIMUL1_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20018 int miStart = mi;
20019 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20020 generateREXprefix(true, null, null, srcBase);
20021 setMachineCodes(mi++, (byte) 0xF7);
20022 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x5));
20023 if (lister != null) lister.RRD(miStart, "IMUL1", dstReg, srcBase, srcDisp);
20024 }
20025
20026 /**
20027 * Generate a IMUL1 by register indirect. That is,
20028 * <PRE>
20029 * EAX:EDX = EAX * [srcBase]
20030 * </PRE>
20031 *
20032 * @param dstReg must always be EAX/R0
20033 * @param srcBase the source base register
20034 */
20035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20036 public final void emitIMUL1_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20037 int miStart = mi;
20038 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20039 generateREXprefix(true, null, null, srcBase);
20040 setMachineCodes(mi++, (byte) 0xF7);
20041 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x5));
20042 if (lister != null) lister.RRN(miStart, "IMUL1", dstReg, srcBase);
20043 }
20044
20045 /**
20046 * Generate a IMUL1 by register indexed. That is,
20047 * <PRE>
20048 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
20049 * </PRE>
20050 *
20051 * @param dstReg must always be EAX/R0
20052 * @param srcBase the source base register
20053 * @param srcIndex the source index register
20054 * @param srcScale the source scale of the index
20055 * @param srcDisp the source displacement
20056 */
20057 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20058 public final void emitIMUL1_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20059 int miStart = mi;
20060 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20061 generateREXprefix(true, null, srcIndex, srcBase);
20062 setMachineCodes(mi++, (byte) 0xF7);
20063 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
20064 if (lister != null) lister.RRXD(miStart, "IMUL1", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20065 }
20066
20067 /**
20068 * Generate a IMUL1 by register offseted. That is,
20069 * <PRE>
20070 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
20071 * </PRE>
20072 *
20073 * @param dstReg must always be EAX/R0
20074 * @param srcIndex the source index register
20075 * @param srcScale the source scale of the index
20076 * @param srcDisp the source displacement
20077 */
20078 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20079 public final void emitIMUL1_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20080 int miStart = mi;
20081 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20082 generateREXprefix(true, null, srcIndex, null);
20083 setMachineCodes(mi++, (byte) 0xF7);
20084 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
20085 if (lister != null) lister.RRFD(miStart, "IMUL1", dstReg, srcIndex, srcScale, srcDisp);
20086 }
20087
20088 /**
20089 * Generate a IMUL1 by absolute address. That is,
20090 * <PRE>
20091 * EAX:EDX = EAX * [srcDisp]
20092 * </PRE>
20093 *
20094 * @param dstReg must always be EAX/R0
20095 * @param srcDisp the source displacement
20096 */
20097 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20098 public final void emitIMUL1_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20099 int miStart = mi;
20100 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20101 generateREXprefix(true, null, null, null);
20102 setMachineCodes(mi++, (byte) 0xF7);
20103 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x5));
20104 if (lister != null) lister.RRA(miStart, "IMUL1", dstReg, srcDisp);
20105 }
20106
20107 /**
20108 * Generate a DIV by register. That is,
20109 * <PRE>
20110 * EAX:EDX = EAX / srcReg
20111 * </PRE>
20112 *
20113 * @param dstReg must always be EAX/R0
20114 * @param srcReg the source register
20115 */
20116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20117 public final void emitDIV_Reg_Reg(GPR dstReg, GPR srcReg) {
20118 int miStart = mi;
20119 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20120 generateREXprefix(false, null, null, srcReg);
20121 setMachineCodes(mi++, (byte) 0xF7);
20122 emitRegRegOperands(srcReg, GPR.getForOpcode(0x6));
20123 if (lister != null) lister.RR(miStart, "DIV", dstReg, srcReg);
20124 }
20125
20126 /**
20127 * Generate a DIV by register displacement. That is,
20128 * <PRE>
20129 * EAX:EDX = EAX / [srcBase + srcDisp]
20130 * </PRE>
20131 *
20132 * @param dstReg must always be EAX/R0
20133 * @param srcBase the source base register
20134 * @param srcDisp the source displacement
20135 */
20136 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20137 public final void emitDIV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20138 int miStart = mi;
20139 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20140 generateREXprefix(false, null, null, srcBase);
20141 setMachineCodes(mi++, (byte) 0xF7);
20142 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x6));
20143 if (lister != null) lister.RRD(miStart, "DIV", dstReg, srcBase, srcDisp);
20144 }
20145
20146 /**
20147 * Generate a DIV by register indirect. That is,
20148 * <PRE>
20149 * EAX:EDX = EAX / [srcBase]
20150 * </PRE>
20151 *
20152 * @param dstReg must always be EAX/R0
20153 * @param srcBase the source base register
20154 */
20155 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20156 public final void emitDIV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20157 int miStart = mi;
20158 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20159 generateREXprefix(false, null, null, srcBase);
20160 setMachineCodes(mi++, (byte) 0xF7);
20161 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x6));
20162 if (lister != null) lister.RRN(miStart, "DIV", dstReg, srcBase);
20163 }
20164
20165 /**
20166 * Generate a DIV by register indexed. That is,
20167 * <PRE>
20168 * EAX:EDX = EAX / [srcBase + srcIndex<<srcScale + srcDisp]
20169 * </PRE>
20170 *
20171 * @param dstReg must always be EAX/R0
20172 * @param srcBase the source base register
20173 * @param srcIndex the source index register
20174 * @param srcScale the source scale of the index
20175 * @param srcDisp the source displacement
20176 */
20177 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20178 public final void emitDIV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20179 int miStart = mi;
20180 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20181 generateREXprefix(false, null, srcIndex, srcBase);
20182 setMachineCodes(mi++, (byte) 0xF7);
20183 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20184 if (lister != null) lister.RRXD(miStart, "DIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20185 }
20186
20187 /**
20188 * Generate a DIV by register offseted. That is,
20189 * <PRE>
20190 * EAX:EDX = EAX / [srcIndex<<srcScale + srcDisp]
20191 * </PRE>
20192 *
20193 * @param dstReg must always be EAX/R0
20194 * @param srcIndex the source index register
20195 * @param srcScale the source scale of the index
20196 * @param srcDisp the source displacement
20197 */
20198 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20199 public final void emitDIV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20200 int miStart = mi;
20201 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20202 generateREXprefix(false, null, srcIndex, null);
20203 setMachineCodes(mi++, (byte) 0xF7);
20204 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20205 if (lister != null) lister.RRFD(miStart, "DIV", dstReg, srcIndex, srcScale, srcDisp);
20206 }
20207
20208 /**
20209 * Generate a DIV by absolute address. That is,
20210 * <PRE>
20211 * EAX:EDX = EAX / [srcDisp]
20212 * </PRE>
20213 *
20214 * @param dstReg must always be EAX/R0
20215 * @param srcDisp the source displacement
20216 */
20217 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20218 public final void emitDIV_Reg_Abs(GPR dstReg, Address srcDisp) {
20219 int miStart = mi;
20220 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20221 generateREXprefix(false, null, null, null);
20222 setMachineCodes(mi++, (byte) 0xF7);
20223 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x6));
20224 if (lister != null) lister.RRA(miStart, "DIV", dstReg, srcDisp);
20225 }
20226
20227 /**
20228 * Generate a DIV by register. That is,
20229 * <PRE>
20230 * EAX:EDX = EAX / srcReg
20231 * </PRE>
20232 *
20233 * @param dstReg must always be EAX/R0
20234 * @param srcReg the source register
20235 */
20236 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20237 public final void emitDIV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
20238 int miStart = mi;
20239 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20240 generateREXprefix(true, null, null, srcReg);
20241 setMachineCodes(mi++, (byte) 0xF7);
20242 emitRegRegOperands(srcReg, GPR.getForOpcode(0x6));
20243 if (lister != null) lister.RR(miStart, "DIV", dstReg, srcReg);
20244 }
20245
20246 /**
20247 * Generate a DIV by register displacement. That is,
20248 * <PRE>
20249 * EAX:EDX = EAX / [srcBase + srcDisp]
20250 * </PRE>
20251 *
20252 * @param dstReg must always be EAX/R0
20253 * @param srcBase the source base register
20254 * @param srcDisp the source displacement
20255 */
20256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20257 public final void emitDIV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20258 int miStart = mi;
20259 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20260 generateREXprefix(true, null, null, srcBase);
20261 setMachineCodes(mi++, (byte) 0xF7);
20262 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x6));
20263 if (lister != null) lister.RRD(miStart, "DIV", dstReg, srcBase, srcDisp);
20264 }
20265
20266 /**
20267 * Generate a DIV by register indirect. That is,
20268 * <PRE>
20269 * EAX:EDX = EAX / [srcBase]
20270 * </PRE>
20271 *
20272 * @param dstReg must always be EAX/R0
20273 * @param srcBase the source base register
20274 */
20275 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20276 public final void emitDIV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20277 int miStart = mi;
20278 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20279 generateREXprefix(true, null, null, srcBase);
20280 setMachineCodes(mi++, (byte) 0xF7);
20281 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x6));
20282 if (lister != null) lister.RRN(miStart, "DIV", dstReg, srcBase);
20283 }
20284
20285 /**
20286 * Generate a DIV by register indexed. That is,
20287 * <PRE>
20288 * EAX:EDX = EAX / [srcBase + srcIndex<<srcScale + srcDisp]
20289 * </PRE>
20290 *
20291 * @param dstReg must always be EAX/R0
20292 * @param srcBase the source base register
20293 * @param srcIndex the source index register
20294 * @param srcScale the source scale of the index
20295 * @param srcDisp the source displacement
20296 */
20297 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20298 public final void emitDIV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20299 int miStart = mi;
20300 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20301 generateREXprefix(true, null, srcIndex, srcBase);
20302 setMachineCodes(mi++, (byte) 0xF7);
20303 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20304 if (lister != null) lister.RRXD(miStart, "DIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20305 }
20306
20307 /**
20308 * Generate a DIV by register offseted. That is,
20309 * <PRE>
20310 * EAX:EDX = EAX / [srcIndex<<srcScale + srcDisp]
20311 * </PRE>
20312 *
20313 * @param dstReg must always be EAX/R0
20314 * @param srcIndex the source index register
20315 * @param srcScale the source scale of the index
20316 * @param srcDisp the source displacement
20317 */
20318 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20319 public final void emitDIV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20320 int miStart = mi;
20321 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20322 generateREXprefix(true, null, srcIndex, null);
20323 setMachineCodes(mi++, (byte) 0xF7);
20324 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20325 if (lister != null) lister.RRFD(miStart, "DIV", dstReg, srcIndex, srcScale, srcDisp);
20326 }
20327
20328 /**
20329 * Generate a DIV by absolute address. That is,
20330 * <PRE>
20331 * EAX:EDX = EAX / [srcDisp]
20332 * </PRE>
20333 *
20334 * @param dstReg must always be EAX/R0
20335 * @param srcDisp the source displacement
20336 */
20337 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20338 public final void emitDIV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20339 int miStart = mi;
20340 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20341 generateREXprefix(true, null, null, null);
20342 setMachineCodes(mi++, (byte) 0xF7);
20343 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x6));
20344 if (lister != null) lister.RRA(miStart, "DIV", dstReg, srcDisp);
20345 }
20346
20347 /**
20348 * Generate a IDIV by register. That is,
20349 * <PRE>
20350 * EAX:EDX = EAX u/ srcReg
20351 * </PRE>
20352 *
20353 * @param dstReg must always be EAX/R0
20354 * @param srcReg the source register
20355 */
20356 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20357 public final void emitIDIV_Reg_Reg(GPR dstReg, GPR srcReg) {
20358 int miStart = mi;
20359 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20360 generateREXprefix(false, null, null, srcReg);
20361 setMachineCodes(mi++, (byte) 0xF7);
20362 emitRegRegOperands(srcReg, GPR.getForOpcode(0x7));
20363 if (lister != null) lister.RR(miStart, "IDIV", dstReg, srcReg);
20364 }
20365
20366 /**
20367 * Generate a IDIV by register displacement. That is,
20368 * <PRE>
20369 * EAX:EDX = EAX u/ [srcBase + srcDisp]
20370 * </PRE>
20371 *
20372 * @param dstReg must always be EAX/R0
20373 * @param srcBase the source base register
20374 * @param srcDisp the source displacement
20375 */
20376 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20377 public final void emitIDIV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20378 int miStart = mi;
20379 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20380 generateREXprefix(false, null, null, srcBase);
20381 setMachineCodes(mi++, (byte) 0xF7);
20382 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x7));
20383 if (lister != null) lister.RRD(miStart, "IDIV", dstReg, srcBase, srcDisp);
20384 }
20385
20386 /**
20387 * Generate a IDIV by register indirect. That is,
20388 * <PRE>
20389 * EAX:EDX = EAX u/ [srcBase]
20390 * </PRE>
20391 *
20392 * @param dstReg must always be EAX/R0
20393 * @param srcBase the source base register
20394 */
20395 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20396 public final void emitIDIV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20397 int miStart = mi;
20398 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20399 generateREXprefix(false, null, null, srcBase);
20400 setMachineCodes(mi++, (byte) 0xF7);
20401 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x7));
20402 if (lister != null) lister.RRN(miStart, "IDIV", dstReg, srcBase);
20403 }
20404
20405 /**
20406 * Generate a IDIV by register indexed. That is,
20407 * <PRE>
20408 * EAX:EDX = EAX u/ [srcBase + srcIndex<<srcScale + srcDisp]
20409 * </PRE>
20410 *
20411 * @param dstReg must always be EAX/R0
20412 * @param srcBase the source base register
20413 * @param srcIndex the source index register
20414 * @param srcScale the source scale of the index
20415 * @param srcDisp the source displacement
20416 */
20417 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20418 public final void emitIDIV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20419 int miStart = mi;
20420 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20421 generateREXprefix(false, null, srcIndex, srcBase);
20422 setMachineCodes(mi++, (byte) 0xF7);
20423 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20424 if (lister != null) lister.RRXD(miStart, "IDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20425 }
20426
20427 /**
20428 * Generate a IDIV by register offseted. That is,
20429 * <PRE>
20430 * EAX:EDX = EAX u/ [srcIndex<<srcScale + srcDisp]
20431 * </PRE>
20432 *
20433 * @param dstReg must always be EAX/R0
20434 * @param srcIndex the source index register
20435 * @param srcScale the source scale of the index
20436 * @param srcDisp the source displacement
20437 */
20438 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20439 public final void emitIDIV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20440 int miStart = mi;
20441 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20442 generateREXprefix(false, null, srcIndex, null);
20443 setMachineCodes(mi++, (byte) 0xF7);
20444 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20445 if (lister != null) lister.RRFD(miStart, "IDIV", dstReg, srcIndex, srcScale, srcDisp);
20446 }
20447
20448 /**
20449 * Generate a IDIV by absolute address. That is,
20450 * <PRE>
20451 * EAX:EDX = EAX u/ [srcDisp]
20452 * </PRE>
20453 *
20454 * @param dstReg must always be EAX/R0
20455 * @param srcDisp the source displacement
20456 */
20457 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20458 public final void emitIDIV_Reg_Abs(GPR dstReg, Address srcDisp) {
20459 int miStart = mi;
20460 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20461 generateREXprefix(false, null, null, null);
20462 setMachineCodes(mi++, (byte) 0xF7);
20463 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x7));
20464 if (lister != null) lister.RRA(miStart, "IDIV", dstReg, srcDisp);
20465 }
20466
20467 /**
20468 * Generate a IDIV by register. That is,
20469 * <PRE>
20470 * EAX:EDX = EAX u/ srcReg
20471 * </PRE>
20472 *
20473 * @param dstReg must always be EAX/R0
20474 * @param srcReg the source register
20475 */
20476 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20477 public final void emitIDIV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
20478 int miStart = mi;
20479 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20480 generateREXprefix(true, null, null, srcReg);
20481 setMachineCodes(mi++, (byte) 0xF7);
20482 emitRegRegOperands(srcReg, GPR.getForOpcode(0x7));
20483 if (lister != null) lister.RR(miStart, "IDIV", dstReg, srcReg);
20484 }
20485
20486 /**
20487 * Generate a IDIV by register displacement. That is,
20488 * <PRE>
20489 * EAX:EDX = EAX u/ [srcBase + srcDisp]
20490 * </PRE>
20491 *
20492 * @param dstReg must always be EAX/R0
20493 * @param srcBase the source base register
20494 * @param srcDisp the source displacement
20495 */
20496 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20497 public final void emitIDIV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20498 int miStart = mi;
20499 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20500 generateREXprefix(true, null, null, srcBase);
20501 setMachineCodes(mi++, (byte) 0xF7);
20502 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x7));
20503 if (lister != null) lister.RRD(miStart, "IDIV", dstReg, srcBase, srcDisp);
20504 }
20505
20506 /**
20507 * Generate a IDIV by register indirect. That is,
20508 * <PRE>
20509 * EAX:EDX = EAX u/ [srcBase]
20510 * </PRE>
20511 *
20512 * @param dstReg must always be EAX/R0
20513 * @param srcBase the source base register
20514 */
20515 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20516 public final void emitIDIV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20517 int miStart = mi;
20518 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20519 generateREXprefix(true, null, null, srcBase);
20520 setMachineCodes(mi++, (byte) 0xF7);
20521 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x7));
20522 if (lister != null) lister.RRN(miStart, "IDIV", dstReg, srcBase);
20523 }
20524
20525 /**
20526 * Generate a IDIV by register indexed. That is,
20527 * <PRE>
20528 * EAX:EDX = EAX u/ [srcBase + srcIndex<<srcScale + srcDisp]
20529 * </PRE>
20530 *
20531 * @param dstReg must always be EAX/R0
20532 * @param srcBase the source base register
20533 * @param srcIndex the source index register
20534 * @param srcScale the source scale of the index
20535 * @param srcDisp the source displacement
20536 */
20537 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20538 public final void emitIDIV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20539 int miStart = mi;
20540 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20541 generateREXprefix(true, null, srcIndex, srcBase);
20542 setMachineCodes(mi++, (byte) 0xF7);
20543 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20544 if (lister != null) lister.RRXD(miStart, "IDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20545 }
20546
20547 /**
20548 * Generate a IDIV by register offseted. That is,
20549 * <PRE>
20550 * EAX:EDX = EAX u/ [srcIndex<<srcScale + srcDisp]
20551 * </PRE>
20552 *
20553 * @param dstReg must always be EAX/R0
20554 * @param srcIndex the source index register
20555 * @param srcScale the source scale of the index
20556 * @param srcDisp the source displacement
20557 */
20558 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20559 public final void emitIDIV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20560 int miStart = mi;
20561 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20562 generateREXprefix(true, null, srcIndex, null);
20563 setMachineCodes(mi++, (byte) 0xF7);
20564 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20565 if (lister != null) lister.RRFD(miStart, "IDIV", dstReg, srcIndex, srcScale, srcDisp);
20566 }
20567
20568 /**
20569 * Generate a IDIV by absolute address. That is,
20570 * <PRE>
20571 * EAX:EDX = EAX u/ [srcDisp]
20572 * </PRE>
20573 *
20574 * @param dstReg must always be EAX/R0
20575 * @param srcDisp the source displacement
20576 */
20577 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20578 public final void emitIDIV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20579 int miStart = mi;
20580 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20581 generateREXprefix(true, null, null, null);
20582 setMachineCodes(mi++, (byte) 0xF7);
20583 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x7));
20584 if (lister != null) lister.RRA(miStart, "IDIV", dstReg, srcDisp);
20585 }
20586
20587 /**
20588 * Generate a register(indirect)--register MOV. That is,
20589 * <PRE>
20590 * [dstBase] := srcReg
20591 * </PRE>
20592 *
20593 * @param dstBase the destination base
20594 * @param srcReg the source register
20595 */
20596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20597 public final void emitMOV_RegInd_Reg(GPR dstBase, GPR srcReg) {
20598 int miStart = mi;
20599 // no group 1 to 4 prefix byte
20600 generateREXprefix(false, srcReg, null, dstBase);
20601 // single byte opcode
20602 setMachineCodes(mi++, (byte) 0x89);
20603 emitRegIndirectRegOperands(dstBase, srcReg);
20604 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
20605 }
20606
20607 /**
20608 * Generate a register-offset--register MOV. That is,
20609 * <PRE>
20610 * [dstReg<<dstScale + dstDisp] := srcReg
20611 * </PRE>
20612 *
20613 * @param dstIndex the destination index register
20614 * @param dstScale the destination shift amount
20615 * @param dstDisp the destination displacement
20616 * @param srcReg the source register
20617 */
20618 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
20619 public final void emitMOV_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20620 int miStart = mi;
20621 // no group 1 to 4 prefix byte
20622 generateREXprefix(false, srcReg, dstIndex, null);
20623 // single byte opcode
20624 setMachineCodes(mi++, (byte) 0x89);
20625 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
20626 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
20627 }
20628
20629 /**
20630 * Generate a absolute--register MOV. That is,
20631 * <PRE>
20632 * [dstDisp] := srcReg
20633 * </PRE>
20634 *
20635 * @param dstDisp the destination address
20636 * @param srcReg the source register
20637 */
20638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
20639 public final void emitMOV_Abs_Reg(Address dstDisp, GPR srcReg) {
20640 int miStart = mi;
20641 // no group 1 to 4 prefix byte
20642 generateREXprefix(false, srcReg, null, null);
20643 // single byte opcode
20644 setMachineCodes(mi++, (byte) 0x89);
20645 emitAbsRegOperands(dstDisp, srcReg);
20646 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
20647 }
20648
20649 /**
20650 * Generate a register-index--register MOV. That is,
20651 * <PRE>
20652 * [dstBase + dstIndex<<dstScale + dstDisp] := srcReg
20653 * </PRE>
20654 *
20655 * @param dstBase the base register
20656 * @param dstIndex the destination index register
20657 * @param dstScale the destination shift amount
20658 * @param dstDisp the destination displacement
20659 * @param srcReg the source register
20660 */
20661 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
20662 public final void emitMOV_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20663 int miStart = mi;
20664 // no group 1 to 4 prefix byte
20665 generateREXprefix(false, srcReg, dstIndex, dstBase);
20666 // single byte opcode
20667 setMachineCodes(mi++, (byte) 0x89);
20668 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
20669 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
20670 }
20671
20672 /**
20673 * Generate a register-displacement--register MOV. That is,
20674 * <PRE>
20675 * [dstBase + dstDisp] := srcReg
20676 * </PRE>
20677 *
20678 * @param dstBase the base register
20679 * @param dstDisp the destination displacement
20680 * @param srcReg the source register
20681 */
20682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
20683 public final void emitMOV_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
20684 int miStart = mi;
20685 // no group 1 to 4 prefix byte
20686 generateREXprefix(false, srcReg, null, dstBase);
20687 // single byte opcode
20688 setMachineCodes(mi++, (byte) 0x89);
20689 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
20690 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
20691 }
20692
20693 /**
20694 * Generate a register--register MOV. That is,
20695 * <PRE>
20696 * dstReg := srcReg
20697 * </PRE>
20698 *
20699 * @param dstReg the destination register
20700 * @param srcReg the source register
20701 */
20702 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20703 public final void emitMOV_Reg_Reg(GPR dstReg, GPR srcReg) {
20704 int miStart = mi;
20705 // no group 1 to 4 prefix byte
20706 generateREXprefix(false, srcReg, null, dstReg);
20707 // single byte opcode
20708 setMachineCodes(mi++, (byte) 0x89);
20709 emitRegRegOperands(dstReg, srcReg);
20710 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
20711 }
20712
20713 /**
20714 * Generate a register--register-displacement MOV. That is,
20715 * <PRE>
20716 * dstReg := [srcReg + srcDisp]
20717 * </PRE>
20718 *
20719 * @param dstReg the destination register
20720 * @param srcBase the source register
20721 * @param srcDisp the source displacement
20722 */
20723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20724 public final void emitMOV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20725 int miStart = mi;
20726 // no group 1 to 4 prefix byte
20727 generateREXprefix(false, dstReg, null, srcBase);
20728 // single byte opcode
20729 setMachineCodes(mi++, (byte) 0x8B);
20730 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
20731 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
20732 }
20733
20734 /**
20735 * Generate a register--register-offset MOV. That is,
20736 * <PRE>
20737 * dstReg := [srcIndex<<srcScale + srcDisp]
20738 * </PRE>
20739 *
20740 * @param dstReg the destination register
20741 * @param srcIndex the source index register
20742 * @param srcScale the source shift amount
20743 * @param srcDisp the source displacement
20744 */
20745 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20746 public final void emitMOV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20747 int miStart = mi;
20748 // no group 1 to 4 prefix byte
20749 generateREXprefix(false, dstReg, srcIndex, null);
20750 // single byte opcode
20751 setMachineCodes(mi++, (byte) 0x8B);
20752 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
20753 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
20754 }
20755
20756 /**
20757 * Generate a register--register-offset MOV. That is,
20758 * <PRE>
20759 * dstReg := [srcDisp]
20760 * </PRE>
20761 *
20762 * @param dstReg the destination register
20763 * @param srcDisp the source displacement
20764 */
20765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20766 public final void emitMOV_Reg_Abs(GPR dstReg, Address srcDisp) {
20767 int miStart = mi;
20768 // no group 1 to 4 prefix byte
20769 generateREXprefix(false, dstReg, null, null);
20770 // single byte opcode
20771 setMachineCodes(mi++, (byte) 0x8B);
20772 emitAbsRegOperands(srcDisp, dstReg);
20773 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
20774 }
20775
20776 /**
20777 * Generate a register--register-offset MOV. That is,
20778 * <PRE>
20779 * dstReg := [srcBase + srcIndex<<srcScale + srcDisp]
20780 * </PRE>
20781 *
20782 * @param dstReg the destination register
20783 * @param srcBase the source base register
20784 * @param srcIndex the source index register
20785 * @param srcScale the source shift amount
20786 * @param srcDisp the source displacement
20787 */
20788 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20789 public final void emitMOV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20790 int miStart = mi;
20791 // no group 1 to 4 prefix byte
20792 generateREXprefix(false, dstReg, srcIndex, srcBase);
20793 // single byte opcode
20794 setMachineCodes(mi++, (byte) 0x8B);
20795 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
20796 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20797 }
20798
20799 /**
20800 * Generate a register--register(indirect) MOV. That is,
20801 * <PRE>
20802 * dstReg := [srcBase]
20803 * </PRE>
20804 *
20805 * @param dstReg the destination register
20806 * @param srcBase the source base register
20807 */
20808 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20809 public final void emitMOV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20810 int miStart = mi;
20811 // no group 1 to 4 prefix byte
20812 generateREXprefix(false, dstReg, null, srcBase);
20813 // single byte opcode
20814 setMachineCodes(mi++, (byte) 0x8B);
20815 emitRegIndirectRegOperands(srcBase, dstReg);
20816 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
20817 }
20818
20819 /**
20820 * Generate a register(indirect)--register MOV. That is,
20821 * <PRE>
20822 * [dstBase] := (byte) srcReg
20823 * </PRE>
20824 *
20825 * @param dstBase the destination base
20826 * @param srcReg the source register
20827 */
20828 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20829 public final void emitMOV_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
20830 int miStart = mi;
20831 // no group 1 to 4 prefix byte
20832 generateREXprefix(false, srcReg, null, dstBase);
20833 // single byte opcode
20834 setMachineCodes(mi++, (byte) 0x88);
20835 emitRegIndirectRegOperands(dstBase, srcReg);
20836 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
20837 }
20838
20839 /**
20840 * Generate a register-offset--register MOV. That is,
20841 * <PRE>
20842 * [dstReg<<dstScale + dstDisp] := (byte) srcReg
20843 * </PRE>
20844 *
20845 * @param dstIndex the destination index register
20846 * @param dstScale the destination shift amount
20847 * @param dstDisp the destination displacement
20848 * @param srcReg the source register
20849 */
20850 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
20851 public final void emitMOV_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20852 int miStart = mi;
20853 // no group 1 to 4 prefix byte
20854 generateREXprefix(false, srcReg, dstIndex, null);
20855 // single byte opcode
20856 setMachineCodes(mi++, (byte) 0x88);
20857 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
20858 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
20859 }
20860
20861 /**
20862 * Generate a absolute--register MOV. That is,
20863 * <PRE>
20864 * [dstDisp] := (byte) srcReg
20865 * </PRE>
20866 *
20867 * @param dstDisp the destination address
20868 * @param srcReg the source register
20869 */
20870 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
20871 public final void emitMOV_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
20872 int miStart = mi;
20873 // no group 1 to 4 prefix byte
20874 generateREXprefix(false, srcReg, null, null);
20875 // single byte opcode
20876 setMachineCodes(mi++, (byte) 0x88);
20877 emitAbsRegOperands(dstDisp, srcReg);
20878 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
20879 }
20880
20881 /**
20882 * Generate a register-index--register MOV. That is,
20883 * <PRE>
20884 * [dstBase + dstIndex<<dstScale + dstDisp] := (byte) srcReg
20885 * </PRE>
20886 *
20887 * @param dstBase the base register
20888 * @param dstIndex the destination index register
20889 * @param dstScale the destination shift amount
20890 * @param dstDisp the destination displacement
20891 * @param srcReg the source register
20892 */
20893 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
20894 public final void emitMOV_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20895 int miStart = mi;
20896 // no group 1 to 4 prefix byte
20897 generateREXprefix(false, srcReg, dstIndex, dstBase);
20898 // single byte opcode
20899 setMachineCodes(mi++, (byte) 0x88);
20900 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
20901 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
20902 }
20903
20904 /**
20905 * Generate a register-displacement--register MOV. That is,
20906 * <PRE>
20907 * [dstBase + dstDisp] := (byte) srcReg
20908 * </PRE>
20909 *
20910 * @param dstBase the base register
20911 * @param dstDisp the destination displacement
20912 * @param srcReg the source register
20913 */
20914 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
20915 public final void emitMOV_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
20916 int miStart = mi;
20917 // no group 1 to 4 prefix byte
20918 generateREXprefix(false, srcReg, null, dstBase);
20919 // single byte opcode
20920 setMachineCodes(mi++, (byte) 0x88);
20921 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
20922 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
20923 }
20924
20925 /**
20926 * Generate a register--register MOV. That is,
20927 * <PRE>
20928 * dstReg := (byte) srcReg
20929 * </PRE>
20930 *
20931 * @param dstReg the destination register
20932 * @param srcReg the source register
20933 */
20934 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20935 public final void emitMOV_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
20936 int miStart = mi;
20937 // no group 1 to 4 prefix byte
20938 generateREXprefix(false, srcReg, null, dstReg);
20939 // single byte opcode
20940 setMachineCodes(mi++, (byte) 0x88);
20941 emitRegRegOperands(dstReg, srcReg);
20942 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
20943 }
20944
20945 /**
20946 * Generate a register--register-displacement MOV. That is,
20947 * <PRE>
20948 * dstReg := (byte) [srcReg + srcDisp]
20949 * </PRE>
20950 *
20951 * @param dstReg the destination register
20952 * @param srcBase the source register
20953 * @param srcDisp the source displacement
20954 */
20955 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20956 public final void emitMOV_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
20957 int miStart = mi;
20958 // no group 1 to 4 prefix byte
20959 generateREXprefix(false, dstReg, null, srcBase);
20960 // single byte opcode
20961 setMachineCodes(mi++, (byte) 0x8A);
20962 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
20963 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
20964 }
20965
20966 /**
20967 * Generate a register--register-offset MOV. That is,
20968 * <PRE>
20969 * dstReg := (byte) [srcIndex<<srcScale + srcDisp]
20970 * </PRE>
20971 *
20972 * @param dstReg the destination register
20973 * @param srcIndex the source index register
20974 * @param srcScale the source shift amount
20975 * @param srcDisp the source displacement
20976 */
20977 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20978 public final void emitMOV_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20979 int miStart = mi;
20980 // no group 1 to 4 prefix byte
20981 generateREXprefix(false, dstReg, srcIndex, null);
20982 // single byte opcode
20983 setMachineCodes(mi++, (byte) 0x8A);
20984 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
20985 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
20986 }
20987
20988 /**
20989 * Generate a register--register-offset MOV. That is,
20990 * <PRE>
20991 * dstReg := (byte) [srcDisp]
20992 * </PRE>
20993 *
20994 * @param dstReg the destination register
20995 * @param srcDisp the source displacement
20996 */
20997 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20998 public final void emitMOV_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
20999 int miStart = mi;
21000 // no group 1 to 4 prefix byte
21001 generateREXprefix(false, dstReg, null, null);
21002 // single byte opcode
21003 setMachineCodes(mi++, (byte) 0x8A);
21004 emitAbsRegOperands(srcDisp, dstReg);
21005 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21006 }
21007
21008 /**
21009 * Generate a register--register-offset MOV. That is,
21010 * <PRE>
21011 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp]
21012 * </PRE>
21013 *
21014 * @param dstReg the destination register
21015 * @param srcBase the source base register
21016 * @param srcIndex the source index register
21017 * @param srcScale the source shift amount
21018 * @param srcDisp the source displacement
21019 */
21020 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21021 public final void emitMOV_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21022 int miStart = mi;
21023 // no group 1 to 4 prefix byte
21024 generateREXprefix(false, dstReg, srcIndex, srcBase);
21025 // single byte opcode
21026 setMachineCodes(mi++, (byte) 0x8A);
21027 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21028 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21029 }
21030
21031 /**
21032 * Generate a register--register(indirect) MOV. That is,
21033 * <PRE>
21034 * dstReg := (byte) [srcBase]
21035 * </PRE>
21036 *
21037 * @param dstReg the destination register
21038 * @param srcBase the source base register
21039 */
21040 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21041 public final void emitMOV_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
21042 int miStart = mi;
21043 // no group 1 to 4 prefix byte
21044 generateREXprefix(false, dstReg, null, srcBase);
21045 // single byte opcode
21046 setMachineCodes(mi++, (byte) 0x8A);
21047 emitRegIndirectRegOperands(srcBase, dstReg);
21048 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21049 }
21050
21051 /**
21052 * Generate a register(indirect)--register MOV. That is,
21053 * <PRE>
21054 * [dstBase] := (word) srcReg
21055 * </PRE>
21056 *
21057 * @param dstBase the destination base
21058 * @param srcReg the source register
21059 */
21060 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21061 public final void emitMOV_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
21062 int miStart = mi;
21063 setMachineCodes(mi++, (byte) 0x66);
21064 generateREXprefix(false, srcReg, null, dstBase);
21065 // single byte opcode
21066 setMachineCodes(mi++, (byte) 0x89);
21067 emitRegIndirectRegOperands(dstBase, srcReg);
21068 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
21069 }
21070
21071 /**
21072 * Generate a register-offset--register MOV. That is,
21073 * <PRE>
21074 * [dstReg<<dstScale + dstDisp] := (word) srcReg
21075 * </PRE>
21076 *
21077 * @param dstIndex the destination index register
21078 * @param dstScale the destination shift amount
21079 * @param dstDisp the destination displacement
21080 * @param srcReg the source register
21081 */
21082 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
21083 public final void emitMOV_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21084 int miStart = mi;
21085 setMachineCodes(mi++, (byte) 0x66);
21086 generateREXprefix(false, srcReg, dstIndex, null);
21087 // single byte opcode
21088 setMachineCodes(mi++, (byte) 0x89);
21089 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
21090 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
21091 }
21092
21093 /**
21094 * Generate a absolute--register MOV. That is,
21095 * <PRE>
21096 * [dstDisp] := (word) srcReg
21097 * </PRE>
21098 *
21099 * @param dstDisp the destination address
21100 * @param srcReg the source register
21101 */
21102 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
21103 public final void emitMOV_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
21104 int miStart = mi;
21105 setMachineCodes(mi++, (byte) 0x66);
21106 generateREXprefix(false, srcReg, null, null);
21107 // single byte opcode
21108 setMachineCodes(mi++, (byte) 0x89);
21109 emitAbsRegOperands(dstDisp, srcReg);
21110 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
21111 }
21112
21113 /**
21114 * Generate a register-index--register MOV. That is,
21115 * <PRE>
21116 * [dstBase + dstIndex<<dstScale + dstDisp] := (word) srcReg
21117 * </PRE>
21118 *
21119 * @param dstBase the base register
21120 * @param dstIndex the destination index register
21121 * @param dstScale the destination shift amount
21122 * @param dstDisp the destination displacement
21123 * @param srcReg the source register
21124 */
21125 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
21126 public final void emitMOV_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21127 int miStart = mi;
21128 setMachineCodes(mi++, (byte) 0x66);
21129 generateREXprefix(false, srcReg, dstIndex, dstBase);
21130 // single byte opcode
21131 setMachineCodes(mi++, (byte) 0x89);
21132 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
21133 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
21134 }
21135
21136 /**
21137 * Generate a register-displacement--register MOV. That is,
21138 * <PRE>
21139 * [dstBase + dstDisp] := (word) srcReg
21140 * </PRE>
21141 *
21142 * @param dstBase the base register
21143 * @param dstDisp the destination displacement
21144 * @param srcReg the source register
21145 */
21146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
21147 public final void emitMOV_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
21148 int miStart = mi;
21149 setMachineCodes(mi++, (byte) 0x66);
21150 generateREXprefix(false, srcReg, null, dstBase);
21151 // single byte opcode
21152 setMachineCodes(mi++, (byte) 0x89);
21153 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
21154 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
21155 }
21156
21157 /**
21158 * Generate a register--register MOV. That is,
21159 * <PRE>
21160 * dstReg := (word) srcReg
21161 * </PRE>
21162 *
21163 * @param dstReg the destination register
21164 * @param srcReg the source register
21165 */
21166 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21167 public final void emitMOV_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
21168 int miStart = mi;
21169 setMachineCodes(mi++, (byte) 0x66);
21170 generateREXprefix(false, srcReg, null, dstReg);
21171 // single byte opcode
21172 setMachineCodes(mi++, (byte) 0x89);
21173 emitRegRegOperands(dstReg, srcReg);
21174 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
21175 }
21176
21177 /**
21178 * Generate a register--register-displacement MOV. That is,
21179 * <PRE>
21180 * dstReg := (word) [srcReg + srcDisp]
21181 * </PRE>
21182 *
21183 * @param dstReg the destination register
21184 * @param srcBase the source register
21185 * @param srcDisp the source displacement
21186 */
21187 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21188 public final void emitMOV_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
21189 int miStart = mi;
21190 setMachineCodes(mi++, (byte) 0x66);
21191 generateREXprefix(false, dstReg, null, srcBase);
21192 // single byte opcode
21193 setMachineCodes(mi++, (byte) 0x8B);
21194 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
21195 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
21196 }
21197
21198 /**
21199 * Generate a register--register-offset MOV. That is,
21200 * <PRE>
21201 * dstReg := (word) [srcIndex<<srcScale + srcDisp]
21202 * </PRE>
21203 *
21204 * @param dstReg the destination register
21205 * @param srcIndex the source index register
21206 * @param srcScale the source shift amount
21207 * @param srcDisp the source displacement
21208 */
21209 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21210 public final void emitMOV_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
21211 int miStart = mi;
21212 setMachineCodes(mi++, (byte) 0x66);
21213 generateREXprefix(false, dstReg, srcIndex, null);
21214 // single byte opcode
21215 setMachineCodes(mi++, (byte) 0x8B);
21216 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
21217 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
21218 }
21219
21220 /**
21221 * Generate a register--register-offset MOV. That is,
21222 * <PRE>
21223 * dstReg := (word) [srcDisp]
21224 * </PRE>
21225 *
21226 * @param dstReg the destination register
21227 * @param srcDisp the source displacement
21228 */
21229 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21230 public final void emitMOV_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
21231 int miStart = mi;
21232 setMachineCodes(mi++, (byte) 0x66);
21233 generateREXprefix(false, dstReg, null, null);
21234 // single byte opcode
21235 setMachineCodes(mi++, (byte) 0x8B);
21236 emitAbsRegOperands(srcDisp, dstReg);
21237 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21238 }
21239
21240 /**
21241 * Generate a register--register-offset MOV. That is,
21242 * <PRE>
21243 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp]
21244 * </PRE>
21245 *
21246 * @param dstReg the destination register
21247 * @param srcBase the source base register
21248 * @param srcIndex the source index register
21249 * @param srcScale the source shift amount
21250 * @param srcDisp the source displacement
21251 */
21252 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21253 public final void emitMOV_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21254 int miStart = mi;
21255 setMachineCodes(mi++, (byte) 0x66);
21256 generateREXprefix(false, dstReg, srcIndex, srcBase);
21257 // single byte opcode
21258 setMachineCodes(mi++, (byte) 0x8B);
21259 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21260 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21261 }
21262
21263 /**
21264 * Generate a register--register(indirect) MOV. That is,
21265 * <PRE>
21266 * dstReg := (word) [srcBase]
21267 * </PRE>
21268 *
21269 * @param dstReg the destination register
21270 * @param srcBase the source base register
21271 */
21272 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21273 public final void emitMOV_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
21274 int miStart = mi;
21275 setMachineCodes(mi++, (byte) 0x66);
21276 generateREXprefix(false, dstReg, null, srcBase);
21277 // single byte opcode
21278 setMachineCodes(mi++, (byte) 0x8B);
21279 emitRegIndirectRegOperands(srcBase, dstReg);
21280 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21281 }
21282
21283 /**
21284 * Generate a register(indirect)--register MOV. That is,
21285 * <PRE>
21286 * [dstBase] := (quad) srcReg
21287 * </PRE>
21288 *
21289 * @param dstBase the destination base
21290 * @param srcReg the source register
21291 */
21292 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21293 public final void emitMOV_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
21294 int miStart = mi;
21295 // no group 1 to 4 prefix byte
21296 generateREXprefix(true, srcReg, null, dstBase);
21297 // single byte opcode
21298 setMachineCodes(mi++, (byte) 0x89);
21299 emitRegIndirectRegOperands(dstBase, srcReg);
21300 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
21301 }
21302
21303 /**
21304 * Generate a register-offset--register MOV. That is,
21305 * <PRE>
21306 * [dstReg<<dstScale + dstDisp] := (quad) srcReg
21307 * </PRE>
21308 *
21309 * @param dstIndex the destination index register
21310 * @param dstScale the destination shift amount
21311 * @param dstDisp the destination displacement
21312 * @param srcReg the source register
21313 */
21314 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
21315 public final void emitMOV_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21316 int miStart = mi;
21317 // no group 1 to 4 prefix byte
21318 generateREXprefix(true, srcReg, dstIndex, null);
21319 // single byte opcode
21320 setMachineCodes(mi++, (byte) 0x89);
21321 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
21322 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
21323 }
21324
21325 /**
21326 * Generate a absolute--register MOV. That is,
21327 * <PRE>
21328 * [dstDisp] := (quad) srcReg
21329 * </PRE>
21330 *
21331 * @param dstDisp the destination address
21332 * @param srcReg the source register
21333 */
21334 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
21335 public final void emitMOV_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
21336 int miStart = mi;
21337 // no group 1 to 4 prefix byte
21338 generateREXprefix(true, srcReg, null, null);
21339 // single byte opcode
21340 setMachineCodes(mi++, (byte) 0x89);
21341 emitAbsRegOperands(dstDisp, srcReg);
21342 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
21343 }
21344
21345 /**
21346 * Generate a register-index--register MOV. That is,
21347 * <PRE>
21348 * [dstBase + dstIndex<<dstScale + dstDisp] := (quad) srcReg
21349 * </PRE>
21350 *
21351 * @param dstBase the base register
21352 * @param dstIndex the destination index register
21353 * @param dstScale the destination shift amount
21354 * @param dstDisp the destination displacement
21355 * @param srcReg the source register
21356 */
21357 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
21358 public final void emitMOV_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21359 int miStart = mi;
21360 // no group 1 to 4 prefix byte
21361 generateREXprefix(true, srcReg, dstIndex, dstBase);
21362 // single byte opcode
21363 setMachineCodes(mi++, (byte) 0x89);
21364 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
21365 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
21366 }
21367
21368 /**
21369 * Generate a register-displacement--register MOV. That is,
21370 * <PRE>
21371 * [dstBase + dstDisp] := (quad) srcReg
21372 * </PRE>
21373 *
21374 * @param dstBase the base register
21375 * @param dstDisp the destination displacement
21376 * @param srcReg the source register
21377 */
21378 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
21379 public final void emitMOV_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
21380 int miStart = mi;
21381 // no group 1 to 4 prefix byte
21382 generateREXprefix(true, srcReg, null, dstBase);
21383 // single byte opcode
21384 setMachineCodes(mi++, (byte) 0x89);
21385 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
21386 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
21387 }
21388
21389 /**
21390 * Generate a register--register MOV. That is,
21391 * <PRE>
21392 * dstReg := (quad) srcReg
21393 * </PRE>
21394 *
21395 * @param dstReg the destination register
21396 * @param srcReg the source register
21397 */
21398 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21399 public final void emitMOV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
21400 int miStart = mi;
21401 // no group 1 to 4 prefix byte
21402 generateREXprefix(true, srcReg, null, dstReg);
21403 // single byte opcode
21404 setMachineCodes(mi++, (byte) 0x89);
21405 emitRegRegOperands(dstReg, srcReg);
21406 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
21407 }
21408
21409 /**
21410 * Generate a register--register-displacement MOV. That is,
21411 * <PRE>
21412 * dstReg := (quad) [srcReg + srcDisp]
21413 * </PRE>
21414 *
21415 * @param dstReg the destination register
21416 * @param srcBase the source register
21417 * @param srcDisp the source displacement
21418 */
21419 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21420 public final void emitMOV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
21421 int miStart = mi;
21422 // no group 1 to 4 prefix byte
21423 generateREXprefix(true, dstReg, null, srcBase);
21424 // single byte opcode
21425 setMachineCodes(mi++, (byte) 0x8B);
21426 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
21427 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
21428 }
21429
21430 /**
21431 * Generate a register--register-offset MOV. That is,
21432 * <PRE>
21433 * dstReg := (quad) [srcIndex<<srcScale + srcDisp]
21434 * </PRE>
21435 *
21436 * @param dstReg the destination register
21437 * @param srcIndex the source index register
21438 * @param srcScale the source shift amount
21439 * @param srcDisp the source displacement
21440 */
21441 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21442 public final void emitMOV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
21443 int miStart = mi;
21444 // no group 1 to 4 prefix byte
21445 generateREXprefix(true, dstReg, srcIndex, null);
21446 // single byte opcode
21447 setMachineCodes(mi++, (byte) 0x8B);
21448 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
21449 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
21450 }
21451
21452 /**
21453 * Generate a register--register-offset MOV. That is,
21454 * <PRE>
21455 * dstReg := (quad) [srcDisp]
21456 * </PRE>
21457 *
21458 * @param dstReg the destination register
21459 * @param srcDisp the source displacement
21460 */
21461 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21462 public final void emitMOV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
21463 int miStart = mi;
21464 // no group 1 to 4 prefix byte
21465 generateREXprefix(true, dstReg, null, null);
21466 // single byte opcode
21467 setMachineCodes(mi++, (byte) 0x8B);
21468 emitAbsRegOperands(srcDisp, dstReg);
21469 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21470 }
21471
21472 /**
21473 * Generate a register--register-offset MOV. That is,
21474 * <PRE>
21475 * dstReg := (quad) [srcBase + srcIndex<<srcScale + srcDisp]
21476 * </PRE>
21477 *
21478 * @param dstReg the destination register
21479 * @param srcBase the source base register
21480 * @param srcIndex the source index register
21481 * @param srcScale the source shift amount
21482 * @param srcDisp the source displacement
21483 */
21484 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21485 public final void emitMOV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21486 int miStart = mi;
21487 // no group 1 to 4 prefix byte
21488 generateREXprefix(true, dstReg, srcIndex, srcBase);
21489 // single byte opcode
21490 setMachineCodes(mi++, (byte) 0x8B);
21491 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21492 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21493 }
21494
21495 /**
21496 * Generate a register--register(indirect) MOV. That is,
21497 * <PRE>
21498 * dstReg := (quad) [srcBase]
21499 * </PRE>
21500 *
21501 * @param dstReg the destination register
21502 * @param srcBase the source base register
21503 */
21504 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21505 public final void emitMOV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
21506 int miStart = mi;
21507 // no group 1 to 4 prefix byte
21508 generateREXprefix(true, dstReg, null, srcBase);
21509 // single byte opcode
21510 setMachineCodes(mi++, (byte) 0x8B);
21511 emitRegIndirectRegOperands(srcBase, dstReg);
21512 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21513 }
21514
21515 /**
21516 * Generate a register-indirect--immediate MOV. That is,
21517 * <PRE>
21518 * [dstBase] MOV = imm
21519 * </PRE>
21520 *
21521 * @param dstBase the destination base register
21522 * @param imm immediate
21523 */
21524 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21525 public final void emitMOV_RegInd_Imm_Byte(GPR dstBase, int imm) {
21526 int miStart = mi;
21527 // no prefix byte
21528 generateREXprefix(false, null, null, dstBase);
21529 setMachineCodes(mi++, (byte) 0xC6);
21530 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21531 emitImm8(imm);
21532 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21533 }
21534
21535 /**
21536 * Generate a register-displacement--immediate MOV. That is,
21537 * <PRE>
21538 * [dstBase + dstDisp] MOV = imm
21539 * </PRE>
21540 *
21541 * @param dstBase the destination base register
21542 * @param dstDisp the destination displacement
21543 * @param imm immediate
21544 */
21545 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21546 public final void emitMOV_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
21547 int miStart = mi;
21548 // no prefix byte
21549 generateREXprefix(false, null, null, dstBase);
21550 setMachineCodes(mi++, (byte) 0xC6);
21551 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21552 emitImm8(imm);
21553 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21554 }
21555
21556 /**
21557 * Generate a register-index--immediate MOV. That is,
21558 * <PRE>
21559 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21560 * </PRE>
21561 *
21562 * @param dstBase the destination base register
21563 * @param dstIndex the destination index register
21564 * @param dstScale the destination shift amount
21565 * @param dstDisp the destination displacement
21566 * @param imm immediate
21567 */
21568 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21569 public final void emitMOV_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21570 int miStart = mi;
21571 // no prefix byte
21572 generateREXprefix(false, null, dstIndex, dstBase);
21573 setMachineCodes(mi++, (byte) 0xC6);
21574 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21575 emitImm8(imm);
21576 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21577 }
21578
21579 /**
21580 * Generate a register-index--immediate MOV. That is,
21581 * <PRE>
21582 * [dstIndex<<scale + dstDisp] MOV = imm
21583 * </PRE>
21584 *
21585 * @param dstIndex the destination index register
21586 * @param dstScale the destination shift amount
21587 * @param dstDisp the destination displacement
21588 * @param imm immediate
21589 */
21590 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21591 public final void emitMOV_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21592 int miStart = mi;
21593 // no prefix byte
21594 generateREXprefix(false, null, dstIndex, null);
21595 setMachineCodes(mi++, (byte) 0xC6);
21596 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21597 emitImm8(imm);
21598 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21599 }
21600
21601 /**
21602 * Generate an absolute MOV. That is,
21603 * <PRE>
21604 * [dstDisp] MOV = imm
21605 * </PRE>
21606 *
21607 * @param dstDisp the destination displacement
21608 * @param imm immediate
21609 */
21610 public final void emitMOV_Abs_Imm_Byte(Address dstDisp, int imm) {
21611 int miStart = mi;
21612 // no prefix byte
21613 generateREXprefix(false, null, null, null);
21614 setMachineCodes(mi++, (byte) 0xC6);
21615 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21616 emitImm8(imm);
21617 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21618 }
21619
21620 /**
21621 * Generate a register-indirect--immediate MOV. That is,
21622 * <PRE>
21623 * [dstBase] MOV = imm
21624 * </PRE>
21625 *
21626 * @param dstBase the destination base register
21627 * @param imm immediate
21628 */
21629 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21630 public final void emitMOV_RegInd_Imm_Word(GPR dstBase, int imm) {
21631 int miStart = mi;
21632 setMachineCodes(mi++, (byte) 0x66);
21633 generateREXprefix(false, null, null, dstBase);
21634 setMachineCodes(mi++, (byte) 0xC7);
21635 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21636 emitImm16(imm);
21637 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21638 }
21639
21640 /**
21641 * Generate a register-displacement--immediate MOV. That is,
21642 * <PRE>
21643 * [dstBase + dstDisp] MOV = imm
21644 * </PRE>
21645 *
21646 * @param dstBase the destination base register
21647 * @param dstDisp the destination displacement
21648 * @param imm immediate
21649 */
21650 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21651 public final void emitMOV_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
21652 int miStart = mi;
21653 setMachineCodes(mi++, (byte) 0x66);
21654 generateREXprefix(false, null, null, dstBase);
21655 setMachineCodes(mi++, (byte) 0xC7);
21656 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21657 emitImm16(imm);
21658 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21659 }
21660
21661 /**
21662 * Generate a register-index--immediate MOV. That is,
21663 * <PRE>
21664 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21665 * </PRE>
21666 *
21667 * @param dstBase the destination base register
21668 * @param dstIndex the destination index register
21669 * @param dstScale the destination shift amount
21670 * @param dstDisp the destination displacement
21671 * @param imm immediate
21672 */
21673 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21674 public final void emitMOV_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21675 int miStart = mi;
21676 setMachineCodes(mi++, (byte) 0x66);
21677 generateREXprefix(false, null, dstIndex, dstBase);
21678 setMachineCodes(mi++, (byte) 0xC7);
21679 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21680 emitImm16(imm);
21681 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21682 }
21683
21684 /**
21685 * Generate a register-index--immediate MOV. That is,
21686 * <PRE>
21687 * [dstIndex<<scale + dstDisp] MOV = imm
21688 * </PRE>
21689 *
21690 * @param dstIndex the destination index register
21691 * @param dstScale the destination shift amount
21692 * @param dstDisp the destination displacement
21693 * @param imm immediate
21694 */
21695 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21696 public final void emitMOV_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21697 int miStart = mi;
21698 setMachineCodes(mi++, (byte) 0x66);
21699 generateREXprefix(false, null, dstIndex, null);
21700 setMachineCodes(mi++, (byte) 0xC7);
21701 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21702 emitImm16(imm);
21703 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21704 }
21705
21706 /**
21707 * Generate an absolute MOV. That is,
21708 * <PRE>
21709 * [dstDisp] MOV = imm
21710 * </PRE>
21711 *
21712 * @param dstDisp the destination displacement
21713 * @param imm immediate
21714 */
21715 public final void emitMOV_Abs_Imm_Word(Address dstDisp, int imm) {
21716 int miStart = mi;
21717 setMachineCodes(mi++, (byte) 0x66);
21718 generateREXprefix(false, null, null, null);
21719 setMachineCodes(mi++, (byte) 0xC7);
21720 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21721 emitImm16(imm);
21722 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21723 }
21724
21725 /**
21726 * Generate a register-indirect--immediate MOV. That is,
21727 * <PRE>
21728 * [dstBase] MOV = imm
21729 * </PRE>
21730 *
21731 * @param dstBase the destination base register
21732 * @param imm immediate
21733 */
21734 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21735 public final void emitMOV_RegInd_Imm(GPR dstBase, int imm) {
21736 int miStart = mi;
21737 // no prefix byte
21738 generateREXprefix(false, null, null, dstBase);
21739 setMachineCodes(mi++, (byte) 0xC7);
21740 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21741 emitImm32(imm);
21742 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21743 }
21744
21745 /**
21746 * Generate a register-displacement--immediate MOV. That is,
21747 * <PRE>
21748 * [dstBase + dstDisp] MOV = imm
21749 * </PRE>
21750 *
21751 * @param dstBase the destination base register
21752 * @param dstDisp the destination displacement
21753 * @param imm immediate
21754 */
21755 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21756 public final void emitMOV_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
21757 int miStart = mi;
21758 // no prefix byte
21759 generateREXprefix(false, null, null, dstBase);
21760 setMachineCodes(mi++, (byte) 0xC7);
21761 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21762 emitImm32(imm);
21763 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21764 }
21765
21766 /**
21767 * Generate a register-index--immediate MOV. That is,
21768 * <PRE>
21769 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21770 * </PRE>
21771 *
21772 * @param dstBase the destination base register
21773 * @param dstIndex the destination index register
21774 * @param dstScale the destination shift amount
21775 * @param dstDisp the destination displacement
21776 * @param imm immediate
21777 */
21778 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21779 public final void emitMOV_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21780 int miStart = mi;
21781 // no prefix byte
21782 generateREXprefix(false, null, dstIndex, dstBase);
21783 setMachineCodes(mi++, (byte) 0xC7);
21784 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21785 emitImm32(imm);
21786 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21787 }
21788
21789 /**
21790 * Generate a register-index--immediate MOV. That is,
21791 * <PRE>
21792 * [dstIndex<<scale + dstDisp] MOV = imm
21793 * </PRE>
21794 *
21795 * @param dstIndex the destination index register
21796 * @param dstScale the destination shift amount
21797 * @param dstDisp the destination displacement
21798 * @param imm immediate
21799 */
21800 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21801 public final void emitMOV_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21802 int miStart = mi;
21803 // no prefix byte
21804 generateREXprefix(false, null, dstIndex, null);
21805 setMachineCodes(mi++, (byte) 0xC7);
21806 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21807 emitImm32(imm);
21808 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21809 }
21810
21811 /**
21812 * Generate an absolute MOV. That is,
21813 * <PRE>
21814 * [dstDisp] MOV = imm
21815 * </PRE>
21816 *
21817 * @param dstDisp the destination displacement
21818 * @param imm immediate
21819 */
21820 public final void emitMOV_Abs_Imm(Address dstDisp, int imm) {
21821 int miStart = mi;
21822 // no prefix byte
21823 generateREXprefix(false, null, null, null);
21824 setMachineCodes(mi++, (byte) 0xC7);
21825 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21826 emitImm32(imm);
21827 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21828 }
21829
21830 /**
21831 * Generate a register-indirect--immediate MOV. That is,
21832 * <PRE>
21833 * [dstBase] MOV = imm
21834 * </PRE>
21835 *
21836 * @param dstBase the destination base register
21837 * @param imm immediate
21838 */
21839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21840 public final void emitMOV_RegInd_Imm_Quad(GPR dstBase, int imm) {
21841 int miStart = mi;
21842 // no prefix byte
21843 generateREXprefix(true, null, null, dstBase);
21844 setMachineCodes(mi++, (byte) 0xC7);
21845 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21846 emitImm32(imm);
21847 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21848 }
21849
21850 /**
21851 * Generate a register-displacement--immediate MOV. That is,
21852 * <PRE>
21853 * [dstBase + dstDisp] MOV = imm
21854 * </PRE>
21855 *
21856 * @param dstBase the destination base register
21857 * @param dstDisp the destination displacement
21858 * @param imm immediate
21859 */
21860 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21861 public final void emitMOV_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
21862 int miStart = mi;
21863 // no prefix byte
21864 generateREXprefix(true, null, null, dstBase);
21865 setMachineCodes(mi++, (byte) 0xC7);
21866 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21867 emitImm32(imm);
21868 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21869 }
21870
21871 /**
21872 * Generate a register-index--immediate MOV. That is,
21873 * <PRE>
21874 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21875 * </PRE>
21876 *
21877 * @param dstBase the destination base register
21878 * @param dstIndex the destination index register
21879 * @param dstScale the destination shift amount
21880 * @param dstDisp the destination displacement
21881 * @param imm immediate
21882 */
21883 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21884 public final void emitMOV_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21885 int miStart = mi;
21886 // no prefix byte
21887 generateREXprefix(true, null, dstIndex, dstBase);
21888 setMachineCodes(mi++, (byte) 0xC7);
21889 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21890 emitImm32(imm);
21891 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21892 }
21893
21894 /**
21895 * Generate a register-index--immediate MOV. That is,
21896 * <PRE>
21897 * [dstIndex<<scale + dstDisp] MOV = imm
21898 * </PRE>
21899 *
21900 * @param dstIndex the destination index register
21901 * @param dstScale the destination shift amount
21902 * @param dstDisp the destination displacement
21903 * @param imm immediate
21904 */
21905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21906 public final void emitMOV_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21907 int miStart = mi;
21908 // no prefix byte
21909 generateREXprefix(true, null, dstIndex, null);
21910 setMachineCodes(mi++, (byte) 0xC7);
21911 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21912 emitImm32(imm);
21913 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21914 }
21915
21916 /**
21917 * Generate an absolute MOV. That is,
21918 * <PRE>
21919 * [dstDisp] MOV = imm
21920 * </PRE>
21921 *
21922 * @param dstDisp the destination displacement
21923 * @param imm immediate