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org.jikesrvm.compilers.opt.mir2mc.ia32
Class AssemblerOpt

java.lang.Object
  extended by org.jikesrvm.compilers.common.assembler.AbstractAssembler
      extended by org.jikesrvm.compilers.common.assembler.ia32.Assembler
          extended by org.jikesrvm.ArchitectureSpecific.Assembler
              extended by org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase
                  extended by org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerOpt
All Implemented Interfaces:
AssemblerConstants, Operators, PhysicalRegisterConstants, Constants, HeapLayoutConstants, RegisterConstants, ThinLockConstants, TIBLayoutConstants, SizeConstants
Direct Known Subclasses:
ArchitectureSpecificOpt.AssemblerOpt
public abstract class AssemblerOpt
extends AssemblerBase

This class is the automatically-generated assembler for the optimizing compiler. It consists of methods that understand the possible operand combinations of each instruction type, and how to translate those operands to calls to the Assember low-level emit method It is generated by GenerateAssembler.java

Nested Class Summary
 
Nested classes/interfaces inherited from interface org.jikesrvm.ia32.RegisterConstants
RegisterConstants.FloatingPointMachineRegister, RegisterConstants.FPR, RegisterConstants.GPR, RegisterConstants.MachineRegister, RegisterConstants.MM, RegisterConstants.XMM
 
Field Summary
private  int instructionCount
          The number of instructions emitted so far
 
Fields inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler
forwardRefs, lister, mi
 
Fields inherited from interface org.jikesrvm.compilers.opt.ir.Operators
ADDR_2INT, ADDR_2INT_opcode, ADDR_2LONG, ADDR_2LONG_opcode, ADDRESS_CONSTANT, ADDRESS_CONSTANT_opcode, ADVISE_ESP, ADVISE_ESP_opcode, ARCH_INDEPENDENT_END_opcode, ARRAYLENGTH, ARRAYLENGTH_opcode, ATHROW, ATHROW_opcode, ATTEMPT_ADDR, ATTEMPT_ADDR_opcode, ATTEMPT_INT, ATTEMPT_INT_opcode, ATTEMPT_LONG, ATTEMPT_LONG_opcode, BBEND, BBEND_opcode, BOOLEAN_CMP_ADDR, BOOLEAN_CMP_ADDR_opcode, BOOLEAN_CMP_DOUBLE, BOOLEAN_CMP_DOUBLE_opcode, BOOLEAN_CMP_FLOAT, BOOLEAN_CMP_FLOAT_opcode, BOOLEAN_CMP_INT, BOOLEAN_CMP_INT_opcode, BOOLEAN_CMP_LONG, BOOLEAN_CMP_LONG_opcode, BOOLEAN_NOT, BOOLEAN_NOT_opcode, BOUNDS_CHECK, BOUNDS_CHECK_opcode, BRANCH_TARGET, BRANCH_TARGET_opcode, BYTE_ALOAD, BYTE_ALOAD_opcode, BYTE_ASTORE, BYTE_ASTORE_opcode, BYTE_LOAD, BYTE_LOAD_opcode, BYTE_STORE, BYTE_STORE_opcode, CALL, CALL_opcode, CALL_SAVE_VOLATILE, CALL_SAVE_VOLATILE_opcode, CHECKCAST, CHECKCAST_NOTNULL, CHECKCAST_NOTNULL_opcode, CHECKCAST_opcode, CHECKCAST_UNRESOLVED, CHECKCAST_UNRESOLVED_opcode, CLEAR_FLOATING_POINT_STATE, CLEAR_FLOATING_POINT_STATE_opcode, CMP_CMOV, CMP_CMOV_opcode, CMP_FCMOV, CMP_FCMOV_opcode, DOUBLE_2FLOAT, DOUBLE_2FLOAT_opcode, DOUBLE_2INT, DOUBLE_2INT_opcode, DOUBLE_2LONG, DOUBLE_2LONG_opcode, DOUBLE_ADD, DOUBLE_ADD_opcode, DOUBLE_ALOAD, DOUBLE_ALOAD_opcode, DOUBLE_AS_LONG_BITS, DOUBLE_AS_LONG_BITS_opcode, DOUBLE_ASTORE, DOUBLE_ASTORE_opcode, DOUBLE_CMPG, DOUBLE_CMPG_opcode, DOUBLE_CMPL, DOUBLE_CMPL_opcode, DOUBLE_COND_MOVE, DOUBLE_COND_MOVE_opcode, DOUBLE_DIV, DOUBLE_DIV_opcode, DOUBLE_IFCMP, DOUBLE_IFCMP_opcode, DOUBLE_LOAD, DOUBLE_LOAD_opcode, DOUBLE_MOVE, DOUBLE_MOVE_opcode, DOUBLE_MUL, DOUBLE_MUL_opcode, DOUBLE_NEG, DOUBLE_NEG_opcode, DOUBLE_REM, DOUBLE_REM_opcode, DOUBLE_SQRT, DOUBLE_SQRT_opcode, DOUBLE_STORE, DOUBLE_STORE_opcode, DOUBLE_SUB, DOUBLE_SUB_opcode, DUMMY_DEF, DUMMY_DEF_opcode, DUMMY_USE, DUMMY_USE_opcode, FCMP_CMOV, FCMP_CMOV_opcode, FCMP_FCMOV, FCMP_FCMOV_opcode, FLOAT_2DOUBLE, FLOAT_2DOUBLE_opcode, FLOAT_2INT, FLOAT_2INT_opcode, FLOAT_2LONG, FLOAT_2LONG_opcode, FLOAT_ADD, FLOAT_ADD_opcode, FLOAT_ALOAD, FLOAT_ALOAD_opcode, FLOAT_AS_INT_BITS, FLOAT_AS_INT_BITS_opcode, FLOAT_ASTORE, FLOAT_ASTORE_opcode, FLOAT_CMPG, FLOAT_CMPG_opcode, FLOAT_CMPL, FLOAT_CMPL_opcode, FLOAT_COND_MOVE, FLOAT_COND_MOVE_opcode, FLOAT_DIV, FLOAT_DIV_opcode, FLOAT_IFCMP, FLOAT_IFCMP_opcode, FLOAT_LOAD, FLOAT_LOAD_opcode, FLOAT_MOVE, FLOAT_MOVE_opcode, FLOAT_MUL, FLOAT_MUL_opcode, FLOAT_NEG, FLOAT_NEG_opcode, FLOAT_REM, FLOAT_REM_opcode, FLOAT_SQRT, FLOAT_SQRT_opcode, FLOAT_STORE, FLOAT_STORE_opcode, FLOAT_SUB, FLOAT_SUB_opcode, FP_ADD, FP_ADD_opcode, FP_DIV, FP_DIV_opcode, FP_MUL, FP_MUL_opcode, FP_NEG, FP_NEG_opcode, FP_REM, FP_REM_opcode, FP_SUB, FP_SUB_opcode, GET_ARRAY_ELEMENT_TIB_FROM_TIB, GET_ARRAY_ELEMENT_TIB_FROM_TIB_opcode, GET_CAUGHT_EXCEPTION, GET_CAUGHT_EXCEPTION_opcode, GET_CLASS_TIB, GET_CLASS_TIB_opcode, GET_CURRENT_PROCESSOR, GET_CURRENT_PROCESSOR_opcode, GET_DOES_IMPLEMENT_FROM_TIB, GET_DOES_IMPLEMENT_FROM_TIB_opcode, GET_OBJ_TIB, GET_OBJ_TIB_opcode, GET_SUPERCLASS_IDS_FROM_TIB, GET_SUPERCLASS_IDS_FROM_TIB_opcode, GET_TIME_BASE, GET_TIME_BASE_opcode, GET_TYPE_FROM_TIB, GET_TYPE_FROM_TIB_opcode, GETFIELD, GETFIELD_opcode, GETSTATIC, GETSTATIC_opcode, GOTO, GOTO_opcode, GUARD_COMBINE, GUARD_COMBINE_opcode, GUARD_COND_MOVE, GUARD_COND_MOVE_opcode, GUARD_MOVE, GUARD_MOVE_opcode, helper, IA32_ADC, IA32_ADC_opcode, IA32_ADD, IA32_ADD_opcode, IA32_ADDSD, IA32_ADDSD_opcode, IA32_ADDSS, IA32_ADDSS_opcode, IA32_AND, IA32_AND_opcode, IA32_ANDNPD, IA32_ANDNPD_opcode, IA32_ANDNPS, IA32_ANDNPS_opcode, IA32_ANDPD, IA32_ANDPD_opcode, IA32_ANDPS, IA32_ANDPS_opcode, IA32_BSWAP, IA32_BSWAP_opcode, IA32_BT, IA32_BT_opcode, IA32_BTC, IA32_BTC_opcode, IA32_BTR, IA32_BTR_opcode, IA32_BTS, IA32_BTS_opcode, IA32_CALL, IA32_CALL_opcode, IA32_CDO, IA32_CDO_opcode, IA32_CDQ, IA32_CDQ_opcode, IA32_CDQE, IA32_CDQE_opcode, IA32_CMOV, IA32_CMOV_opcode, IA32_CMP, IA32_CMP_opcode, IA32_CMPEQSD, IA32_CMPEQSD_opcode, IA32_CMPEQSS, IA32_CMPEQSS_opcode, IA32_CMPLESD, IA32_CMPLESD_opcode, IA32_CMPLESS, IA32_CMPLESS_opcode, IA32_CMPLTSD, IA32_CMPLTSD_opcode, IA32_CMPLTSS, IA32_CMPLTSS_opcode, IA32_CMPNESD, IA32_CMPNESD_opcode, IA32_CMPNESS, IA32_CMPNESS_opcode, IA32_CMPNLESD, IA32_CMPNLESD_opcode, IA32_CMPNLESS, IA32_CMPNLESS_opcode, IA32_CMPNLTSD, IA32_CMPNLTSD_opcode, IA32_CMPNLTSS, IA32_CMPNLTSS_opcode, IA32_CMPORDSD, IA32_CMPORDSD_opcode, IA32_CMPORDSS, IA32_CMPORDSS_opcode, IA32_CMPUNORDSD, IA32_CMPUNORDSD_opcode, IA32_CMPUNORDSS, IA32_CMPUNORDSS_opcode, IA32_CMPXCHG, IA32_CMPXCHG_opcode, IA32_CMPXCHG8B, IA32_CMPXCHG8B_opcode, IA32_CVTSD2SI, IA32_CVTSD2SI_opcode, IA32_CVTSD2SIQ, IA32_CVTSD2SIQ_opcode, IA32_CVTSD2SS, IA32_CVTSD2SS_opcode, IA32_CVTSI2SD, IA32_CVTSI2SD_opcode, IA32_CVTSI2SDQ, IA32_CVTSI2SDQ_opcode, IA32_CVTSI2SS, IA32_CVTSI2SS_opcode, IA32_CVTSS2SD, IA32_CVTSS2SD_opcode, IA32_CVTSS2SI, IA32_CVTSS2SI_opcode, IA32_CVTTSD2SI, IA32_CVTTSD2SI_opcode, IA32_CVTTSD2SIQ, IA32_CVTTSD2SIQ_opcode, IA32_CVTTSS2SI, IA32_CVTTSS2SI_opcode, IA32_DEC, IA32_DEC_opcode, IA32_DIV, IA32_DIV_opcode, IA32_DIVSD, IA32_DIVSD_opcode, IA32_DIVSS, IA32_DIVSS_opcode, IA32_FADD, IA32_FADD_opcode, IA32_FADDP, IA32_FADDP_opcode, IA32_FCHS, IA32_FCHS_opcode, IA32_FCLEAR, IA32_FCLEAR_opcode, IA32_FCMOV, IA32_FCMOV_opcode, IA32_FCOMI, IA32_FCOMI_opcode, IA32_FCOMIP, IA32_FCOMIP_opcode, IA32_FDIV, IA32_FDIV_opcode, IA32_FDIVP, IA32_FDIVP_opcode, IA32_FDIVR, IA32_FDIVR_opcode, IA32_FDIVRP, IA32_FDIVRP_opcode, IA32_FEXAM, IA32_FEXAM_opcode, IA32_FFREE, IA32_FFREE_opcode, IA32_FIADD, IA32_FIADD_opcode, IA32_FIDIV, IA32_FIDIV_opcode, IA32_FIDIVR, IA32_FIDIVR_opcode, IA32_FILD, IA32_FILD_opcode, IA32_FIMUL, IA32_FIMUL_opcode, IA32_FINIT, IA32_FINIT_opcode, IA32_FIST, IA32_FIST_opcode, IA32_FISTP, IA32_FISTP_opcode, IA32_FISUB, IA32_FISUB_opcode, IA32_FISUBR, IA32_FISUBR_opcode, IA32_FLD, IA32_FLD_opcode, IA32_FLD1, IA32_FLD1_opcode, IA32_FLDCW, IA32_FLDCW_opcode, IA32_FLDL2E, IA32_FLDL2E_opcode, IA32_FLDL2T, IA32_FLDL2T_opcode, IA32_FLDLG2, IA32_FLDLG2_opcode, IA32_FLDLN2, IA32_FLDLN2_opcode, IA32_FLDPI, IA32_FLDPI_opcode, IA32_FLDZ, IA32_FLDZ_opcode, IA32_FMOV, IA32_FMOV_ENDING_LIVE_RANGE, IA32_FMOV_ENDING_LIVE_RANGE_opcode, IA32_FMOV_opcode, IA32_FMUL, IA32_FMUL_opcode, IA32_FMULP, IA32_FMULP_opcode, IA32_FNINIT, IA32_FNINIT_opcode, IA32_FNSAVE, IA32_FNSAVE_opcode, IA32_FNSTCW, IA32_FNSTCW_opcode, IA32_FPREM, IA32_FPREM_opcode, IA32_FRSTOR, IA32_FRSTOR_opcode, IA32_FST, IA32_FST_opcode, IA32_FSTCW, IA32_FSTCW_opcode, IA32_FSTP, IA32_FSTP_opcode, IA32_FSUB, IA32_FSUB_opcode, IA32_FSUBP, IA32_FSUBP_opcode, IA32_FSUBR, IA32_FSUBR_opcode, IA32_FSUBRP, IA32_FSUBRP_opcode, IA32_FUCOMI, IA32_FUCOMI_opcode, IA32_FUCOMIP, IA32_FUCOMIP_opcode, IA32_FXCH, IA32_FXCH_opcode, IA32_IDIV, IA32_IDIV_opcode, IA32_IMUL1, IA32_IMUL1_opcode, IA32_IMUL2, IA32_IMUL2_opcode, IA32_INC, IA32_INC_opcode, IA32_INT, IA32_INT_opcode, IA32_JCC, IA32_JCC_opcode, IA32_JCC2, IA32_JCC2_opcode, IA32_JMP, IA32_JMP_opcode, IA32_LEA, IA32_LEA_opcode, IA32_LOCK, IA32_LOCK_CMPXCHG, IA32_LOCK_CMPXCHG_opcode, IA32_LOCK_CMPXCHG8B, IA32_LOCK_CMPXCHG8B_opcode, IA32_LOCK_opcode, IA32_METHODSTART, IA32_METHODSTART_opcode, IA32_MOV, IA32_MOV_opcode, IA32_MOVD, IA32_MOVD_opcode, IA32_MOVLPD, IA32_MOVLPD_opcode, IA32_MOVLPS, IA32_MOVLPS_opcode, IA32_MOVQ, IA32_MOVQ_opcode, IA32_MOVSD, IA32_MOVSD_opcode, IA32_MOVSS, IA32_MOVSS_opcode, IA32_MOVSX__B, IA32_MOVSX__B_opcode, IA32_MOVSX__W, IA32_MOVSX__W_opcode, IA32_MOVSXQ__B, IA32_MOVSXQ__B_opcode, IA32_MOVSXQ__W, IA32_MOVSXQ__W_opcode, IA32_MOVZX__B, IA32_MOVZX__B_opcode, IA32_MOVZX__W, IA32_MOVZX__W_opcode, IA32_MOVZXQ__B, IA32_MOVZXQ__B_opcode, IA32_MOVZXQ__W, IA32_MOVZXQ__W_opcode, IA32_MUL, IA32_MUL_opcode, IA32_MULSD, IA32_MULSD_opcode, IA32_MULSS, IA32_MULSS_opcode, IA32_NEG, IA32_NEG_opcode, IA32_NOT, IA32_NOT_opcode, IA32_OFFSET, IA32_OFFSET_opcode, IA32_OR, IA32_OR_opcode, IA32_ORPD, IA32_ORPD_opcode, IA32_ORPS, IA32_ORPS_opcode, IA32_PAUSE, IA32_PAUSE_opcode, IA32_POP, IA32_POP_opcode, IA32_PREFETCHNTA, IA32_PREFETCHNTA_opcode, IA32_PSLLQ, IA32_PSLLQ_opcode, IA32_PSRLQ, IA32_PSRLQ_opcode, IA32_PUSH, IA32_PUSH_opcode, IA32_RCL, IA32_RCL_opcode, IA32_RCR, IA32_RCR_opcode, IA32_RDTSC, IA32_RDTSC_opcode, IA32_RET, IA32_RET_opcode, IA32_ROL, IA32_ROL_opcode, IA32_ROR, IA32_ROR_opcode, IA32_SAL, IA32_SAL_opcode, IA32_SAR, IA32_SAR_opcode, IA32_SBB, IA32_SBB_opcode, IA32_SET__B, IA32_SET__B_opcode, IA32_SHL, IA32_SHL_opcode, IA32_SHLD, IA32_SHLD_opcode, IA32_SHR, IA32_SHR_opcode, IA32_SHRD, IA32_SHRD_opcode, IA32_SQRTSD, IA32_SQRTSD_opcode, IA32_SQRTSS, IA32_SQRTSS_opcode, IA32_SUB, IA32_SUB_opcode, IA32_SUBSD, IA32_SUBSD_opcode, IA32_SUBSS, IA32_SUBSS_opcode, IA32_SYSCALL, IA32_SYSCALL_opcode, IA32_TEST, IA32_TEST_opcode, IA32_TRAPIF, IA32_TRAPIF_opcode, IA32_UCOMISD, IA32_UCOMISD_opcode, IA32_UCOMISS, IA32_UCOMISS_opcode, IA32_XOR, IA32_XOR_opcode, IA32_XORPD, IA32_XORPD_opcode, IA32_XORPS, IA32_XORPS_opcode, IG_CLASS_TEST, IG_CLASS_TEST_opcode, IG_METHOD_TEST, IG_METHOD_TEST_opcode, IG_PATCH_POINT, IG_PATCH_POINT_opcode, INSTANCEOF, INSTANCEOF_NOTNULL, INSTANCEOF_NOTNULL_opcode, INSTANCEOF_opcode, INSTANCEOF_UNRESOLVED, INSTANCEOF_UNRESOLVED_opcode, INSTRUMENTED_EVENT_COUNTER, INSTRUMENTED_EVENT_COUNTER_opcode, INT_2ADDRSigExt, INT_2ADDRSigExt_opcode, INT_2ADDRZerExt, INT_2ADDRZerExt_opcode, INT_2BYTE, INT_2BYTE_opcode, INT_2DOUBLE, INT_2DOUBLE_opcode, INT_2FLOAT, INT_2FLOAT_opcode, INT_2FP, INT_2FP_opcode, INT_2LONG, INT_2LONG_opcode, INT_2SHORT, INT_2SHORT_opcode, INT_2USHORT, INT_2USHORT_opcode, INT_ADD, INT_ADD_opcode, INT_ALOAD, INT_ALOAD_opcode, INT_AND, INT_AND_opcode, INT_ASTORE, INT_ASTORE_opcode, INT_BITS_AS_FLOAT, INT_BITS_AS_FLOAT_opcode, INT_COND_MOVE, INT_COND_MOVE_opcode, INT_CONSTANT, INT_CONSTANT_opcode, INT_DIV, INT_DIV_opcode, INT_IFCMP, INT_IFCMP_opcode, INT_IFCMP2, INT_IFCMP2_opcode, INT_LOAD, INT_LOAD_opcode, INT_MOVE, INT_MOVE_opcode, INT_MUL, INT_MUL_opcode, INT_NEG, INT_NEG_opcode, INT_NOT, INT_NOT_opcode, INT_OR, INT_OR_opcode, INT_REM, INT_REM_opcode, INT_SHL, INT_SHL_opcode, INT_SHR, INT_SHR_opcode, INT_STORE, INT_STORE_opcode, INT_SUB, INT_SUB_opcode, INT_USHR, INT_USHR_opcode, INT_XOR, INT_XOR_opcode, INT_ZERO_CHECK, INT_ZERO_CHECK_opcode, IR_PROLOGUE, IR_PROLOGUE_opcode, LABEL, LABEL_opcode, LCMP_CMOV, LCMP_CMOV_opcode, LONG_2ADDR, LONG_2ADDR_opcode, LONG_2DOUBLE, LONG_2DOUBLE_opcode, LONG_2FLOAT, LONG_2FLOAT_opcode, LONG_2FP, LONG_2FP_opcode, LONG_2INT, LONG_2INT_opcode, LONG_ADD, LONG_ADD_opcode, LONG_ALOAD, LONG_ALOAD_opcode, LONG_AND, LONG_AND_opcode, LONG_ASTORE, LONG_ASTORE_opcode, LONG_BITS_AS_DOUBLE, LONG_BITS_AS_DOUBLE_opcode, LONG_CMP, LONG_CMP_opcode, LONG_COND_MOVE, LONG_COND_MOVE_opcode, LONG_CONSTANT, LONG_CONSTANT_opcode, LONG_DIV, LONG_DIV_opcode, LONG_IFCMP, LONG_IFCMP_opcode, LONG_LOAD, LONG_LOAD_opcode, LONG_MOVE, LONG_MOVE_opcode, LONG_MUL, LONG_MUL_opcode, LONG_NEG, LONG_NEG_opcode, LONG_NOT, LONG_NOT_opcode, LONG_OR, LONG_OR_opcode, LONG_REM, LONG_REM_opcode, LONG_SHL, LONG_SHL_opcode, LONG_SHR, LONG_SHR_opcode, LONG_STORE, LONG_STORE_opcode, LONG_SUB, LONG_SUB_opcode, LONG_USHR, LONG_USHR_opcode, LONG_XOR, LONG_XOR_opcode, LONG_ZERO_CHECK, LONG_ZERO_CHECK_opcode, LOOKUPSWITCH, LOOKUPSWITCH_opcode, LOWTABLESWITCH, LOWTABLESWITCH_opcode, MATERIALIZE_FP_CONSTANT, MATERIALIZE_FP_CONSTANT_opcode, MIR_END, MIR_END_opcode, MIR_LOWTABLESWITCH, MIR_LOWTABLESWITCH_opcode, MIR_START, MIR_START_opcode, MONITORENTER, MONITORENTER_opcode, MONITOREXIT, MONITOREXIT_opcode, MUST_IMPLEMENT_INTERFACE, MUST_IMPLEMENT_INTERFACE_opcode, NEW, NEW_opcode, NEW_UNRESOLVED, NEW_UNRESOLVED_opcode, NEWARRAY, NEWARRAY_opcode, NEWARRAY_UNRESOLVED, NEWARRAY_UNRESOLVED_opcode, NEWOBJMULTIARRAY, NEWOBJMULTIARRAY_opcode, NOP, NOP_opcode, NULL, NULL_CHECK, NULL_CHECK_opcode, NULL_opcode, OBJARRAY_STORE_CHECK, OBJARRAY_STORE_CHECK_NOTNULL, OBJARRAY_STORE_CHECK_NOTNULL_opcode, OBJARRAY_STORE_CHECK_opcode, OSR_BARRIER, OSR_BARRIER_opcode, OTHER_OPERAND, OTHER_OPERAND_opcode, PAUSE, PAUSE_opcode, PHI, PHI_opcode, PI, PI_opcode, PREFETCH, PREFETCH_opcode, PREPARE_ADDR, PREPARE_ADDR_opcode, PREPARE_INT, PREPARE_INT_opcode, PREPARE_LONG, PREPARE_LONG_opcode, PUTFIELD, PUTFIELD_opcode, PUTSTATIC, PUTSTATIC_opcode, READ_CEILING, READ_CEILING_opcode, REF_ADD, REF_ADD_opcode, REF_ALOAD, REF_ALOAD_opcode, REF_AND, REF_AND_opcode, REF_ASTORE, REF_ASTORE_opcode, REF_COND_MOVE, REF_COND_MOVE_opcode, REF_IFCMP, REF_IFCMP_opcode, REF_LOAD, REF_LOAD_opcode, REF_MOVE, REF_MOVE_opcode, REF_NEG, REF_NEG_opcode, REF_NOT, REF_NOT_opcode, REF_OR, REF_OR_opcode, REF_SHL, REF_SHL_opcode, REF_SHR, REF_SHR_opcode, REF_STORE, REF_STORE_opcode, REF_SUB, REF_SUB_opcode, REF_USHR, REF_USHR_opcode, REF_XOR, REF_XOR_opcode, REGISTER, REGISTER_opcode, REQUIRE_ESP, REQUIRE_ESP_opcode, RESOLVE, RESOLVE_MEMBER, RESOLVE_MEMBER_opcode, RESOLVE_opcode, RETURN, RETURN_opcode, ROUND_TO_ZERO, ROUND_TO_ZERO_opcode, SET_CAUGHT_EXCEPTION, SET_CAUGHT_EXCEPTION_opcode, SHORT_ALOAD, SHORT_ALOAD_opcode, SHORT_ASTORE, SHORT_ASTORE_opcode, SHORT_LOAD, SHORT_LOAD_opcode, SHORT_STORE, SHORT_STORE_opcode, SPLIT, SPLIT_opcode, SYSCALL, SYSCALL_opcode, TABLESWITCH, TABLESWITCH_opcode, TRAP, TRAP_IF, TRAP_IF_opcode, TRAP_opcode, UBYTE_ALOAD, UBYTE_ALOAD_opcode, UBYTE_LOAD, UBYTE_LOAD_opcode, UNINT_BEGIN, UNINT_BEGIN_opcode, UNINT_END, UNINT_END_opcode, USHORT_ALOAD, USHORT_ALOAD_opcode, USHORT_LOAD, USHORT_LOAD_opcode, WRITE_FLOOR, WRITE_FLOOR_opcode, YIELDPOINT_BACKEDGE, YIELDPOINT_BACKEDGE_opcode, YIELDPOINT_EPILOGUE, YIELDPOINT_EPILOGUE_opcode, YIELDPOINT_OSR, YIELDPOINT_OSR_opcode, YIELDPOINT_PROLOGUE, YIELDPOINT_PROLOGUE_opcode
 
Fields inherited from interface org.jikesrvm.Constants
NOT_REACHED, REFLECTION_FPRS_BITS, REFLECTION_FPRS_MASK, REFLECTION_GPRS_BITS, REFLECTION_GPRS_MASK
 
Fields inherited from interface org.jikesrvm.objectmodel.ThinLockConstants
TL_DEDICATED_U16_OFFSET, TL_DEDICATED_U16_SHIFT, TL_LOCK_COUNT_MASK, TL_LOCK_COUNT_SHIFT, TL_LOCK_COUNT_UNIT, TL_LOCK_ID_MASK, TL_LOCK_ID_SHIFT, TL_NUM_BITS_RC, TL_NUM_BITS_STAT, TL_NUM_BITS_TID, TL_STAT_BIASABLE, TL_STAT_FAT, TL_STAT_MASK, TL_STAT_SHIFT, TL_STAT_THIN, TL_THREAD_ID_MASK, TL_THREAD_ID_SHIFT, TL_UNLOCK_MASK
 
Fields inherited from interface org.jikesrvm.SizeConstants
BITS_IN_ADDRESS, BITS_IN_BOOLEAN, BITS_IN_BYTE, BITS_IN_CHAR, BITS_IN_DOUBLE, BITS_IN_EXTENT, BITS_IN_FLOAT, BITS_IN_INT, BITS_IN_LONG, BITS_IN_OFFSET, BITS_IN_PAGE, BITS_IN_SHORT, BITS_IN_WORD, BYTES_IN_ADDRESS, BYTES_IN_BOOLEAN, BYTES_IN_BYTE, BYTES_IN_CHAR, BYTES_IN_DOUBLE, BYTES_IN_EXTENT, BYTES_IN_FLOAT, BYTES_IN_INT, BYTES_IN_LONG, BYTES_IN_OFFSET, BYTES_IN_PAGE, BYTES_IN_SHORT, BYTES_IN_WORD, LOG_BITS_IN_ADDRESS, LOG_BITS_IN_BOOLEAN, LOG_BITS_IN_BYTE, LOG_BITS_IN_CHAR, LOG_BITS_IN_DOUBLE, LOG_BITS_IN_EXTENT, LOG_BITS_IN_FLOAT, LOG_BITS_IN_INT, LOG_BITS_IN_LONG, LOG_BITS_IN_OFFSET, LOG_BITS_IN_PAGE, LOG_BITS_IN_SHORT, LOG_BITS_IN_WORD, LOG_BYTES_IN_ADDRESS, LOG_BYTES_IN_BOOLEAN, LOG_BYTES_IN_BYTE, LOG_BYTES_IN_CHAR, LOG_BYTES_IN_DOUBLE, LOG_BYTES_IN_EXTENT, LOG_BYTES_IN_FLOAT, LOG_BYTES_IN_INT, LOG_BYTES_IN_LONG, LOG_BYTES_IN_OFFSET, LOG_BYTES_IN_PAGE, LOG_BYTES_IN_SHORT, LOG_BYTES_IN_WORD
 
Fields inherited from interface org.jikesrvm.objectmodel.TIBLayoutConstants
IMT_METHOD_SLOTS, NEEDS_DYNAMIC_LINK, TIB_ARRAY_ELEMENT_TIB_INDEX, TIB_DOES_IMPLEMENT_INDEX, TIB_FIRST_SPECIALIZED_METHOD_INDEX, TIB_FIRST_VIRTUAL_METHOD_INDEX, TIB_INTERFACE_DISPATCH_TABLE_INDEX, TIB_SUPERCLASS_IDS_INDEX, TIB_TYPE_INDEX
 
Fields inherited from interface org.jikesrvm.HeapLayoutConstants
BAD_MAP_COMPRESSION, BOOT_IMAGE_CODE_END, BOOT_IMAGE_CODE_SIZE, BOOT_IMAGE_CODE_START, BOOT_IMAGE_DATA_END, BOOT_IMAGE_DATA_SIZE, BOOT_IMAGE_DATA_START, BOOT_IMAGE_END, BOOT_IMAGE_RMAP_END, BOOT_IMAGE_RMAP_START, MAX_BOOT_IMAGE_RMAP_SIZE, MAXIMUM_MAPPABLE
 
Fields inherited from interface org.jikesrvm.compilers.opt.regalloc.ia32.PhysicalRegisterConstants
AF, C0, C1, C2, C3, CF, CONDITION_VALUE, DOUBLE_REG, DOUBLE_VALUE, FIRST_DOUBLE, FIRST_INT, FIRST_SPECIAL, FLOAT_VALUE, INT_REG, INT_VALUE, NUM_SPECIALS, NUMBER_TYPE, OF, PF, SF, SPECIAL_REG, ST0, ST1, ZF
 
Fields inherited from interface org.jikesrvm.ia32.RegisterConstants
ALL_FPRS, ALL_GPRS, EAX, EBX, ECX, EDI, EDX, ESI, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7, INSTRUCTION_WIDTH, LG_INSTRUCTION_WIDTH, MM0, MM1, MM10, MM11, MM12, MM13, MM14, MM15, MM2, MM3, MM4, MM5, MM6, MM7, MM8, MM9, NATIVE_NONVOLATILE_FPRS, NATIVE_NONVOLATILE_GPRS, NATIVE_PARAMETER_FPRS, NATIVE_PARAMETER_GPRS, NATIVE_VOLATILE_FPRS, NATIVE_VOLATILE_GPRS, NONVOLATILE_FPRS, NONVOLATILE_GPRS, NUM_FPRS, NUM_GPRS, NUM_NONVOLATILE_FPRS, NUM_NONVOLATILE_GPRS, NUM_PARAMETER_FPRS, NUM_PARAMETER_GPRS, NUM_RETURN_FPRS, NUM_RETURN_GPRS, NUM_VOLATILE_FPRS, NUM_VOLATILE_GPRS, PARAMETER_FPRS, PARAMETER_GPRS, R0, R1, R10, R11, R12, R13, R14, R15, R2, R3, R4, R5, R6, R7, R8, R9, RETURN_FPRS, RETURN_GPRS, STACK_POINTER, THREAD_REGISTER, VOLATILE_FPRS, VOLATILE_GPRS, XMM0, XMM1, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9
 
Fields inherited from interface org.jikesrvm.compilers.common.assembler.ia32.AssemblerConstants
BYTE, CONDITION, EQ, GE, GT, LE, LGE, LGT, LLE, LLT, LONG, LT, NE, NO, NS, O, PE, PO, S, SHORT, WORD
 
Constructor Summary
AssemblerOpt(int bcSize, boolean print, IR ir)
           
 
Method Summary
private  void doADC(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADC operator
private  void doADD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADD operator
private  void doADDSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSD operator
private  void doADDSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ADDSS operator
private  void doAND(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a AND operator
private  void doANDNPD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPD operator
private  void doANDNPS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDNPS operator
private  void doANDPD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPD operator
private  void doANDPS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ANDPS operator
private  void doBSWAP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a BSWAP operator
private  void doBT(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Test instruction and has a BT operator
private  void doBTC(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTC operator
private  void doBTR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTR operator
private  void doBTS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Test instruction and has a BTS operator
private  void doCALL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Call instruction and has a CALL operator
private  void doCDO(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDO operator
private  void doCDQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQ operator
private  void doCDQE(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_ConvertDW2QW instruction and has a CDQE operator
private  void doCMOV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a CMOV operator
private  void doCMP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a CMP operator
private  void doCMPEQSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSD operator
private  void doCMPEQSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPEQSS operator
private  void doCMPLESD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESD operator
private  void doCMPLESS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLESS operator
private  void doCMPLTSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSD operator
private  void doCMPLTSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPLTSS operator
private  void doCMPNESD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESD operator
private  void doCMPNESS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNESS operator
private  void doCMPNLESD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESD operator
private  void doCMPNLESS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLESS operator
private  void doCMPNLTSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSD operator
private  void doCMPNLTSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPNLTSS operator
private  void doCMPORDSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSD operator
private  void doCMPORDSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPORDSS operator
private  void doCMPUNORDSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSD operator
private  void doCMPUNORDSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a CMPUNORDSS operator
private  void doCMPXCHG(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CompareExchange instruction and has a CMPXCHG operator
private  void doCMPXCHG8B(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CompareExchange8B instruction and has a CMPXCHG8B operator
private  void doCVTSD2SI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SI operator
private  void doCVTSD2SIQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SIQ operator
private  void doCVTSD2SS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSD2SS operator
private  void doCVTSI2SD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SD operator
private  void doCVTSI2SDQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SDQ operator
private  void doCVTSI2SS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSI2SS operator
private  void doCVTSS2SD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SD operator
private  void doCVTSS2SI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTSS2SI operator
private  void doCVTTSD2SI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SI operator
private  void doCVTTSD2SIQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSD2SIQ operator
private  void doCVTTSS2SI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a CVTTSS2SI operator
private  void doDEC(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a DEC operator
private  void doDIV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Divide instruction and has a DIV operator
private  void doDIVSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSD operator
private  void doDIVSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a DIVSS operator
private  void doFADD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADD operator
private  void doFADDP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FADDP operator
private  void doFCHS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a FCHS operator
private  void doFCMOV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CondMove instruction and has a FCMOV operator
private  void doFCOMI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMI operator
private  void doFCOMIP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FCOMIP operator
private  void doFDIV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIV operator
private  void doFDIVP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVP operator
private  void doFDIVR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVR operator
private  void doFDIVRP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FDIVRP operator
private  void doFFREE(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FFREE operator
private  void doFIADD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIADD operator
private  void doFIDIV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIV operator
private  void doFIDIVR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIDIVR operator
private  void doFILD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FILD operator
private  void doFIMUL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FIMUL operator
private  void doFINIT(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FINIT operator
private  void doFIST(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FIST operator
private  void doFISTP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FISTP operator
private  void doFISUB(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUB operator
private  void doFISUBR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FISUBR operator
private  void doFLD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FLD operator
private  void doFLD1(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLD1 operator
private  void doFLDCW(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FLDCW operator
private  void doFLDL2E(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2E operator
private  void doFLDL2T(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDL2T operator
private  void doFLDLG2(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLG2 operator
private  void doFLDLN2(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDLN2 operator
private  void doFLDPI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDPI operator
private  void doFLDZ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a FLDZ operator
private  void doFMUL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMUL operator
private  void doFMULP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FMULP operator
private  void doFNINIT(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Empty instruction and has a FNINIT operator
private  void doFNSAVE(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FNSAVE operator
private  void doFNSTCW(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FNSTCW operator
private  void doFPREM(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FPREM operator
private  void doFRSTOR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_FSave instruction and has a FRSTOR operator
private  void doFST(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FST operator
private  void doFSTCW(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a FSTCW operator
private  void doFSTP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a FSTP operator
private  void doFSUB(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUB operator
private  void doFSUBP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBP operator
private  void doFSUBR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBR operator
private  void doFSUBRP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a FSUBRP operator
private  void doFUCOMI(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMI operator
private  void doFUCOMIP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a FUCOMIP operator
private  void doFXCH(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_XChng instruction and has a FXCH operator
private  void doIDIV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Divide instruction and has a IDIV operator
private  void doIMUL1(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a IMUL1 operator
private  void doIMUL2(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a IMUL2 operator
private  void doINC(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a INC operator
 void doInst(Instruction inst)
          Assemble the given instruction
private  void doINT(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Trap instruction and has a INT operator
private  void doLEA(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Lea instruction and has a LEA operator
private  void doMETHODSTART(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a METHODSTART operator
private  void doMOV(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOV operator
private  void doMOVD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVD operator
private  void doMOVLPD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPD operator
private  void doMOVLPS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVLPS operator
private  void doMOVQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVQ operator
private  void doMOVSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSD operator
private  void doMOVSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Move instruction and has a MOVSS operator
private  void doMOVSX(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSX operator
private  void doMOVSXQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVSXQ operator
private  void doMOVZX(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZX operator
private  void doMOVZXQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a MOVZXQ operator
private  void doMUL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Multiply instruction and has a MUL operator
private  void doMULSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSD operator
private  void doMULSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a MULSS operator
private  void doNEG(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NEG operator
private  void doNOT(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryAcc instruction and has a NOT operator
private  void doOFFSET(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CaseLabel instruction and has a OFFSET operator
private  void doOR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a OR operator
private  void doORPD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPD operator
private  void doORPS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ORPS operator
private  void doPAUSE(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Empty instruction and has a PAUSE operator
private  void doPOP(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Nullary instruction and has a POP operator
private  void doPREFETCHNTA(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_CacheOp instruction and has a PREFETCHNTA operator
private  void doPSLLQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSLLQ operator
private  void doPSRLQ(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a PSRLQ operator
private  void doPUSH(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_UnaryNoRes instruction and has a PUSH operator
private  void doRCL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCL operator
private  void doRCR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a RCR operator
private  void doRDTSC(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_RDTSC instruction and has a RDTSC operator
private  void doRET(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Return instruction and has a RET operator
private  void doROL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROL operator
private  void doROR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a ROR operator
private  void doSAL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAL operator
private  void doSAR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SAR operator
private  void doSBB(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SBB operator
private  void doSET(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Set instruction and has a SET operator
private  void doSHL(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHL operator
private  void doSHLD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHLD operator
private  void doSHR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SHR operator
private  void doSHRD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_DoubleShift instruction and has a SHRD operator
private  void doSQRTSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSD operator
private  void doSQRTSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Unary instruction and has a SQRTSS operator
private  void doSUB(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUB operator
private  void doSUBSD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSD operator
private  void doSUBSS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a SUBSS operator
private  void doTEST(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Test instruction and has a TEST operator
private  void doUCOMISD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISD operator
private  void doUCOMISS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_Compare instruction and has a UCOMISS operator
private  void doXOR(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XOR operator
private  void doXORPD(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPD operator
private  void doXORPS(Instruction inst)
          Emit the given instruction, assuming that it is a MIR_BinaryAcc instruction and has a XORPS operator
 
Methods inherited from class org.jikesrvm.compilers.opt.mir2mc.ia32.AssemblerBase
disasm, doJCC, doJMP, doLOWTABLESWITCH, estimateSize, generateCode, getBase, getCond, getDisp, getFPR_Reg, getGPR_Reg, getImm, getIndex, getLabel, getMM_Reg, getReg, getScale, getXMM_Reg, isAbs, isByte, isCond, isFPR_Reg, isGPR_Reg, isHotCode, isImm, isImmOrLabel, isLabel, isMM_Reg, isQuad, isReg, isRegDisp, isRegIdx, isRegInd, isRegOff, isWord, isXMM_Reg, targetIsClose
 
Methods inherited from class org.jikesrvm.compilers.common.assembler.ia32.Assembler
comment, emitADC_Abs_Imm_Byte, emitADC_Abs_Imm_Quad, emitADC_Abs_Imm_Word, emitADC_Abs_Imm, emitADC_Abs_Reg_Byte, emitADC_Abs_Reg_Quad, emitADC_Abs_Reg_Word, emitADC_Abs_Reg, emitADC_Reg_Abs_Byte, emitADC_Reg_Abs_Quad, emitADC_Reg_Abs_Word, emitADC_Reg_Abs, emitADC_Reg_Imm_Byte, emitADC_Reg_Imm_Quad, emitADC_Reg_Imm_Word, emitADC_Reg_Imm, emitADC_Reg_Reg_Byte, emitADC_Reg_Reg_Quad, emitADC_Reg_Reg_Word, emitADC_Reg_Reg, emitADC_Reg_RegDisp_Byte, emitADC_Reg_RegDisp_Quad, emitADC_Reg_RegDisp_Word, emitADC_Reg_RegDisp, emitADC_Reg_RegIdx_Byte, emitADC_Reg_RegIdx_Quad, emitADC_Reg_RegIdx_Word, emitADC_Reg_RegIdx, emitADC_Reg_RegInd_Byte, emitADC_Reg_RegInd_Quad, emitADC_Reg_RegInd_Word, emitADC_Reg_RegInd, emitADC_Reg_RegOff_Byte, emitADC_Reg_RegOff_Quad, emitADC_Reg_RegOff_Word, emitADC_Reg_RegOff, emitADC_RegDisp_Imm_Byte, emitADC_RegDisp_Imm_Quad, emitADC_RegDisp_Imm_Word, emitADC_RegDisp_Imm, emitADC_RegDisp_Reg_Byte, emitADC_RegDisp_Reg_Quad, emitADC_RegDisp_Reg_Word, emitADC_RegDisp_Reg, emitADC_RegIdx_Imm_Byte, emitADC_RegIdx_Imm_Quad, emitADC_RegIdx_Imm_Word, emitADC_RegIdx_Imm, emitADC_RegIdx_Reg_Byte, emitADC_RegIdx_Reg_Quad, emitADC_RegIdx_Reg_Word, emitADC_RegIdx_Reg, emitADC_RegInd_Imm_Byte, emitADC_RegInd_Imm_Quad, emitADC_RegInd_Imm_Word, emitADC_RegInd_Imm, emitADC_RegInd_Reg_Byte, emitADC_RegInd_Reg_Quad, emitADC_RegInd_Reg_Word, emitADC_RegInd_Reg, emitADC_RegOff_Imm_Byte, emitADC_RegOff_Imm_Quad, emitADC_RegOff_Imm_Word, emitADC_RegOff_Imm, emitADC_RegOff_Reg_Byte, emitADC_RegOff_Reg_Quad, emitADC_RegOff_Reg_Word, emitADC_RegOff_Reg, emitADD_Abs_Imm_Byte, emitADD_Abs_Imm_Quad, emitADD_Abs_Imm_Word, emitADD_Abs_Imm, emitADD_Abs_Reg_Byte, emitADD_Abs_Reg_Quad, emitADD_Abs_Reg_Word, emitADD_Abs_Reg, emitADD_Reg_Abs_Byte, emitADD_Reg_Abs_Quad, emitADD_Reg_Abs_Word, emitADD_Reg_Abs, emitADD_Reg_Imm_Byte, emitADD_Reg_Imm_Quad, emitADD_Reg_Imm_Word, emitADD_Reg_Imm, emitADD_Reg_Reg_Byte, emitADD_Reg_Reg_Quad, emitADD_Reg_Reg_Word, emitADD_Reg_Reg, emitADD_Reg_RegDisp_Byte, emitADD_Reg_RegDisp_Quad, emitADD_Reg_RegDisp_Word, emitADD_Reg_RegDisp, emitADD_Reg_RegIdx_Byte, emitADD_Reg_RegIdx_Quad, emitADD_Reg_RegIdx_Word, emitADD_Reg_RegIdx, emitADD_Reg_RegInd_Byte, emitADD_Reg_RegInd_Quad, emitADD_Reg_RegInd_Word, emitADD_Reg_RegInd, emitADD_Reg_RegOff_Byte, emitADD_Reg_RegOff_Quad, emitADD_Reg_RegOff_Word, emitADD_Reg_RegOff, emitADD_RegDisp_Imm_Byte, emitADD_RegDisp_Imm_Quad, emitADD_RegDisp_Imm_Word, emitADD_RegDisp_Imm, emitADD_RegDisp_Reg_Byte, emitADD_RegDisp_Reg_Quad, emitADD_RegDisp_Reg_Word, emitADD_RegDisp_Reg, emitADD_RegIdx_Imm_Byte, emitADD_RegIdx_Imm_Quad, emitADD_RegIdx_Imm_Word, emitADD_RegIdx_Imm, emitADD_RegIdx_Reg_Byte, emitADD_RegIdx_Reg_Quad, emitADD_RegIdx_Reg_Word, emitADD_RegIdx_Reg, emitADD_RegInd_Imm_Byte, emitADD_RegInd_Imm_Quad, emitADD_RegInd_Imm_Word, emitADD_RegInd_Imm, emitADD_RegInd_Reg_Byte, emitADD_RegInd_Reg_Quad, emitADD_RegInd_Reg_Word, emitADD_RegInd_Reg, emitADD_RegOff_Imm_Byte, emitADD_RegOff_Imm_Quad, emitADD_RegOff_Imm_Word, emitADD_RegOff_Imm, emitADD_RegOff_Reg_Byte, emitADD_RegOff_Reg_Quad, emitADD_RegOff_Reg_Word, emitADD_RegOff_Reg, emitADDSD_Reg_Abs, emitADDSD_Reg_Reg, emitADDSD_Reg_RegDisp, emitADDSD_Reg_RegIdx, emitADDSD_Reg_RegInd, emitADDSD_Reg_RegOff, emitADDSS_Reg_Abs, emitADDSS_Reg_Reg, emitADDSS_Reg_RegDisp, emitADDSS_Reg_RegIdx, emitADDSS_Reg_RegInd, emitADDSS_Reg_RegOff, emitAND_Abs_Imm_Byte, emitAND_Abs_Imm_Quad, emitAND_Abs_Imm_Word, emitAND_Abs_Imm, emitAND_Abs_Reg_Byte, emitAND_Abs_Reg_Quad, emitAND_Abs_Reg_Word, emitAND_Abs_Reg, emitAND_Reg_Abs_Byte, emitAND_Reg_Abs_Quad, emitAND_Reg_Abs_Word, emitAND_Reg_Abs, emitAND_Reg_Imm_Byte, emitAND_Reg_Imm_Quad, emitAND_Reg_Imm_Word, emitAND_Reg_Imm, emitAND_Reg_Reg_Byte, emitAND_Reg_Reg_Quad, emitAND_Reg_Reg_Word, emitAND_Reg_Reg, emitAND_Reg_RegDisp_Byte, emitAND_Reg_RegDisp_Quad, emitAND_Reg_RegDisp_Word, emitAND_Reg_RegDisp, emitAND_Reg_RegIdx_Byte, emitAND_Reg_RegIdx_Quad, emitAND_Reg_RegIdx_Word, emitAND_Reg_RegIdx, emitAND_Reg_RegInd_Byte, emitAND_Reg_RegInd_Quad, emitAND_Reg_RegInd_Word, emitAND_Reg_RegInd, emitAND_Reg_RegOff_Byte, emitAND_Reg_RegOff_Quad, emitAND_Reg_RegOff_Word, emitAND_Reg_RegOff, emitAND_RegDisp_Imm_Byte, emitAND_RegDisp_Imm_Quad, emitAND_RegDisp_Imm_Word, emitAND_RegDisp_Imm, emitAND_RegDisp_Reg_Byte, emitAND_RegDisp_Reg_Quad, emitAND_RegDisp_Reg_Word, emitAND_RegDisp_Reg, emitAND_RegIdx_Imm_Byte, emitAND_RegIdx_Imm_Quad, emitAND_RegIdx_Imm_Word, emitAND_RegIdx_Imm, emitAND_RegIdx_Reg_Byte, emitAND_RegIdx_Reg_Quad, emitAND_RegIdx_Reg_Word, emitAND_RegIdx_Reg, emitAND_RegInd_Imm_Byte, emitAND_RegInd_Imm_Quad, emitAND_RegInd_Imm_Word, emitAND_RegInd_Imm, emitAND_RegInd_Reg_Byte, emitAND_RegInd_Reg_Quad, emitAND_RegInd_Reg_Word, emitAND_RegInd_Reg, emitAND_RegOff_Imm_Byte, emitAND_RegOff_Imm_Quad, emitAND_RegOff_Imm_Word, emitAND_RegOff_Imm, emitAND_RegOff_Reg_Byte, emitAND_RegOff_Reg_Quad, emitAND_RegOff_Reg_Word, emitAND_RegOff_Reg, emitANDNPD_Reg_Abs, emitANDNPD_Reg_Reg, emitANDNPD_Reg_RegDisp, emitANDNPD_Reg_RegIdx, emitANDNPD_Reg_RegInd, emitANDNPD_Reg_RegOff, emitANDNPS_Reg_Abs, emitANDNPS_Reg_Reg, emitANDNPS_Reg_RegDisp, emitANDNPS_Reg_RegIdx, emitANDNPS_Reg_RegInd, emitANDNPS_Reg_RegOff, emitANDPD_Reg_Abs, emitANDPD_Reg_Reg, emitANDPD_Reg_RegDisp, emitANDPD_Reg_RegIdx, emitANDPD_Reg_RegInd, emitANDPD_Reg_RegOff, emitANDPS_Reg_Abs, emitANDPS_Reg_Reg, emitANDPS_Reg_RegDisp, emitANDPS_Reg_RegIdx, emitANDPS_Reg_RegInd, emitANDPS_Reg_RegOff, emitBranchLikelyNextInstruction, emitBranchUnlikelyNextInstruction, emitBSWAP_Reg_Quad, emitBSWAP_Reg, emitBT_Abs_Imm, emitBT_Abs_Reg, emitBT_Reg_Imm, emitBT_Reg_Reg, emitBT_RegDisp_Imm, emitBT_RegDisp_Reg, emitBT_RegIdx_Imm, emitBT_RegIdx_Reg, emitBT_RegInd_Imm, emitBT_RegInd_Reg, emitBT_RegOff_Imm, emitBT_RegOff_Reg, emitBTC_Abs_Imm, emitBTC_Abs_Reg, emitBTC_Reg_Imm, emitBTC_Reg_Reg, emitBTC_RegDisp_Imm, emitBTC_RegDisp_Reg, emitBTC_RegIdx_Imm, emitBTC_RegIdx_Reg, emitBTC_RegInd_Imm, emitBTC_RegInd_Reg, emitBTC_RegOff_Imm, emitBTC_RegOff_Reg, emitBTR_Abs_Imm, emitBTR_Abs_Reg, emitBTR_Reg_Imm, emitBTR_Reg_Reg, emitBTR_RegDisp_Imm, emitBTR_RegDisp_Reg, emitBTR_RegIdx_Imm, emitBTR_RegIdx_Reg, emitBTR_RegInd_Imm, emitBTR_RegInd_Reg, emitBTR_RegOff_Imm, emitBTR_RegOff_Reg, emitBTS_Abs_Imm, emitBTS_Abs_Reg, emitBTS_Reg_Imm, emitBTS_Reg_Reg, emitBTS_RegDisp_Imm, emitBTS_RegDisp_Reg, emitBTS_RegIdx_Imm, emitBTS_RegIdx_Reg, emitBTS_RegInd_Imm, emitBTS_RegInd_Reg, emitBTS_RegOff_Imm, emitBTS_RegOff_Reg, emitCALL_Abs, emitCALL_Imm, emitCALL_ImmOrLabel, emitCALL_Label, emitCALL_Reg, emitCALL_RegDisp, emitCALL_RegIdx, emitCALL_RegInd, emitCALL_RegOff, emitCDO, emitCDQ, emitCDQE, emitCMOV_Cond_Reg_Abs, emitCMOV_Cond_Reg_Reg, emitCMOV_Cond_Reg_RegDisp, emitCMOV_Cond_Reg_RegIdx, emitCMOV_Cond_Reg_RegInd, emitCMOV_Cond_Reg_RegOff, emitCMP_Abs_Imm_Byte, emitCMP_Abs_Imm_Quad, emitCMP_Abs_Imm_Word, emitCMP_Abs_Imm, emitCMP_Abs_Reg_Byte, emitCMP_Abs_Reg_Quad, emitCMP_Abs_Reg_Word, emitCMP_Abs_Reg, emitCMP_Reg_Abs_Byte, emitCMP_Reg_Abs_Quad, emitCMP_Reg_Abs_Word, emitCMP_Reg_Abs, emitCMP_Reg_Imm_Byte, emitCMP_Reg_Imm_Quad, emitCMP_Reg_Imm_Word, emitCMP_Reg_Imm, emitCMP_Reg_Reg_Byte, emitCMP_Reg_Reg_Quad, emitCMP_Reg_Reg_Word, emitCMP_Reg_Reg, emitCMP_Reg_RegDisp_Byte, emitCMP_Reg_RegDisp_Quad, emitCMP_Reg_RegDisp_Word, emitCMP_Reg_RegDisp, emitCMP_Reg_RegIdx_Byte, emitCMP_Reg_RegIdx_Quad, emitCMP_Reg_RegIdx_Word, emitCMP_Reg_RegIdx, emitCMP_Reg_RegInd_Byte, emitCMP_Reg_RegInd_Quad, emitCMP_Reg_RegInd_Word, emitCMP_Reg_RegInd, emitCMP_Reg_RegOff_Byte, emitCMP_Reg_RegOff_Quad, emitCMP_Reg_RegOff_Word, emitCMP_Reg_RegOff, emitCMP_RegDisp_Imm_Byte, emitCMP_RegDisp_Imm_Quad, emitCMP_RegDisp_Imm_Word, emitCMP_RegDisp_Imm, emitCMP_RegDisp_Reg_Byte, emitCMP_RegDisp_Reg_Quad, emitCMP_RegDisp_Reg_Word, emitCMP_RegDisp_Reg, emitCMP_RegIdx_Imm_Byte, emitCMP_RegIdx_Imm_Quad, emitCMP_RegIdx_Imm_Word, emitCMP_RegIdx_Imm, emitCMP_RegIdx_Reg_Byte, emitCMP_RegIdx_Reg_Quad, emitCMP_RegIdx_Reg_Word, emitCMP_RegIdx_Reg, emitCMP_RegInd_Imm_Byte, emitCMP_RegInd_Imm_Quad, emitCMP_RegInd_Imm_Word, emitCMP_RegInd_Imm, emitCMP_RegInd_Reg_Byte, emitCMP_RegInd_Reg_Quad, emitCMP_RegInd_Reg_Word, emitCMP_RegInd_Reg, emitCMP_RegOff_Imm_Byte, emitCMP_RegOff_Imm_Quad, emitCMP_RegOff_Imm_Word, emitCMP_RegOff_Imm, emitCMP_RegOff_Reg_Byte, emitCMP_RegOff_Reg_Quad, emitCMP_RegOff_Reg_Word, emitCMP_RegOff_Reg, emitCMPEQSD_Reg_Abs, emitCMPEQSD_Reg_Reg, emitCMPEQSD_Reg_RegDisp, emitCMPEQSD_Reg_RegIdx, emitCMPEQSD_Reg_RegInd, emitCMPEQSD_Reg_RegOff, emitCMPEQSS_Reg_Abs, emitCMPEQSS_Reg_Reg, emitCMPEQSS_Reg_RegDisp, emitCMPEQSS_Reg_RegIdx, emitCMPEQSS_Reg_RegInd, emitCMPEQSS_Reg_RegOff, emitCMPLESD_Reg_Abs, emitCMPLESD_Reg_Reg, emitCMPLESD_Reg_RegDisp, emitCMPLESD_Reg_RegIdx, emitCMPLESD_Reg_RegInd, emitCMPLESD_Reg_RegOff, emitCMPLESS_Reg_Abs, emitCMPLESS_Reg_Reg, emitCMPLESS_Reg_RegDisp, emitCMPLESS_Reg_RegIdx, emitCMPLESS_Reg_RegInd, emitCMPLESS_Reg_RegOff, emitCMPLTSD_Reg_Abs, emitCMPLTSD_Reg_Reg, emitCMPLTSD_Reg_RegDisp, emitCMPLTSD_Reg_RegIdx, emitCMPLTSD_Reg_RegInd, emitCMPLTSD_Reg_RegOff, emitCMPLTSS_Reg_Abs, emitCMPLTSS_Reg_Reg, emitCMPLTSS_Reg_RegDisp, emitCMPLTSS_Reg_RegIdx, emitCMPLTSS_Reg_RegInd, emitCMPLTSS_Reg_RegOff, emitCMPNESD_Reg_Abs, emitCMPNESD_Reg_Reg, emitCMPNESD_Reg_RegDisp, emitCMPNESD_Reg_RegIdx, emitCMPNESD_Reg_RegInd, emitCMPNESD_Reg_RegOff, emitCMPNESS_Reg_Abs, emitCMPNESS_Reg_Reg, emitCMPNESS_Reg_RegDisp, emitCMPNESS_Reg_RegIdx, emitCMPNESS_Reg_RegInd, emitCMPNESS_Reg_RegOff, emitCMPNLESD_Reg_Abs, emitCMPNLESD_Reg_Reg, emitCMPNLESD_Reg_RegDisp, emitCMPNLESD_Reg_RegIdx, emitCMPNLESD_Reg_RegInd, emitCMPNLESD_Reg_RegOff, emitCMPNLESS_Reg_Abs, emitCMPNLESS_Reg_Reg, emitCMPNLESS_Reg_RegDisp, emitCMPNLESS_Reg_RegIdx, emitCMPNLESS_Reg_RegInd, emitCMPNLESS_Reg_RegOff, emitCMPNLTSD_Reg_Abs, emitCMPNLTSD_Reg_Reg, emitCMPNLTSD_Reg_RegDisp, emitCMPNLTSD_Reg_RegIdx, emitCMPNLTSD_Reg_RegInd, emitCMPNLTSD_Reg_RegOff, emitCMPNLTSS_Reg_Abs, emitCMPNLTSS_Reg_Reg, emitCMPNLTSS_Reg_RegDisp, emitCMPNLTSS_Reg_RegIdx, emitCMPNLTSS_Reg_RegInd, emitCMPNLTSS_Reg_RegOff, emitCMPORDSD_Reg_Abs, emitCMPORDSD_Reg_Reg, emitCMPORDSD_Reg_RegDisp, emitCMPORDSD_Reg_RegIdx, emitCMPORDSD_Reg_RegInd, emitCMPORDSD_Reg_RegOff, emitCMPORDSS_Reg_Abs, emitCMPORDSS_Reg_Reg, emitCMPORDSS_Reg_RegDisp, emitCMPORDSS_Reg_RegIdx, emitCMPORDSS_Reg_RegInd, emitCMPORDSS_Reg_RegOff, emitCMPUNORDSD_Reg_Abs, emitCMPUNORDSD_Reg_Reg, emitCMPUNORDSD_Reg_RegDisp, emitCMPUNORDSD_Reg_RegIdx, emitCMPUNORDSD_Reg_RegInd, emitCMPUNORDSD_Reg_RegOff, emitCMPUNORDSS_Reg_Abs, emitCMPUNORDSS_Reg_Reg, emitCMPUNORDSS_Reg_RegDisp, emitCMPUNORDSS_Reg_RegIdx, emitCMPUNORDSS_Reg_RegInd, emitCMPUNORDSS_Reg_RegOff, emitCMPXCHG_Abs_Reg_Quad, emitCMPXCHG_Abs_Reg, emitCMPXCHG_Reg_Reg_Quad, emitCMPXCHG_Reg_Reg, emitCMPXCHG_RegDisp_Reg_Quad, emitCMPXCHG_RegDisp_Reg, emitCMPXCHG_RegIdx_Reg_Quad, emitCMPXCHG_RegIdx_Reg, emitCMPXCHG_RegInd_Reg_Quad, emitCMPXCHG_RegInd_Reg, emitCMPXCHG_RegOff_Reg_Quad, emitCMPXCHG_RegOff_Reg, emitCMPXCHG8B_RegDisp, emitCMPXCHG8B_RegIdx, emitCMPXCHG8B_RegInd, emitCMPXCHG8B_RegOff, emitCVTSD2SI_Reg_Abs, emitCVTSD2SI_Reg_Reg, emitCVTSD2SI_Reg_RegDisp, emitCVTSD2SI_Reg_RegIdx, emitCVTSD2SI_Reg_RegInd, emitCVTSD2SI_Reg_RegOff, emitCVTSD2SIQ_Reg_Abs_Quad, emitCVTSD2SIQ_Reg_Reg_Quad, emitCVTSD2SIQ_Reg_RegDisp_Quad, emitCVTSD2SIQ_Reg_RegIdx_Quad, emitCVTSD2SIQ_Reg_RegInd_Quad, emitCVTSD2SIQ_Reg_RegOff_Quad, emitCVTSD2SS_Reg_Abs, emitCVTSD2SS_Reg_Reg, emitCVTSD2SS_Reg_RegDisp, emitCVTSD2SS_Reg_RegIdx, emitCVTSD2SS_Reg_RegInd, emitCVTSD2SS_Reg_RegOff, emitCVTSI2SD_Reg_Abs, emitCVTSI2SD_Reg_Reg, emitCVTSI2SD_Reg_RegDisp, emitCVTSI2SD_Reg_RegIdx, emitCVTSI2SD_Reg_RegInd, emitCVTSI2SD_Reg_RegOff, emitCVTSI2SDQ_Reg_Abs_Quad, emitCVTSI2SDQ_Reg_Reg_Quad, emitCVTSI2SDQ_Reg_RegDisp_Quad, emitCVTSI2SDQ_Reg_RegIdx_Quad, emitCVTSI2SDQ_Reg_RegInd_Quad, emitCVTSI2SDQ_Reg_RegOff_Quad, emitCVTSI2SS_Reg_Abs_Quad, emitCVTSI2SS_Reg_Abs, emitCVTSI2SS_Reg_Reg_Quad, emitCVTSI2SS_Reg_Reg, emitCVTSI2SS_Reg_RegDisp_Quad, emitCVTSI2SS_Reg_RegDisp, emitCVTSI2SS_Reg_RegIdx_Quad, emitCVTSI2SS_Reg_RegIdx, emitCVTSI2SS_Reg_RegInd_Quad, emitCVTSI2SS_Reg_RegInd, emitCVTSI2SS_Reg_RegOff_Quad, emitCVTSI2SS_Reg_RegOff, emitCVTSS2SD_Reg_Abs, emitCVTSS2SD_Reg_Reg, emitCVTSS2SD_Reg_RegDisp, emitCVTSS2SD_Reg_RegIdx, emitCVTSS2SD_Reg_RegInd, emitCVTSS2SD_Reg_RegOff, emitCVTSS2SI_Reg_Abs_Quad, emitCVTSS2SI_Reg_Abs, emitCVTSS2SI_Reg_Reg_Quad, emitCVTSS2SI_Reg_Reg, emitCVTSS2SI_Reg_RegDisp_Quad, emitCVTSS2SI_Reg_RegDisp, emitCVTSS2SI_Reg_RegIdx_Quad, emitCVTSS2SI_Reg_RegIdx, emitCVTSS2SI_Reg_RegInd_Quad, emitCVTSS2SI_Reg_RegInd, emitCVTSS2SI_Reg_RegOff_Quad, emitCVTSS2SI_Reg_RegOff, emitCVTTSD2SI_Reg_Abs, emitCVTTSD2SI_Reg_Reg, emitCVTTSD2SI_Reg_RegDisp, emitCVTTSD2SI_Reg_RegIdx, emitCVTTSD2SI_Reg_RegInd, emitCVTTSD2SI_Reg_RegOff, emitCVTTSD2SIQ_Reg_Abs_Quad, emitCVTTSD2SIQ_Reg_Reg_Quad, emitCVTTSD2SIQ_Reg_RegDisp_Quad, emitCVTTSD2SIQ_Reg_RegIdx_Quad, emitCVTTSD2SIQ_Reg_RegInd_Quad, emitCVTTSD2SIQ_Reg_RegOff_Quad, emitCVTTSS2SI_Reg_Abs_Quad, emitCVTTSS2SI_Reg_Abs, emitCVTTSS2SI_Reg_Reg_Quad, emitCVTTSS2SI_Reg_Reg, emitCVTTSS2SI_Reg_RegDisp_Quad, emitCVTTSS2SI_Reg_RegDisp, emitCVTTSS2SI_Reg_RegIdx_Quad, emitCVTTSS2SI_Reg_RegIdx, emitCVTTSS2SI_Reg_RegInd_Quad, emitCVTTSS2SI_Reg_RegInd, emitCVTTSS2SI_Reg_RegOff_Quad, emitCVTTSS2SI_Reg_RegOff, emitDEC_Abs_Byte, emitDEC_Abs_Quad, emitDEC_Abs_Word, emitDEC_Abs, emitDEC_Reg_Byte, emitDEC_Reg_Quad, emitDEC_Reg_Word, emitDEC_Reg, emitDEC_RegDisp_Byte, emitDEC_RegDisp_Quad, emitDEC_RegDisp_Word, emitDEC_RegDisp, emitDEC_RegIdx_Byte, emitDEC_RegIdx_Quad, emitDEC_RegIdx_Word, emitDEC_RegIdx, emitDEC_RegInd_Byte, emitDEC_RegInd_Quad, emitDEC_RegInd_Word, emitDEC_RegInd, emitDEC_RegOff_Byte, emitDEC_RegOff_Quad, emitDEC_RegOff_Word, emitDEC_RegOff, emitDIV_Reg_Abs_Quad, emitDIV_Reg_Abs, emitDIV_Reg_Reg_Quad, emitDIV_Reg_Reg, emitDIV_Reg_RegDisp_Quad, emitDIV_Reg_RegDisp, emitDIV_Reg_RegIdx_Quad, emitDIV_Reg_RegIdx, emitDIV_Reg_RegInd_Quad, emitDIV_Reg_RegInd, emitDIV_Reg_RegOff_Quad, emitDIV_Reg_RegOff, emitDIVSD_Reg_Abs, emitDIVSD_Reg_Reg, emitDIVSD_Reg_RegDisp, emitDIVSD_Reg_RegIdx, emitDIVSD_Reg_RegInd, emitDIVSD_Reg_RegOff, emitDIVSS_Reg_Abs, emitDIVSS_Reg_Reg, emitDIVSS_Reg_RegDisp, emitDIVSS_Reg_RegIdx, emitDIVSS_Reg_RegInd, emitDIVSS_Reg_RegOff, emitEMMS, emitENTER_Imm, emitFADD_Reg_Abs_Quad, emitFADD_Reg_Abs, emitFADD_Reg_Reg, emitFADD_Reg_RegDisp_Quad, emitFADD_Reg_RegDisp, emitFADD_Reg_RegIdx_Quad, emitFADD_Reg_RegIdx, emitFADD_Reg_RegInd_Quad, emitFADD_Reg_RegInd, emitFADD_Reg_RegOff_Quad, emitFADD_Reg_RegOff, emitFADDP_Reg_Reg, emitFCHS, emitFCMOV_Cond_Reg_Reg, emitFCOMI_Reg_Reg, emitFCOMIP_Reg_Reg, emitFDIV_Reg_Abs_Quad, emitFDIV_Reg_Abs, emitFDIV_Reg_Reg, emitFDIV_Reg_RegDisp_Quad, emitFDIV_Reg_RegDisp, emitFDIV_Reg_RegIdx_Quad, emitFDIV_Reg_RegIdx, emitFDIV_Reg_RegInd_Quad, emitFDIV_Reg_RegInd, emitFDIV_Reg_RegOff_Quad, emitFDIV_Reg_RegOff, emitFDIVP_Reg_Reg, emitFDIVR_Reg_Abs_Quad, emitFDIVR_Reg_Abs, emitFDIVR_Reg_Reg, emitFDIVR_Reg_RegDisp_Quad, emitFDIVR_Reg_RegDisp, emitFDIVR_Reg_RegIdx_Quad, emitFDIVR_Reg_RegIdx, emitFDIVR_Reg_RegInd_Quad, emitFDIVR_Reg_RegInd, emitFDIVR_Reg_RegOff_Quad, emitFDIVR_Reg_RegOff, emitFDIVRP_Reg_Reg, emitFFREE_Reg, emitFIADD_Reg_Abs_Word, emitFIADD_Reg_Abs, emitFIADD_Reg_RegDisp_Word, emitFIADD_Reg_RegDisp, emitFIADD_Reg_RegIdx_Word, emitFIADD_Reg_RegIdx, emitFIADD_Reg_RegInd_Word, emitFIADD_Reg_RegInd, emitFIADD_Reg_RegOff_Word, emitFIADD_Reg_RegOff, emitFIDIV_Reg_Abs_Word, emitFIDIV_Reg_Abs, emitFIDIV_Reg_RegDisp_Word, emitFIDIV_Reg_RegDisp, emitFIDIV_Reg_RegIdx_Word, emitFIDIV_Reg_RegIdx, emitFIDIV_Reg_RegInd_Word, emitFIDIV_Reg_RegInd, emitFIDIV_Reg_RegOff_Word, emitFIDIV_Reg_RegOff, emitFIDIVR_Reg_Abs_Word, emitFIDIVR_Reg_Abs, emitFIDIVR_Reg_RegDisp_Word, emitFIDIVR_Reg_RegDisp, emitFIDIVR_Reg_RegIdx_Word, emitFIDIVR_Reg_RegIdx, emitFIDIVR_Reg_RegInd_Word, emitFIDIVR_Reg_RegInd, emitFIDIVR_Reg_RegOff_Word, emitFIDIVR_Reg_RegOff, emitFILD_Reg_Abs_Quad, emitFILD_Reg_Abs_Word, emitFILD_Reg_Abs, emitFILD_Reg_RegDisp_Quad, emitFILD_Reg_RegDisp_Word, emitFILD_Reg_RegDisp, emitFILD_Reg_RegIdx_Quad, emitFILD_Reg_RegIdx_Word, emitFILD_Reg_RegIdx, emitFILD_Reg_RegInd_Quad, emitFILD_Reg_RegInd_Word, emitFILD_Reg_RegInd, emitFILD_Reg_RegOff_Quad, emitFILD_Reg_RegOff_Word, emitFILD_Reg_RegOff, emitFIMUL_Reg_Abs_Word, emitFIMUL_Reg_Abs, emitFIMUL_Reg_RegDisp_Word, emitFIMUL_Reg_RegDisp, emitFIMUL_Reg_RegIdx_Word, emitFIMUL_Reg_RegIdx, emitFIMUL_Reg_RegInd_Word, emitFIMUL_Reg_RegInd, emitFIMUL_Reg_RegOff_Word, emitFIMUL_Reg_RegOff, emitFINIT, emitFIST_Abs_Reg_Word, emitFIST_Abs_Reg, emitFIST_RegDisp_Reg_Word, emitFIST_RegDisp_Reg, emitFIST_RegIdx_Reg_Word, emitFIST_RegIdx_Reg, emitFIST_RegInd_Reg_Word, emitFIST_RegInd_Reg, emitFIST_RegOff_Reg_Word, emitFIST_RegOff_Reg, emitFISTP_Abs_Reg_Quad, emitFISTP_Abs_Reg_Word, emitFISTP_Abs_Reg, emitFISTP_RegDisp_Reg_Quad, emitFISTP_RegDisp_Reg_Word, emitFISTP_RegDisp_Reg, emitFISTP_RegIdx_Reg_Quad, emitFISTP_RegIdx_Reg_Word, emitFISTP_RegIdx_Reg, emitFISTP_RegInd_Reg_Quad, emitFISTP_RegInd_Reg_Word, emitFISTP_RegInd_Reg, emitFISTP_RegOff_Reg_Quad, emitFISTP_RegOff_Reg_Word, emitFISTP_RegOff_Reg, emitFISUB_Reg_Abs_Word, emitFISUB_Reg_Abs, emitFISUB_Reg_RegDisp_Word, emitFISUB_Reg_RegDisp, emitFISUB_Reg_RegIdx_Word, emitFISUB_Reg_RegIdx, emitFISUB_Reg_RegInd_Word, emitFISUB_Reg_RegInd, emitFISUB_Reg_RegOff_Word, emitFISUB_Reg_RegOff, emitFISUBR_Reg_Abs_Word, emitFISUBR_Reg_Abs, emitFISUBR_Reg_RegDisp_Word, emitFISUBR_Reg_RegDisp, emitFISUBR_Reg_RegIdx_Word, emitFISUBR_Reg_RegIdx, emitFISUBR_Reg_RegInd_Word, emitFISUBR_Reg_RegInd, emitFISUBR_Reg_RegOff_Word, emitFISUBR_Reg_RegOff, emitFLD_Reg_Abs_Quad, emitFLD_Reg_Abs, emitFLD_Reg_Reg, emitFLD_Reg_RegDisp_Quad, emitFLD_Reg_RegDisp, emitFLD_Reg_RegIdx_Quad, emitFLD_Reg_RegIdx, emitFLD_Reg_RegInd_Quad, emitFLD_Reg_RegInd, emitFLD_Reg_RegOff_Quad, emitFLD_Reg_RegOff, emitFLD1_Reg, emitFLDCW_Abs, emitFLDCW_RegDisp, emitFLDCW_RegIdx, emitFLDCW_RegInd, emitFLDCW_RegOff, emitFLDL2E_Reg, emitFLDL2T_Reg, emitFLDLG2_Reg, emitFLDLN2_Reg, emitFLDPI_Reg, emitFLDZ_Reg, emitFMUL_Reg_Abs_Quad, emitFMUL_Reg_Abs, emitFMUL_Reg_Reg, emitFMUL_Reg_RegDisp_Quad, emitFMUL_Reg_RegDisp, emitFMUL_Reg_RegIdx_Quad, emitFMUL_Reg_RegIdx, emitFMUL_Reg_RegInd_Quad, emitFMUL_Reg_RegInd, emitFMUL_Reg_RegOff_Quad, emitFMUL_Reg_RegOff, emitFMULP_Reg_Reg, emitFNINIT, emitFNSAVE_Abs, emitFNSAVE_RegDisp, emitFNSAVE_RegIdx, emitFNSAVE_RegInd, emitFNSAVE_RegOff, emitFNSTCW_Abs, emitFNSTCW_RegDisp, emitFNSTCW_RegIdx, emitFNSTCW_RegInd, emitFNSTCW_RegOff, emitFNSTSW, emitFPREM, emitFRSTOR_Abs, emitFRSTOR_RegDisp, emitFRSTOR_RegIdx, emitFRSTOR_RegInd, emitFRSTOR_RegOff, emitFSAVE_Abs, emitFSAVE_RegDisp, emitFSAVE_RegIdx, emitFSAVE_RegInd, emitFSAVE_RegOff, emitFST_Abs_Reg_Quad, emitFST_Abs_Reg, emitFST_Reg_Reg, emitFST_RegDisp_Reg_Quad, emitFST_RegDisp_Reg, emitFST_RegIdx_Reg_Quad, emitFST_RegIdx_Reg, emitFST_RegInd_Reg_Quad, emitFST_RegInd_Reg, emitFST_RegOff_Reg_Quad, emitFST_RegOff_Reg, emitFSTCW_Abs, emitFSTCW_RegDisp, emitFSTCW_RegIdx, emitFSTCW_RegInd, emitFSTCW_RegOff, emitFSTP_Abs_Reg_Quad, emitFSTP_Abs_Reg, emitFSTP_Reg_Reg, emitFSTP_RegDisp_Reg_Quad, emitFSTP_RegDisp_Reg, emitFSTP_RegIdx_Reg_Quad, emitFSTP_RegIdx_Reg, emitFSTP_RegInd_Reg_Quad, emitFSTP_RegInd_Reg, emitFSTP_RegOff_Reg_Quad, emitFSTP_RegOff_Reg, emitFSUB_Reg_Abs_Quad, emitFSUB_Reg_Abs, emitFSUB_Reg_Reg, emitFSUB_Reg_RegDisp_Quad, emitFSUB_Reg_RegDisp, emitFSUB_Reg_RegIdx_Quad, emitFSUB_Reg_RegIdx, emitFSUB_Reg_RegInd_Quad, emitFSUB_Reg_RegInd, emitFSUB_Reg_RegOff_Quad, emitFSUB_Reg_RegOff, emitFSUBP_Reg_Reg, emitFSUBR_Reg_Abs_Quad, emitFSUBR_Reg_Abs, emitFSUBR_Reg_Reg, emitFSUBR_Reg_RegDisp_Quad, emitFSUBR_Reg_RegDisp, emitFSUBR_Reg_RegIdx_Quad, emitFSUBR_Reg_RegIdx, emitFSUBR_Reg_RegInd_Quad, emitFSUBR_Reg_RegInd, emitFSUBR_Reg_RegOff_Quad, emitFSUBR_Reg_RegOff, emitFSUBRP_Reg_Reg, emitFUCOMI_Reg_Reg, emitFUCOMIP_Reg_Reg, emitFUCOMPP, emitFXCH_Reg_Reg, emitIDIV_Reg_Abs_Quad, emitIDIV_Reg_Abs, emitIDIV_Reg_Reg_Quad, emitIDIV_Reg_Reg, emitIDIV_Reg_RegDisp_Quad, emitIDIV_Reg_RegDisp, emitIDIV_Reg_RegIdx_Quad, emitIDIV_Reg_RegIdx, emitIDIV_Reg_RegInd_Quad, emitIDIV_Reg_RegInd, emitIDIV_Reg_RegOff_Quad, emitIDIV_Reg_RegOff, emitIMUL1_Reg_Abs_Quad, emitIMUL1_Reg_Abs, emitIMUL1_Reg_Reg_Quad, emitIMUL1_Reg_Reg, emitIMUL1_Reg_RegDisp_Quad, emitIMUL1_Reg_RegDisp, emitIMUL1_Reg_RegIdx_Quad, emitIMUL1_Reg_RegIdx, emitIMUL1_Reg_RegInd_Quad, emitIMUL1_Reg_RegInd, emitIMUL1_Reg_RegOff_Quad, emitIMUL1_Reg_RegOff, emitIMUL2_Reg_Abs_Quad, emitIMUL2_Reg_Abs, emitIMUL2_Reg_Imm_Quad, emitIMUL2_Reg_Imm, emitIMUL2_Reg_Reg_Quad, emitIMUL2_Reg_Reg, emitIMUL2_Reg_RegDisp_Quad, emitIMUL2_Reg_RegDisp, emitIMUL2_Reg_RegIdx_Quad, emitIMUL2_Reg_RegIdx, emitIMUL2_Reg_RegInd_Quad, emitIMUL2_Reg_RegInd, emitIMUL2_Reg_RegOff_Quad, emitIMUL2_Reg_RegOff, emitINC_Abs_Byte, emitINC_Abs_Quad, emitINC_Abs_Word, emitINC_Abs, emitINC_Reg_Byte, emitINC_Reg_Quad, emitINC_Reg_Word, emitINC_Reg, emitINC_RegDisp_Byte, emitINC_RegDisp_Quad, emitINC_RegDisp_Word, emitINC_RegDisp, emitINC_RegIdx_Byte, emitINC_RegIdx_Quad, emitINC_RegIdx_Word, emitINC_RegIdx, emitINC_RegInd_Byte, emitINC_RegInd_Quad, emitINC_RegInd_Word, emitINC_RegInd, emitINC_RegOff_Byte, emitINC_RegOff_Quad, emitINC_RegOff_Word, emitINC_RegOff, emitINT_Imm, emitJCC_Cond_Imm, emitJCC_Cond_ImmOrLabel, emitJCC_Cond_Label, emitJMP_Abs, emitJMP_Imm, emitJMP_ImmOrLabel, emitJMP_Label, emitJMP_Reg, emitJMP_RegDisp, emitJMP_RegIdx, emitJMP_RegInd, emitJMP_RegOff, emitLEA_Reg_Abs_Quad, emitLEA_Reg_Abs, emitLEA_Reg_RegDisp_Quad, emitLEA_Reg_RegDisp, emitLEA_Reg_RegIdx_Quad, emitLEA_Reg_RegIdx, emitLEA_Reg_RegInd_Quad, emitLEA_Reg_RegInd, emitLEA_Reg_RegOff_Quad, emitLEA_Reg_RegOff, emitLockNextInstruction, emitMETHODSTART_Reg, emitMOV_Abs_Imm_Byte, emitMOV_Abs_Imm_Quad, emitMOV_Abs_Imm_Word, emitMOV_Abs_Imm, emitMOV_Abs_Reg_Byte, emitMOV_Abs_Reg_Quad, emitMOV_Abs_Reg_Word, emitMOV_Abs_Reg, emitMOV_Reg_Abs_Byte, emitMOV_Reg_Abs_Quad, emitMOV_Reg_Abs_Word, emitMOV_Reg_Abs, emitMOV_Reg_Imm_Quad, emitMOV_Reg_Imm, emitMOV_Reg_Reg_Byte, emitMOV_Reg_Reg_Quad, emitMOV_Reg_Reg_Word, emitMOV_Reg_Reg, emitMOV_Reg_RegDisp_Byte, emitMOV_Reg_RegDisp_Quad, emitMOV_Reg_RegDisp_Word, emitMOV_Reg_RegDisp, emitMOV_Reg_RegIdx_Byte, emitMOV_Reg_RegIdx_Quad, emitMOV_Reg_RegIdx_Word, emitMOV_Reg_RegIdx, emitMOV_Reg_RegInd_Byte, emitMOV_Reg_RegInd_Quad, emitMOV_Reg_RegInd_Word, emitMOV_Reg_RegInd, emitMOV_Reg_RegOff_Byte, emitMOV_Reg_RegOff_Quad, emitMOV_Reg_RegOff_Word, emitMOV_Reg_RegOff, emitMOV_RegDisp_Imm_Byte, emitMOV_RegDisp_Imm_Quad, emitMOV_RegDisp_Imm_Word, emitMOV_RegDisp_Imm, emitMOV_RegDisp_Reg_Byte, emitMOV_RegDisp_Reg_Quad, emitMOV_RegDisp_Reg_Word, emitMOV_RegDisp_Reg, emitMOV_RegIdx_Imm_Byte, emitMOV_RegIdx_Imm_Quad, emitMOV_RegIdx_Imm_Word, emitMOV_RegIdx_Imm, emitMOV_RegIdx_Reg_Byte, emitMOV_RegIdx_Reg_Quad, emitMOV_RegIdx_Reg_Word, emitMOV_RegIdx_Reg, emitMOV_RegInd_Imm_Byte, emitMOV_RegInd_Imm_Quad, emitMOV_RegInd_Imm_Word, emitMOV_RegInd_Imm, emitMOV_RegInd_Reg_Byte, emitMOV_RegInd_Reg_Quad, emitMOV_RegInd_Reg_Word, emitMOV_RegInd_Reg, emitMOV_RegOff_Imm_Byte, emitMOV_RegOff_Imm_Quad, emitMOV_RegOff_Imm_Word, emitMOV_RegOff_Imm, emitMOV_RegOff_Reg_Byte, emitMOV_RegOff_Reg_Quad, emitMOV_RegOff_Reg_Word, emitMOV_RegOff_Reg, emitMOVD_Abs_Reg, emitMOVD_Abs_Reg, emitMOVD_Reg_Abs, emitMOVD_Reg_Abs, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_Reg, emitMOVD_Reg_RegDisp, emitMOVD_Reg_RegDisp, emitMOVD_Reg_RegIdx, emitMOVD_Reg_RegIdx, emitMOVD_Reg_RegInd, emitMOVD_Reg_RegInd, emitMOVD_Reg_RegOff, emitMOVD_Reg_RegOff, emitMOVD_RegDisp_Reg, emitMOVD_RegDisp_Reg, emitMOVD_RegIdx_Reg, emitMOVD_RegIdx_Reg, emitMOVD_RegInd_Reg, emitMOVD_RegInd_Reg, emitMOVD_RegOff_Reg, emitMOVD_RegOff_Reg, emitMOVLPD_Abs_Reg, emitMOVLPD_Reg_Abs, emitMOVLPD_Reg_Reg, emitMOVLPD_Reg_RegDisp, emitMOVLPD_Reg_RegIdx, emitMOVLPD_Reg_RegInd, emitMOVLPD_Reg_RegOff, emitMOVLPD_RegDisp_Reg, emitMOVLPD_RegIdx_Reg, emitMOVLPD_RegInd_Reg, emitMOVLPD_RegOff_Reg, emitMOVLPS_Abs_Reg, emitMOVLPS_Reg_Abs, emitMOVLPS_Reg_Reg, emitMOVLPS_Reg_RegDisp, emitMOVLPS_Reg_RegIdx, emitMOVLPS_Reg_RegInd, emitMOVLPS_Reg_RegOff, emitMOVLPS_RegDisp_Reg, emitMOVLPS_RegIdx_Reg, emitMOVLPS_RegInd_Reg, emitMOVLPS_RegOff_Reg, emitMOVQ_Abs_Reg, emitMOVQ_Abs_Reg, emitMOVQ_Reg_Abs, emitMOVQ_Reg_Abs, emitMOVQ_Reg_Reg, emitMOVQ_Reg_Reg, emitMOVQ_Reg_RegDisp, emitMOVQ_Reg_RegDisp, emitMOVQ_Reg_RegIdx, emitMOVQ_Reg_RegIdx, emitMOVQ_Reg_RegInd, emitMOVQ_Reg_RegInd, emitMOVQ_Reg_RegOff, emitMOVQ_Reg_RegOff, emitMOVQ_RegDisp_Reg, emitMOVQ_RegDisp_Reg, emitMOVQ_RegIdx_Reg, emitMOVQ_RegIdx_Reg, emitMOVQ_RegInd_Reg, emitMOVQ_RegInd_Reg, emitMOVQ_RegOff_Reg, emitMOVQ_RegOff_Reg, emitMOVSD_Abs_Reg, emitMOVSD_Reg_Abs, emitMOVSD_Reg_Reg, emitMOVSD_Reg_RegDisp, emitMOVSD_Reg_RegIdx, emitMOVSD_Reg_RegInd, emitMOVSD_Reg_RegOff, emitMOVSD_RegDisp_Reg, emitMOVSD_RegIdx_Reg, emitMOVSD_RegInd_Reg, emitMOVSD_RegOff_Reg, emitMOVSS_Abs_Reg, emitMOVSS_Reg_Abs, emitMOVSS_Reg_Reg, emitMOVSS_Reg_RegDisp, emitMOVSS_Reg_RegIdx, emitMOVSS_Reg_RegInd, emitMOVSS_Reg_RegOff, emitMOVSS_RegDisp_Reg, emitMOVSS_RegIdx_Reg, emitMOVSS_RegInd_Reg, emitMOVSS_RegOff_Reg, emitMOVSX_Reg_Abs_Byte, emitMOVSX_Reg_Abs_Word, emitMOVSX_Reg_Reg_Byte, emitMOVSX_Reg_Reg_Word, emitMOVSX_Reg_RegDisp_Byte, emitMOVSX_Reg_RegDisp_Word, emitMOVSX_Reg_RegIdx_Byte, emitMOVSX_Reg_RegIdx_Word, emitMOVSX_Reg_RegInd_Byte, emitMOVSX_Reg_RegInd_Word, emitMOVSX_Reg_RegOff_Byte, emitMOVSX_Reg_RegOff_Word, emitMOVSXQ_Reg_Abs_Byte, emitMOVSXQ_Reg_Abs_Word, emitMOVSXQ_Reg_Reg_Byte, emitMOVSXQ_Reg_Reg_Word, emitMOVSXQ_Reg_RegDisp_Byte, emitMOVSXQ_Reg_RegDisp_Word, emitMOVSXQ_Reg_RegIdx_Byte, emitMOVSXQ_Reg_RegIdx_Word, emitMOVSXQ_Reg_RegInd_Byte, emitMOVSXQ_Reg_RegInd_Word, emitMOVSXQ_Reg_RegOff_Byte, emitMOVSXQ_Reg_RegOff_Word, emitMOVZX_Reg_Abs_Byte, emitMOVZX_Reg_Abs_Word, emitMOVZX_Reg_Reg_Byte, emitMOVZX_Reg_Reg_Word, emitMOVZX_Reg_RegDisp_Byte, emitMOVZX_Reg_RegDisp_Word, emitMOVZX_Reg_RegIdx_Byte, emitMOVZX_Reg_RegIdx_Word, emitMOVZX_Reg_RegInd_Byte, emitMOVZX_Reg_RegInd_Word, emitMOVZX_Reg_RegOff_Byte, emitMOVZX_Reg_RegOff_Word, emitMOVZXQ_Reg_Abs_Byte, emitMOVZXQ_Reg_Abs_Word, emitMOVZXQ_Reg_Reg_Byte, emitMOVZXQ_Reg_Reg_Word, emitMOVZXQ_Reg_RegDisp_Byte, emitMOVZXQ_Reg_RegDisp_Word, emitMOVZXQ_Reg_RegIdx_Byte, emitMOVZXQ_Reg_RegIdx_Word, emitMOVZXQ_Reg_RegInd_Byte, emitMOVZXQ_Reg_RegInd_Word, emitMOVZXQ_Reg_RegOff_Byte, emitMOVZXQ_Reg_RegOff_Word, emitMUL_Reg_Abs_Quad, emitMUL_Reg_Abs, emitMUL_Reg_Reg_Quad, emitMUL_Reg_Reg, emitMUL_Reg_RegDisp_Quad, emitMUL_Reg_RegDisp, emitMUL_Reg_RegIdx_Quad, emitMUL_Reg_RegIdx, emitMUL_Reg_RegInd_Quad, emitMUL_Reg_RegInd, emitMUL_Reg_RegOff_Quad, emitMUL_Reg_RegOff, emitMULSD_Reg_Abs, emitMULSD_Reg_Reg, emitMULSD_Reg_RegDisp, emitMULSD_Reg_RegIdx, emitMULSD_Reg_RegInd, emitMULSD_Reg_RegOff, emitMULSS_Reg_Abs, emitMULSS_Reg_Reg, emitMULSS_Reg_RegDisp, emitMULSS_Reg_RegIdx, emitMULSS_Reg_RegInd, emitMULSS_Reg_RegOff, emitNEG_Abs_Byte, emitNEG_Abs_Quad, emitNEG_Abs_Word, emitNEG_Abs, emitNEG_Reg_Byte, emitNEG_Reg_Quad, emitNEG_Reg_Word, emitNEG_Reg, emitNEG_RegDisp_Byte, emitNEG_RegDisp_Quad, emitNEG_RegDisp_Word, emitNEG_RegDisp, emitNEG_RegIdx_Byte, emitNEG_RegIdx_Quad, emitNEG_RegIdx_Word, emitNEG_RegIdx, emitNEG_RegInd_Byte, emitNEG_RegInd_Quad, emitNEG_RegInd_Word, emitNEG_RegInd, emitNEG_RegOff_Byte, emitNEG_RegOff_Quad, emitNEG_RegOff_Word, emitNEG_RegOff, emitNOP, emitNOT_Abs_Byte, emitNOT_Abs_Quad, emitNOT_Abs_Word, emitNOT_Abs, emitNOT_Reg_Byte, emitNOT_Reg_Quad, emitNOT_Reg_Word, emitNOT_Reg, emitNOT_RegDisp_Byte, emitNOT_RegDisp_Quad, emitNOT_RegDisp_Word, emitNOT_RegDisp, emitNOT_RegIdx_Byte, emitNOT_RegIdx_Quad, emitNOT_RegIdx_Word, emitNOT_RegIdx, emitNOT_RegInd_Byte,