org.jikesrvm.compilers.common.assembler.ia32
Class Assembler

java.lang.Object
  org.jikesrvm.compilers.common.assembler.AbstractAssembler
      org.jikesrvm.compilers.common.assembler.ia32.Assembler

All Implemented Interfaces:

AssemblerConstants, RegisterConstants

Direct Known Subclasses:

ArchitectureSpecific.Assembler

public abstract class Assembler
extends AbstractAssembler
implements RegisterConstants, AssemblerConstants

This class is the low-level assembler for Intel; it contains functionality for encoding specific instructions into an array of bytes. It consists of three parts:

• Some support that handles common operations for generating any IA32 instruction, such as encoding the operands into the ModRM and SIB bytes
• Some hand-coded methods that emit instructions with distinctive formats or with special consistency requirements, such as FXCH or CMOV
• Machine-generated methods that emit instructions with relatively standard formats, such as binary accumulation instructions like ADD and SUB.

This assembler provides a direct interface to the IA32 ISA: it contains emit methods that generate specific IA32 opcodes, and each emit method specifies the addressing modes and operand sizes that it expects. Thus, it has an emit method that generates an ADD of a register-displacement operand and an immediate operand. It is the job of the client to determine the addressing modes, operand sizes and exact opcodes that it desires.

This assembler does provide support for forward branches. It is permitted to specify a branch operand as an arbitrary label, and later to inform the assembler to which instruction this label refers. The assembler, when informed to what the label refers, will go back and generate the appropriate offsets for all branches that refer to the given label. The mechanism is implemented by the following methods and helper classes:

• forwardRefs
• resolveForwardReferences(int)
• patchUnconditionalBranch(int)
• patchConditionalBranch(int)
• emitJCC_Cond_Label(byte, int)
• emitJMP_Label(int)
• emitCALL_Label(int)
• ForwardReference

There is also support for generating tableswitches. This consists providing support for storing tables of relative addresses that can be used to compute the target of a tableswitch. This support assumes a particular code sequence for tableswitches (followed by baseline and optimizing compilers). See emitOFFSET_Imm_ImmOrLabel(int, int, int) for details.

The automatically-generated emit methods of this assembler exploit regularities in the IA32 binary encoding; for example, several instructions (ADD, ADC, SUB, AND, OR, XOR) can be classified as binary accumulators that share a common set of permitted addressing modes and binary encoding all the way down a special case for enconding operands EAX and an immediate. A shell script (genAssembler.sh in the intel assembler source directory) explots this by specifying a generic way of emtting a binary accumulation and then calling it for each specific opcode that fits that format. These generated methods are combined with the hand-coded ones (from Assembler.in, also in the assembler source directory) as part of the Jikes RVM build process.

This assembler is shared by the baseline and optimizing compilers: it used directly by the baseline compiler, while the optimizing compiler has an ArchitectureSpecificOpt.AssemblerOpt that is built on top of this one to match Instructions and Operators to the emit methods this assembler provides. The ArchitectureSpecificOpt.AssemblerOpt is entirely machine-generated, and this requires that the methods for encoding instructions use a stylized naming and signiture convention that is designed to make the method signiture computable from the opcode and the operand types. The naming convention is as follows:

   final void emitopcode\(_operand code\)*[_size](\(operand arguments\)*)
 

opcode is the opcode of the instruction (e.g. ADC, MOV, etc)

operand code represents the type of the nth operand:

"Imm" immediate operands

"Reg" register operands

"RegInd" register indirect operands

"RegDisp" register displacement

"RegOff" shifted index + displacement

"RegIdx" register base + shifted index + displacement

"Cond" condition codes

size indicates non-word-sized operations

"Byte" bytes

"Word" Intel "words" (i.e. 16 bites)

"Quad" quad words (i.e. double-precision floating point)

operand arguments are the needed components of the operands, in order

"Imm"

• immediate value (int)

"Reg"

• register number (byte)

"RegInd"

• register number (byte)

"RegDisp"

• register number (byte)
• displacement (int)

"RegOff"

• index register (byte)
• scale (short)
• displacement (int)

"RegIdx"

• base register (byte)
• index register (byte)
• scale (short)
• displacement (int)

"Cond"

• condition code mask (byte)

See Also:

ArchitectureSpecificOpt.AssemblerOpt, Lister, ForwardReference